obs266_machdep.c revision 1.27 1 1.27 rin /* $NetBSD: obs266_machdep.c,v 1.27 2021/08/03 09:25:44 rin Exp $ */
2 1.1 shige /* Original: md_machdep.c,v 1.3 2005/01/24 18:47:37 shige Exp $ */
3 1.1 shige
4 1.1 shige /*
5 1.1 shige * Copyright 2001, 2002 Wasabi Systems, Inc.
6 1.1 shige * All rights reserved.
7 1.1 shige *
8 1.1 shige * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
9 1.1 shige *
10 1.1 shige * Redistribution and use in source and binary forms, with or without
11 1.1 shige * modification, are permitted provided that the following conditions
12 1.1 shige * are met:
13 1.1 shige * 1. Redistributions of source code must retain the above copyright
14 1.1 shige * notice, this list of conditions and the following disclaimer.
15 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 shige * notice, this list of conditions and the following disclaimer in the
17 1.1 shige * documentation and/or other materials provided with the distribution.
18 1.1 shige * 3. All advertising materials mentioning features or use of this software
19 1.1 shige * must display the following acknowledgement:
20 1.1 shige * This product includes software developed for the NetBSD Project by
21 1.1 shige * Wasabi Systems, Inc.
22 1.1 shige * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23 1.1 shige * or promote products derived from this software without specific prior
24 1.1 shige * written permission.
25 1.1 shige *
26 1.1 shige * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27 1.1 shige * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 shige * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 shige * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30 1.1 shige * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 shige * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 shige * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 shige * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 shige * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 shige * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 shige * POSSIBILITY OF SUCH DAMAGE.
37 1.1 shige */
38 1.1 shige
39 1.1 shige /*
40 1.1 shige * Copyright (C) 1995, 1996 Wolfgang Solfrank.
41 1.1 shige * Copyright (C) 1995, 1996 TooLs GmbH.
42 1.1 shige * All rights reserved.
43 1.1 shige *
44 1.1 shige * Redistribution and use in source and binary forms, with or without
45 1.1 shige * modification, are permitted provided that the following conditions
46 1.1 shige * are met:
47 1.1 shige * 1. Redistributions of source code must retain the above copyright
48 1.1 shige * notice, this list of conditions and the following disclaimer.
49 1.1 shige * 2. Redistributions in binary form must reproduce the above copyright
50 1.1 shige * notice, this list of conditions and the following disclaimer in the
51 1.1 shige * documentation and/or other materials provided with the distribution.
52 1.1 shige * 3. All advertising materials mentioning features or use of this software
53 1.1 shige * must display the following acknowledgement:
54 1.1 shige * This product includes software developed by TooLs GmbH.
55 1.1 shige * 4. The name of TooLs GmbH may not be used to endorse or promote products
56 1.1 shige * derived from this software without specific prior written permission.
57 1.1 shige *
58 1.1 shige * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
59 1.1 shige * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
60 1.1 shige * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
61 1.1 shige * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
62 1.1 shige * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
63 1.1 shige * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
64 1.1 shige * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
65 1.1 shige * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
66 1.1 shige * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
67 1.1 shige * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
68 1.1 shige */
69 1.1 shige
70 1.1 shige #include <sys/cdefs.h>
71 1.27 rin __KERNEL_RCSID(0, "$NetBSD: obs266_machdep.c,v 1.27 2021/08/03 09:25:44 rin Exp $");
72 1.1 shige
73 1.1 shige #include "opt_ddb.h"
74 1.1 shige
75 1.1 shige #include <sys/param.h>
76 1.26 rin #include <sys/bus.h>
77 1.26 rin #include <sys/device.h>
78 1.1 shige #include <sys/kernel.h>
79 1.26 rin #include <sys/module.h>
80 1.1 shige #include <sys/reboot.h>
81 1.1 shige #include <sys/systm.h>
82 1.1 shige
83 1.1 shige #include <machine/obs266.h>
84 1.18 matt
85 1.26 rin #include <powerpc/spr.h>
86 1.26 rin #include <powerpc/ibm4xx/spr.h>
87 1.26 rin
88 1.26 rin #include <powerpc/ibm4xx/cpu.h>
89 1.12 kiyohara #include <powerpc/ibm4xx/dcr4xx.h>
90 1.12 kiyohara #include <powerpc/ibm4xx/ibm405gp.h>
91 1.12 kiyohara #include <powerpc/ibm4xx/openbios.h>
92 1.25 rin #include <powerpc/ibm4xx/tlb.h>
93 1.18 matt
94 1.26 rin #include <powerpc/ibm4xx/pci_machdep.h>
95 1.26 rin #include <dev/pci/pciconf.h>
96 1.4 shige #include <dev/pci/pcivar.h>
97 1.4 shige
98 1.13 kiyohara #include "com.h"
99 1.13 kiyohara #if (NCOM > 0)
100 1.13 kiyohara #include <sys/termios.h>
101 1.26 rin #include <powerpc/ibm4xx/dev/comopbvar.h>
102 1.26 rin #include <dev/ic/comreg.h>
103 1.13 kiyohara
104 1.13 kiyohara #ifndef CONADDR
105 1.13 kiyohara #define CONADDR IBM405GP_UART0_BASE
106 1.13 kiyohara #endif
107 1.13 kiyohara #ifndef CONSPEED
108 1.13 kiyohara #define CONSPEED B9600
109 1.13 kiyohara #endif
110 1.13 kiyohara #ifndef CONMODE
111 1.13 kiyohara /* 8N1 */
112 1.13 kiyohara #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8)
113 1.13 kiyohara #endif
114 1.13 kiyohara #endif /* NCOM */
115 1.5 kiyohara
116 1.5 kiyohara #define TLB_PG_SIZE (16*1024*1024)
117 1.5 kiyohara
118 1.19 matt void initppc(vaddr_t, vaddr_t, char *, void *);
119 1.1 shige
120 1.1 shige void
121 1.19 matt initppc(vaddr_t startkernel, vaddr_t endkernel, char *args, void *info_block)
122 1.1 shige {
123 1.5 kiyohara vaddr_t va;
124 1.1 shige u_int memsize;
125 1.1 shige
126 1.1 shige /* Setup board from OpenBIOS */
127 1.24 rin openbios_board_init(info_block);
128 1.1 shige memsize = openbios_board_memsize_get();
129 1.1 shige
130 1.6 freza /* Linear map kernel memory */
131 1.6 freza for (va = 0; va < endkernel; va += TLB_PG_SIZE)
132 1.5 kiyohara ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
133 1.5 kiyohara
134 1.6 freza /* Map console after RAM (see pmap_tlbmiss()) */
135 1.13 kiyohara ppc4xx_tlb_reserve(CONADDR, roundup(memsize, TLB_PG_SIZE), TLB_PG_SIZE,
136 1.13 kiyohara TLB_I | TLB_G);
137 1.5 kiyohara
138 1.1 shige /* Initialize IBM405GPr CPU */
139 1.1 shige ibm40x_memsize_init(memsize, startkernel);
140 1.19 matt ibm4xx_init(startkernel, endkernel, pic_ext_intr);
141 1.1 shige
142 1.1 shige #ifdef DEBUG
143 1.1 shige openbios_board_print();
144 1.1 shige #endif
145 1.1 shige
146 1.1 shige #ifdef DDB
147 1.1 shige if (boothowto & RB_KDB)
148 1.1 shige Debugger();
149 1.1 shige #endif
150 1.1 shige }
151 1.1 shige
152 1.1 shige void
153 1.1 shige consinit(void)
154 1.1 shige {
155 1.1 shige
156 1.13 kiyohara #if (NCOM > 0)
157 1.13 kiyohara com_opb_cnattach(OBS266_COM_FREQ, CONADDR, CONSPEED, CONMODE);
158 1.13 kiyohara #endif
159 1.1 shige }
160 1.1 shige
161 1.1 shige /*
162 1.1 shige * Machine dependent startup code.
163 1.1 shige */
164 1.1 shige void
165 1.1 shige cpu_startup(void)
166 1.1 shige {
167 1.1 shige
168 1.1 shige /*
169 1.1 shige * cpu common startup
170 1.1 shige */
171 1.1 shige ibm4xx_cpu_startup("OpenBlockS266 IBM PowerPC 405GPr Board");
172 1.1 shige
173 1.1 shige /*
174 1.1 shige * Set up the board properties database.
175 1.1 shige */
176 1.1 shige openbios_board_info_set();
177 1.1 shige
178 1.1 shige /*
179 1.1 shige * Now that we have VM, malloc()s are OK in bus_space.
180 1.1 shige */
181 1.1 shige bus_space_mallocok();
182 1.1 shige
183 1.1 shige /*
184 1.1 shige * no fake mapiodev
185 1.1 shige */
186 1.1 shige fake_mapiodev = 0;
187 1.1 shige }
188 1.1 shige
189 1.4 shige int
190 1.20 matt ibm4xx_pci_bus_maxdevs(void *v, int busno)
191 1.12 kiyohara {
192 1.12 kiyohara
193 1.12 kiyohara /*
194 1.12 kiyohara * Bus number is irrelevant. Configuration Mechanism 1 is in
195 1.12 kiyohara * use, can have devices 0-32 (i.e. the `normal' range).
196 1.12 kiyohara */
197 1.12 kiyohara return 31;
198 1.12 kiyohara }
199 1.12 kiyohara
200 1.12 kiyohara int
201 1.20 matt ibm4xx_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
202 1.4 shige {
203 1.4 shige /*
204 1.4 shige * We need to map the interrupt pin to the interrupt bit
205 1.4 shige * in the UIC associated with it.
206 1.4 shige *
207 1.4 shige * This platform has 4 PCI devices.
208 1.4 shige *
209 1.4 shige # External IRQ Mappings:
210 1.4 shige * dev 1 (Ext IRQ3): PCI Connector
211 1.4 shige * dev 2 (Ext IRQ4): PCI Connector
212 1.4 shige * dev 3 (Ext IRQ5): HPT IDE Controller
213 1.4 shige * dev 4 (Ext IRQ6): Davicom Ethernet
214 1.4 shige */
215 1.4 shige static const int irqmap[4/*device*/][4/*pin*/] = {
216 1.4 shige { 3, 3, 3, 3 }, /* 1: PCI Connector 1 */
217 1.4 shige { 4, 4, 4, 4 }, /* 2: PCI Connector 2 */
218 1.4 shige { 5, 5, -1, -1 }, /* 3: HPT IDE Controller */
219 1.4 shige { 6, 6, -1, -1 }, /* 4: Damicom Ethernet */
220 1.4 shige };
221 1.4 shige
222 1.4 shige int pin, dev, irq;
223 1.4 shige
224 1.4 shige pin = pa->pa_intrpin;
225 1.4 shige dev = pa->pa_device;
226 1.4 shige *ihp = -1;
227 1.4 shige
228 1.4 shige /* if interrupt pin not used... */
229 1.4 shige if (pin == 0)
230 1.4 shige return 1;
231 1.4 shige
232 1.4 shige if (pin > 4) {
233 1.4 shige printf("pci_intr_map: bad interrupt pin %d\n", pin);
234 1.4 shige return 1;
235 1.4 shige }
236 1.4 shige
237 1.4 shige if ((dev < 1) || (dev > 4)) {
238 1.4 shige printf("pci_intr_map: bad device %d\n", dev);
239 1.4 shige return 1;
240 1.4 shige }
241 1.4 shige
242 1.4 shige
243 1.4 shige if ((irq = irqmap[dev - 1][pin - 1]) == -1) {
244 1.4 shige printf("pci_intr_map: no IRQ routing for device %d pin %d\n",
245 1.4 shige dev, pin);
246 1.4 shige return 1;
247 1.4 shige }
248 1.4 shige
249 1.4 shige *ihp = irq + 25;
250 1.4 shige return 0;
251 1.4 shige }
252 1.4 shige
253 1.4 shige void
254 1.20 matt ibm4xx_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
255 1.20 matt int *iline)
256 1.4 shige {
257 1.4 shige
258 1.4 shige static const int ilinemap[4/*device*/] = {
259 1.20 matt 28, 29, 30, 31
260 1.4 shige };
261 1.4 shige
262 1.4 shige if ((dev < 1) || (dev > 4)) {
263 1.20 matt printf("%s: bad device %d\n", __func__, dev);
264 1.4 shige *iline = 0;
265 1.4 shige return;
266 1.4 shige }
267 1.20 matt *iline = ilinemap[dev - 1];
268 1.4 shige }
269