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samfpgareg.h revision 1.1 
      1 /*	$NetBSD: samfpgareg.h,v 1.1 2026/09/28 20:41:00 rkujawa Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2026 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Radoslaw Kujawa.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * FPGA chip on ACube Sam460ex (Lattice XP2).
     34  */
     35 
     36 #ifndef _EVBPPC_SAM460EX_SAMFPGAREG_H_
     37 #define _EVBPPC_SAM460EX_SAMFPGAREG_H_
     38 
     39 #define	SAMFPGA_SIZE		0x40
     40 
     41 /* J22 GPIO */
     42 #define	SAMFPGA_GPIO_NBANK	5
     43 #define	SAMFPGA_GPIO_NPINS	80
     44 #define	SAMFPGA_GPIO_OUT(b)	(0x02 + 2 * (b))	/* output, r/w */
     45 #define	SAMFPGA_GPIO_DIR(b)	(0x0c + 2 * (b))	/* 1 = output */
     46 #define	SAMFPGA_GPIO_IN(b)	(0x20 + 2 * (b))	/* pin level */
     47 #define	SAMFPGA_GPIO_BANK(p)	((p) >> 4)
     48 #define	SAMFPGA_GPIO_BIT(p)	__BIT((p) & 0xf)
     49 
     50 /* FPGA design revision, BCD */
     51 #define	SAMFPGA_REV_DATE	0x2a
     52 #define	 SAMFPGA_REV_DATE_DAY	__BITS(15, 8)
     53 #define	 SAMFPGA_REV_DATE_MONTH	__BITS(7, 0)
     54 #define	SAMFPGA_REV_YEAR	0x2c
     55 #define	 SAMFPGA_REV_YEAR_YEAR	__BITS(15, 8)	/* 20xx */
     56 #define	 SAMFPGA_REV_YEAR_REV	__BITS(7, 0)
     57 
     58 /* Board control */
     59 #define	SAMFPGA_CTL		0x2e
     60 #define	 SAMFPGA_CTL_B0		__BIT(0)	/* ??? */
     61 #define	 SAMFPGA_CTL_LED_RED	__BIT(1)	/* 1 = on */
     62 #define	 SAMFPGA_CTL_LED_YELLOW	__BIT(2)
     63 #define	 SAMFPGA_CTL_LED_AMBER	__BIT(3)
     64 #define	 SAMFPGA_CTL_LEDS	__BITS(3, 1)
     65 #define	 SAMFPGA_CTL_RESET	__BIT(4)	/* pulsed: board reset; held: power off */
     66 
     67 #define	SAMFPGA_USB		0x30		/* ??? U-Boot sets bit 2 */
     68 
     69 #endif	/* _EVBPPC_SAM460EX_SAMFPGAREG_H_ */
     70