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design_gsrd2.c revision 1.2.20.1
      1  1.2.20.1    joerg /* 	$NetBSD: design_gsrd2.c,v 1.2.20.1 2007/10/26 15:42:28 joerg Exp $ */
      2       1.1    freza 
      3       1.1    freza /*
      4       1.1    freza  * Copyright (c) 2006 Jachym Holecek
      5       1.1    freza  * All rights reserved.
      6       1.1    freza  *
      7       1.1    freza  * Written for DFC Design, s.r.o.
      8       1.1    freza  *
      9       1.1    freza  * Redistribution and use in source and binary forms, with or without
     10       1.1    freza  * modification, are permitted provided that the following conditions
     11       1.1    freza  * are met:
     12       1.1    freza  *
     13       1.1    freza  * 1. Redistributions of source code must retain the above copyright
     14       1.1    freza  *    notice, this list of conditions and the following disclaimer.
     15       1.1    freza  *
     16       1.1    freza  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1    freza  *    notice, this list of conditions and the following disclaimer in the
     18       1.1    freza  *    documentation and/or other materials provided with the distribution.
     19       1.1    freza  *
     20       1.1    freza  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21       1.1    freza  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22       1.1    freza  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23       1.1    freza  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24       1.1    freza  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25       1.1    freza  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26       1.1    freza  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27       1.1    freza  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28       1.1    freza  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29       1.1    freza  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30       1.1    freza  */
     31       1.1    freza 
     32       1.1    freza #include "opt_virtex.h"
     33       1.1    freza 
     34       1.1    freza #include <sys/cdefs.h>
     35  1.2.20.1    joerg __KERNEL_RCSID(0, "$NetBSD: design_gsrd2.c,v 1.2.20.1 2007/10/26 15:42:28 joerg Exp $");
     36       1.1    freza 
     37       1.1    freza #include <sys/param.h>
     38       1.1    freza #include <sys/systm.h>
     39       1.1    freza #include <sys/device.h>
     40       1.1    freza #include <sys/kernel.h>
     41       1.1    freza #include <sys/malloc.h>
     42       1.1    freza #include <sys/extent.h>
     43       1.1    freza 
     44       1.1    freza #include <machine/cpu.h>
     45       1.1    freza #include <machine/bus.h>
     46       1.1    freza #include <machine/intr.h>
     47       1.1    freza #include <machine/powerpc.h>
     48       1.1    freza #include <machine/tlb.h>
     49       1.1    freza 
     50       1.1    freza #include <powerpc/ibm4xx/dev/plbvar.h>
     51       1.1    freza 
     52       1.1    freza #include <evbppc/virtex/dev/xcvbusvar.h>
     53       1.1    freza #include <evbppc/virtex/dev/cdmacreg.h>
     54       1.1    freza #include <evbppc/virtex/dev/temacreg.h>
     55       1.1    freza #include <evbppc/virtex/dev/tftreg.h>
     56       1.1    freza 
     57       1.1    freza #include <evbppc/virtex/virtex.h>
     58       1.1    freza #include <evbppc/virtex/dcr.h>
     59       1.1    freza 
     60       1.1    freza 
     61       1.1    freza #define	DCR_TEMAC_BASE 		0x0030
     62       1.1    freza #define	DCR_TFT0_BASE 		0x0082
     63       1.1    freza #define	DCR_TFT1_BASE 		0x0086
     64       1.1    freza #define	DCR_CDMAC_BASE 		0x0140
     65       1.1    freza 
     66       1.1    freza #define OPB_BASE 		0x80000000 	/* below are offsets in opb */
     67       1.1    freza #define OPB_XLCOM_BASE 		0x010000
     68       1.1    freza #define OPB_GPIO_BASE 		0x020000
     69       1.1    freza #define OPB_PSTWO0_BASE 	0x040000
     70       1.1    freza #define OPB_PSTWO1_BASE 	0x041000
     71       1.1    freza #define CDMAC_NCHAN 		2 	/* cdmac {Tx,Rx} */
     72       1.1    freza #define CDMAC_INTR_LINE 	0
     73       1.1    freza 
     74       1.1    freza #define	TFT_FB_BASE 		0x3c00000
     75       1.1    freza #define TFT_FB_SIZE 		(2*1024*1024)
     76       1.1    freza 
     77       1.1    freza /*
     78       1.1    freza  * CDMAC per-channel interrupt handler. CDMAC has one interrupt signal
     79       1.1    freza  * per two channels on mpmc2, so we have to dispatch channels manually.
     80       1.1    freza  *
     81       1.1    freza  * Note: we hardwire priority to IPL_NET, temac(4) is the only device that
     82       1.1    freza  * needs to service DMA interrupts anyway.
     83       1.1    freza  */
     84       1.1    freza typedef struct cdmac_intrhand {
     85       1.1    freza 	void 			(*cih_func)(void *);
     86       1.1    freza 	void 			*cih_arg;
     87       1.1    freza } *cdmac_intrhand_t;
     88       1.1    freza 
     89       1.1    freza /* Two instantiated channels, one logical interrupt per direction. */
     90       1.1    freza static struct cdmac_intrhand 	cdmacintr[CDMAC_NCHAN];
     91       1.1    freza static void 			*cdmac_ih;
     92       1.1    freza 
     93       1.1    freza 
     94       1.1    freza /*
     95       1.1    freza  * DCR bus space leaf access routines.
     96       1.1    freza  */
     97       1.1    freza 
     98       1.1    freza static void
     99       1.1    freza tft0_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
    100       1.1    freza     uint32_t val)
    101       1.1    freza {
    102       1.1    freza 	addr += h;
    103       1.1    freza 
    104       1.1    freza 	switch (addr) {
    105       1.1    freza 	WCASE(DCR_TFT0_BASE, TFT_CTRL);
    106       1.1    freza 	WCASE(DCR_TFT0_BASE, TFT_ADDR);
    107       1.1    freza 	WDEAD(addr);
    108       1.1    freza 	}
    109       1.1    freza }
    110       1.1    freza 
    111       1.1    freza static uint32_t
    112       1.1    freza tft0_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
    113       1.1    freza {
    114       1.1    freza 	uint32_t 		val;
    115       1.1    freza 
    116       1.1    freza 	addr += h;
    117       1.1    freza 
    118       1.1    freza 	switch (addr) {
    119       1.1    freza 	RCASE(DCR_TFT0_BASE, TFT_CTRL);
    120       1.1    freza 	RCASE(DCR_TFT0_BASE, TFT_ADDR);
    121       1.1    freza 	RDEAD(addr);
    122       1.1    freza 	}
    123       1.1    freza 
    124       1.1    freza 	return (val);
    125       1.1    freza }
    126       1.1    freza 
    127       1.1    freza static void
    128       1.1    freza tft1_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
    129       1.1    freza     uint32_t val)
    130       1.1    freza {
    131       1.1    freza 	addr += h;
    132       1.1    freza 
    133       1.1    freza 	switch (addr) {
    134       1.1    freza 	WCASE(DCR_TFT1_BASE, TFT_CTRL);
    135       1.1    freza 	WCASE(DCR_TFT0_BASE, TFT_ADDR);
    136       1.1    freza 	WDEAD(addr);
    137       1.1    freza 	}
    138       1.1    freza }
    139       1.1    freza 
    140       1.1    freza static uint32_t
    141       1.1    freza tft1_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
    142       1.1    freza {
    143       1.1    freza 	uint32_t 		val;
    144       1.1    freza 
    145       1.1    freza 	addr += h;
    146       1.1    freza 
    147       1.1    freza 	switch (addr) {
    148       1.1    freza 	RCASE(DCR_TFT1_BASE, TFT_CTRL);
    149       1.1    freza 	RCASE(DCR_TFT0_BASE, TFT_ADDR);
    150       1.1    freza 	RDEAD(addr);
    151       1.1    freza 	}
    152       1.1    freza 
    153       1.1    freza 	return (val);
    154       1.1    freza }
    155       1.1    freza 
    156       1.1    freza #define DOCHAN(op, base, channel) \
    157       1.1    freza 	op(base, channel + CDMAC_NEXT); 	\
    158       1.1    freza 	op(base, channel + CDMAC_CURADDR); 	\
    159       1.1    freza 	op(base, channel + CDMAC_CURSIZE); 	\
    160       1.1    freza 	op(base, channel + CDMAC_CURDESC)
    161       1.1    freza 
    162       1.1    freza static void
    163       1.1    freza cdmac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
    164       1.1    freza     uint32_t val)
    165       1.1    freza {
    166       1.1    freza 	addr += h;
    167       1.1    freza 
    168       1.1    freza 	switch (addr) {
    169       1.1    freza 	WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); 	/* Tx engine */
    170       1.1    freza 	WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); 	/* Rx engine */
    171       1.1    freza 	WCASE(DCR_CDMAC_BASE, CDMAC_INTR);
    172       1.1    freza 	DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));
    173       1.1    freza 	DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));
    174       1.1    freza 	WDEAD(addr);
    175       1.1    freza 	}
    176       1.1    freza }
    177       1.1    freza 
    178       1.1    freza static uint32_t
    179       1.1    freza cdmac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
    180       1.1    freza {
    181       1.1    freza 	uint32_t 		val;
    182       1.1    freza 
    183       1.1    freza 	addr += h;
    184       1.1    freza 
    185       1.1    freza 	switch (addr) {
    186       1.1    freza 	RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); 	/* Tx engine */
    187       1.1    freza 	RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); 	/* Rx engine */
    188       1.1    freza 	RCASE(DCR_CDMAC_BASE, CDMAC_INTR);
    189       1.1    freza 	DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));
    190       1.1    freza 	DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));
    191       1.1    freza 	RDEAD(addr);
    192       1.1    freza 	}
    193       1.1    freza 
    194       1.1    freza 	return (val);
    195       1.1    freza }
    196       1.1    freza 
    197       1.1    freza #undef DOCHAN
    198       1.1    freza 
    199       1.1    freza static void
    200       1.1    freza temac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
    201       1.1    freza     uint32_t val)
    202       1.1    freza {
    203       1.1    freza 	addr += h;
    204       1.1    freza 
    205       1.1    freza 	switch (addr) {
    206       1.1    freza 	WCASE(DCR_TEMAC_BASE, TEMAC_RESET);
    207       1.1    freza 	WDEAD(addr);
    208       1.1    freza 	}
    209       1.1    freza }
    210       1.1    freza 
    211       1.1    freza static uint32_t
    212       1.1    freza temac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
    213       1.1    freza {
    214       1.1    freza 	uint32_t 		val;
    215       1.1    freza 
    216       1.1    freza 	addr += h;
    217       1.1    freza 
    218       1.1    freza 	switch (addr) {
    219       1.1    freza 	RCASE(DCR_TEMAC_BASE, TEMAC_RESET);
    220       1.1    freza 	RDEAD(addr);
    221       1.1    freza 	}
    222       1.1    freza 
    223       1.1    freza 	return (val);
    224       1.1    freza }
    225       1.1    freza 
    226       1.1    freza static const struct powerpc_bus_space cdmac_bst = {
    227       1.1    freza 	DCR_BST_BODY(DCR_CDMAC_BASE, cdmac_read_4, cdmac_write_4)
    228       1.1    freza };
    229       1.1    freza 
    230       1.1    freza static const struct powerpc_bus_space temac_bst = {
    231       1.1    freza 	DCR_BST_BODY(DCR_TEMAC_BASE, temac_read_4, temac_write_4)
    232       1.1    freza };
    233       1.1    freza 
    234       1.1    freza static const struct powerpc_bus_space tft0_bst = {
    235       1.1    freza 	DCR_BST_BODY(DCR_TFT0_BASE, tft0_read_4, tft0_write_4)
    236       1.1    freza };
    237       1.1    freza 
    238       1.1    freza static const struct powerpc_bus_space tft1_bst = {
    239       1.1    freza 	DCR_BST_BODY(DCR_TFT1_BASE, tft1_read_4, tft1_write_4)
    240       1.1    freza };
    241       1.1    freza 
    242       1.1    freza static struct powerpc_bus_space opb_bst = {
    243       1.1    freza 	.pbs_flags 	= _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
    244       1.1    freza 	.pbs_base 	= 0 /*OPB_BASE*/,
    245       1.1    freza 	.pbs_offset 	= OPB_BASE,
    246       1.1    freza };
    247       1.1    freza 
    248       1.1    freza static char opb_extent_storage[EXTENT_FIXED_STORAGE_SIZE(8)] __aligned(8);
    249       1.1    freza 
    250       1.1    freza /*
    251       1.1    freza  * Master device configuration table for GSRD2 design.
    252       1.1    freza  */
    253       1.1    freza static const struct gsrddev {
    254       1.1    freza 	const char 		*gdv_name;
    255       1.1    freza 	const char 		*gdv_attr;
    256       1.1    freza 	bus_space_tag_t 	gdv_bst;
    257       1.1    freza 	bus_addr_t 		gdv_addr;
    258       1.1    freza 	int 			gdv_intr;
    259       1.1    freza 	int 			gdv_rx_dma;
    260       1.1    freza 	int 			gdv_tx_dma;
    261       1.1    freza 	int 			gdv_dcr; 		/* XXX bst flag */
    262       1.1    freza } gsrd_devices[] = {
    263       1.1    freza 	{			/* gsrd_devices[0] */
    264       1.1    freza 		.gdv_name 	= "xlcom",
    265       1.1    freza 		.gdv_attr 	= "xcvbus",
    266       1.1    freza 		.gdv_bst 	= &opb_bst,
    267       1.1    freza 		.gdv_addr 	= OPB_XLCOM_BASE,
    268       1.1    freza 		.gdv_intr 	= 2,
    269       1.1    freza 		.gdv_rx_dma 	= -1,
    270       1.1    freza 		.gdv_tx_dma 	= -1,
    271       1.1    freza 		.gdv_dcr 	= 0,
    272       1.1    freza 	},
    273       1.1    freza 	{			/* gsrd_devices[1] */
    274       1.1    freza 		.gdv_name 	= "temac",
    275       1.1    freza 		.gdv_attr 	= "xcvbus",
    276       1.1    freza 		.gdv_bst 	= &temac_bst,
    277       1.1    freza 		.gdv_addr 	= 0,
    278       1.1    freza 		.gdv_intr 	= 1, 		/* unused MII intr */
    279       1.1    freza 		.gdv_rx_dma 	= 1, 		/* cdmac Rx */
    280       1.1    freza 		.gdv_tx_dma 	= 0, 		/* cdmac Tx */
    281       1.1    freza 		.gdv_dcr 	= 1,
    282       1.1    freza 	},
    283       1.1    freza #ifndef DESIGN_DFC
    284       1.1    freza 	{			/* gsrd_devices[2] */
    285       1.1    freza 		.gdv_name 	= "tft",
    286       1.1    freza 		.gdv_attr 	= "plbus",
    287       1.1    freza 		.gdv_bst 	= &tft0_bst,
    288       1.1    freza 		.gdv_addr 	= 0,
    289       1.1    freza 		.gdv_intr 	= -1,
    290       1.1    freza 		.gdv_rx_dma 	= -1,
    291       1.1    freza 		.gdv_tx_dma 	= -1,
    292       1.1    freza 		.gdv_dcr 	= 1,
    293       1.1    freza 	},
    294       1.1    freza #endif
    295       1.1    freza 	{			/* gsrd_devices[2] */
    296       1.1    freza 		.gdv_name 	= "tft",
    297       1.1    freza 		.gdv_attr 	= "plbus",
    298       1.1    freza 		.gdv_bst 	= &tft1_bst,
    299       1.1    freza 		.gdv_addr 	= 0,
    300       1.1    freza 		.gdv_intr 	= -1,
    301       1.1    freza 		.gdv_rx_dma 	= -1,
    302       1.1    freza 		.gdv_tx_dma 	= -1,
    303       1.1    freza 		.gdv_dcr 	= 1,
    304       1.1    freza 	},
    305       1.1    freza #ifdef DESIGN_DFC
    306       1.1    freza 	{			/* gsrd_devices[3] */
    307       1.1    freza 		.gdv_name 	= "pstwo",
    308       1.1    freza 		.gdv_attr 	= "xcvbus",
    309       1.1    freza 		.gdv_bst 	= &opb_bst,
    310       1.1    freza 		.gdv_addr 	= OPB_PSTWO0_BASE,
    311       1.1    freza 		.gdv_intr 	= 3,
    312       1.1    freza 		.gdv_rx_dma 	= -1,
    313       1.1    freza 		.gdv_tx_dma 	= -1,
    314       1.1    freza 		.gdv_dcr 	= 0,
    315       1.1    freza 	},
    316       1.1    freza 	{			/* gsrd_devices[4] */
    317       1.1    freza 		.gdv_name 	= "pstwo",
    318       1.1    freza 		.gdv_attr 	= "xcvbus",
    319       1.1    freza 		.gdv_bst 	= &opb_bst,
    320       1.1    freza 		.gdv_addr 	= OPB_PSTWO1_BASE,
    321       1.1    freza 		.gdv_intr 	= 4,
    322       1.1    freza 		.gdv_rx_dma 	= -1,
    323       1.1    freza 		.gdv_tx_dma 	= -1,
    324       1.1    freza 		.gdv_dcr 	= 0,
    325       1.1    freza 	},
    326       1.1    freza #endif
    327       1.1    freza };
    328       1.1    freza 
    329       1.1    freza static struct ll_dmac *
    330       1.1    freza virtex_mpmc_mapdma(int idx, struct ll_dmac *chan)
    331       1.1    freza {
    332       1.1    freza 	if (idx == -1)
    333       1.1    freza 		return (NULL);
    334       1.1    freza 
    335       1.1    freza 	KASSERT(idx >= 0 && idx < CDMAC_NCHAN);
    336       1.1    freza 
    337       1.1    freza 	chan->dmac_iot = &cdmac_bst;
    338       1.1    freza 	chan->dmac_ctrl_addr = CDMAC_CTRL_BASE(idx);
    339       1.1    freza 	chan->dmac_stat_addr = CDMAC_STAT_BASE(idx);
    340       1.1    freza 	chan->dmac_chan = idx;
    341       1.1    freza 
    342       1.1    freza 	return (chan);
    343       1.1    freza }
    344       1.1    freza 
    345       1.1    freza static int
    346       1.1    freza cdmac_intr(void *arg)
    347       1.1    freza {
    348       1.1    freza 	uint32_t 		isr;
    349       1.1    freza 	int 			did = 0;
    350       1.1    freza 
    351       1.1    freza 	isr = bus_space_read_4(&cdmac_bst, 0, CDMAC_INTR);
    352       1.1    freza 
    353       1.1    freza 	if (ISSET(isr, CDMAC_INTR_TX0) && cdmacintr[0].cih_func) {
    354       1.1    freza 		(cdmacintr[0].cih_func)(cdmacintr[0].cih_arg);
    355       1.1    freza 		did++;
    356       1.1    freza 	}
    357       1.1    freza 	if (ISSET(isr, CDMAC_INTR_RX0) && cdmacintr[1].cih_func) {
    358       1.1    freza 		(cdmacintr[1].cih_func)(cdmacintr[1].cih_arg);
    359       1.1    freza 		did++;
    360       1.1    freza 	}
    361       1.1    freza 
    362       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, isr); 	/* ack */
    363       1.1    freza 
    364       1.1    freza 	/* XXX This still happens all the time under load. */
    365       1.1    freza #if 0
    366       1.1    freza 	if (did == 0)
    367       1.1    freza 		aprint_normal("WARNING: stray cdmac isr 0x%x\n", isr);
    368       1.1    freza #endif
    369       1.1    freza 	return (0);
    370       1.1    freza }
    371       1.1    freza 
    372       1.1    freza /*
    373       1.1    freza  * Public interface.
    374       1.1    freza  */
    375       1.1    freza 
    376       1.1    freza void
    377       1.1    freza virtex_autoconf(device_t self, struct plb_attach_args *paa)
    378       1.1    freza {
    379       1.1    freza 
    380       1.1    freza 	struct xcvbus_attach_args 	vaa;
    381       1.1    freza 	struct ll_dmac 			rx, tx;
    382       1.1    freza 	int 				i;
    383       1.1    freza 
    384       1.1    freza 	/* Reset DMA channels. */
    385       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(0), CDMAC_STAT_RESET);
    386       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(1), CDMAC_STAT_RESET);
    387       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, 0);
    388       1.1    freza 
    389       1.1    freza 	vaa.vaa_dmat = paa->plb_dmat;
    390       1.1    freza 
    391       1.1    freza 	for (i = 0; i < __arraycount(gsrd_devices); i++) {
    392       1.1    freza 		const struct gsrddev 	*g = &gsrd_devices[i];
    393       1.1    freza 
    394       1.1    freza 		vaa._vaa_is_dcr = g->gdv_dcr; 	/* XXX bst flag */
    395       1.1    freza 		vaa.vaa_name 	= g->gdv_name;
    396       1.1    freza 		vaa.vaa_addr 	= g->gdv_addr;
    397       1.1    freza 		vaa.vaa_intr 	= g->gdv_intr;
    398       1.1    freza 		vaa.vaa_iot 	= g->gdv_bst;
    399       1.1    freza 
    400       1.1    freza 		vaa.vaa_rx_dmac = virtex_mpmc_mapdma(g->gdv_rx_dma, &rx);
    401       1.1    freza 		vaa.vaa_tx_dmac = virtex_mpmc_mapdma(g->gdv_tx_dma, &tx);
    402       1.1    freza 
    403       1.1    freza 		config_found_ia(self, g->gdv_attr, &vaa, xcvbus_print);
    404       1.1    freza 	}
    405       1.1    freza 
    406       1.1    freza 	/* Setup the dispatch handler. */
    407       1.1    freza 	cdmac_ih = intr_establish(CDMAC_INTR_LINE, IST_LEVEL, IPL_NET,
    408       1.1    freza 	    cdmac_intr, NULL);
    409       1.1    freza 	if (cdmac_ih == NULL)
    410       1.1    freza 		panic("virtex_mpmc_done: could not establish cdmac intr");
    411       1.1    freza 
    412       1.1    freza 	/* Clear (XXX?) and enable interrupts. */
    413       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, ~CDMAC_INTR_MIE);
    414       1.1    freza 	bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, CDMAC_INTR_MIE);
    415       1.1    freza }
    416       1.1    freza 
    417       1.1    freza void *
    418       1.1    freza ll_dmac_intr_establish(int chan, void (*handler)(void *), void *arg)
    419       1.1    freza {
    420       1.1    freza 	KASSERT(chan >= 0 && chan < CDMAC_NCHAN);
    421       1.1    freza 	KASSERT(cdmacintr[chan].cih_func == NULL);
    422       1.1    freza 	KASSERT(cdmacintr[chan].cih_arg == NULL);
    423       1.1    freza 
    424       1.1    freza 	cdmacintr[chan].cih_func = handler;
    425       1.1    freza 	cdmacintr[chan].cih_arg = arg;
    426       1.1    freza 
    427       1.1    freza 	return (&cdmacintr[chan]);
    428       1.1    freza }
    429       1.1    freza 
    430       1.1    freza void
    431       1.1    freza ll_dmac_intr_disestablish(int chan, void *handle)
    432       1.1    freza {
    433       1.1    freza 	int 			s;
    434       1.1    freza 
    435       1.1    freza 	KASSERT(chan >= 0 && chan < CDMAC_NCHAN);
    436       1.1    freza 	KASSERT(&cdmacintr[chan] == handle);
    437       1.1    freza 
    438       1.1    freza 	s = splnet();
    439       1.1    freza 	cdmacintr[chan].cih_func = NULL;
    440       1.1    freza 	cdmacintr[chan].cih_arg = NULL;
    441       1.1    freza 	splx(s);
    442       1.1    freza }
    443       1.1    freza 
    444       1.1    freza int
    445  1.2.20.1    joerg virtex_bus_space_tag(const char *xname, bus_space_tag_t *bst)
    446       1.1    freza {
    447       1.1    freza 	if (strncmp(xname, "xlcom", 5) == 0) {
    448       1.1    freza 		*bst = &opb_bst;
    449       1.1    freza 		return (0);
    450       1.1    freza 	}
    451       1.1    freza 
    452       1.1    freza 	return (ENODEV);
    453       1.1    freza }
    454       1.1    freza 
    455       1.1    freza void
    456       1.1    freza virtex_machdep_init(vaddr_t endva, vsize_t maxsz, struct mem_region *phys,
    457       1.1    freza     struct mem_region *avail)
    458       1.1    freza {
    459       1.1    freza 	ppc4xx_tlb_reserve(OPB_BASE, endva, maxsz, TLB_I | TLB_G);
    460       1.1    freza 	endva += maxsz;
    461       1.1    freza 
    462       1.1    freza 	opb_bst.pbs_limit = maxsz;
    463       1.1    freza 
    464       1.1    freza 	if (bus_space_init(&opb_bst, "opbtag", opb_extent_storage,
    465       1.1    freza 	    sizeof(opb_extent_storage)))
    466       1.1    freza 		panic("virtex_machdep_init: failed to initialize opb_bst");
    467       1.1    freza 
    468       1.1    freza 	/*
    469       1.1    freza 	 * The TFT controller is broken, we can't change FB address.
    470       1.1    freza 	 * Hardwire it at predefined base address, create uncached
    471       1.1    freza 	 * mapping.
    472       1.1    freza 	 */
    473       1.1    freza 
    474       1.1    freza 	avail[0].size = TFT_FB_BASE - avail[0].start;
    475       1.1    freza 	ppc4xx_tlb_reserve(TFT_FB_BASE, endva, TFT_FB_SIZE, TLB_I | TLB_G);
    476       1.1    freza }
    477       1.1    freza 
    478       1.1    freza void
    479       1.1    freza device_register(struct device *dev, void *aux)
    480       1.1    freza {
    481       1.1    freza 	prop_number_t 		pn;
    482       1.1    freza 	void 			*fb;
    483       1.1    freza 
    484       1.1    freza 	if (strncmp(device_xname(dev), "tft0", 4) == 0) {
    485       1.1    freza 		fb = ppc4xx_tlb_mapiodev(TFT_FB_BASE, TFT_FB_SIZE);
    486       1.1    freza 		if (fb == NULL)
    487       1.1    freza 			panic("device_register: framebuffer mapping gone!\n");
    488       1.1    freza 
    489       1.1    freza 		pn = prop_number_create_unsigned_integer(TFT_FB_BASE);
    490       1.1    freza 		if (pn == NULL) {
    491       1.1    freza 			printf("WARNING: could not allocate virtex-tft-pa\n");
    492       1.1    freza 			return ;
    493       1.1    freza 		}
    494       1.1    freza 		if (prop_dictionary_set(device_properties(dev),
    495       1.2  thorpej 		    "virtex-tft-pa", pn) != true)
    496       1.1    freza 			printf("WARNING: could not set virtex-tft-pa\n");
    497       1.1    freza 		prop_object_release(pn);
    498       1.1    freza 
    499       1.1    freza 		pn = prop_number_create_unsigned_integer((uintptr_t)fb);
    500       1.1    freza 		if (pn == NULL) {
    501       1.1    freza 			printf("WARNING: could not allocate virtex-tft-va\n");
    502       1.1    freza 			return ;
    503       1.1    freza 		}
    504       1.1    freza 		if (prop_dictionary_set(device_properties(dev),
    505       1.2  thorpej 		    "virtex-tft-va", pn) != true)
    506       1.1    freza 			printf("WARNING: could not set virtex-tft-va\n");
    507       1.1    freza 		prop_object_release(pn);
    508       1.1    freza 	}
    509       1.1    freza }
    510