design_gsrd2.c revision 1.3.52.1
1 /* $NetBSD: design_gsrd2.c,v 1.3.52.1 2011/06/23 14:19:10 cherry Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Jachym Holecek 5 * All rights reserved. 6 * 7 * Written for DFC Design, s.r.o. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_virtex.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: design_gsrd2.c,v 1.3.52.1 2011/06/23 14:19:10 cherry Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/extent.h> 43 #include <sys/cpu.h> 44 #include <sys/bus.h> 45 #include <sys/intr.h> 46 47 #include <machine/powerpc.h> 48 #include <machine/tlb.h> 49 50 #include <powerpc/ibm4xx/cpu.h> 51 #include <powerpc/ibm4xx/dev/plbvar.h> 52 53 #include <evbppc/virtex/dev/xcvbusvar.h> 54 #include <evbppc/virtex/dev/cdmacreg.h> 55 #include <evbppc/virtex/dev/temacreg.h> 56 #include <evbppc/virtex/dev/tftreg.h> 57 58 #include <evbppc/virtex/virtex.h> 59 #include <evbppc/virtex/dcr.h> 60 61 62 #define DCR_TEMAC_BASE 0x0030 63 #define DCR_TFT0_BASE 0x0082 64 #define DCR_TFT1_BASE 0x0086 65 #define DCR_CDMAC_BASE 0x0140 66 67 #define OPB_BASE 0x80000000 /* below are offsets in opb */ 68 #define OPB_XLCOM_BASE 0x010000 69 #define OPB_GPIO_BASE 0x020000 70 #define OPB_PSTWO0_BASE 0x040000 71 #define OPB_PSTWO1_BASE 0x041000 72 #define CDMAC_NCHAN 2 /* cdmac {Tx,Rx} */ 73 #define CDMAC_INTR_LINE 0 74 75 #define TFT_FB_BASE 0x3c00000 76 #define TFT_FB_SIZE (2*1024*1024) 77 78 /* 79 * CDMAC per-channel interrupt handler. CDMAC has one interrupt signal 80 * per two channels on mpmc2, so we have to dispatch channels manually. 81 * 82 * Note: we hardwire priority to IPL_NET, temac(4) is the only device that 83 * needs to service DMA interrupts anyway. 84 */ 85 typedef struct cdmac_intrhand { 86 void (*cih_func)(void *); 87 void *cih_arg; 88 } *cdmac_intrhand_t; 89 90 /* Two instantiated channels, one logical interrupt per direction. */ 91 static struct cdmac_intrhand cdmacintr[CDMAC_NCHAN]; 92 static void *cdmac_ih; 93 94 95 /* 96 * DCR bus space leaf access routines. 97 */ 98 99 static void 100 tft0_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr, 101 uint32_t val) 102 { 103 addr += h; 104 105 switch (addr) { 106 WCASE(DCR_TFT0_BASE, TFT_CTRL); 107 WCASE(DCR_TFT0_BASE, TFT_ADDR); 108 WDEAD(addr); 109 } 110 } 111 112 static uint32_t 113 tft0_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr) 114 { 115 uint32_t val; 116 117 addr += h; 118 119 switch (addr) { 120 RCASE(DCR_TFT0_BASE, TFT_CTRL); 121 RCASE(DCR_TFT0_BASE, TFT_ADDR); 122 RDEAD(addr); 123 } 124 125 return (val); 126 } 127 128 static void 129 tft1_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr, 130 uint32_t val) 131 { 132 addr += h; 133 134 switch (addr) { 135 WCASE(DCR_TFT1_BASE, TFT_CTRL); 136 WCASE(DCR_TFT0_BASE, TFT_ADDR); 137 WDEAD(addr); 138 } 139 } 140 141 static uint32_t 142 tft1_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr) 143 { 144 uint32_t val; 145 146 addr += h; 147 148 switch (addr) { 149 RCASE(DCR_TFT1_BASE, TFT_CTRL); 150 RCASE(DCR_TFT0_BASE, TFT_ADDR); 151 RDEAD(addr); 152 } 153 154 return (val); 155 } 156 157 #define DOCHAN(op, base, channel) \ 158 op(base, channel + CDMAC_NEXT); \ 159 op(base, channel + CDMAC_CURADDR); \ 160 op(base, channel + CDMAC_CURSIZE); \ 161 op(base, channel + CDMAC_CURDESC) 162 163 static void 164 cdmac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr, 165 uint32_t val) 166 { 167 addr += h; 168 169 switch (addr) { 170 WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */ 171 WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */ 172 WCASE(DCR_CDMAC_BASE, CDMAC_INTR); 173 DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0)); 174 DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1)); 175 WDEAD(addr); 176 } 177 } 178 179 static uint32_t 180 cdmac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr) 181 { 182 uint32_t val; 183 184 addr += h; 185 186 switch (addr) { 187 RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */ 188 RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */ 189 RCASE(DCR_CDMAC_BASE, CDMAC_INTR); 190 DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0)); 191 DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1)); 192 RDEAD(addr); 193 } 194 195 return (val); 196 } 197 198 #undef DOCHAN 199 200 static void 201 temac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr, 202 uint32_t val) 203 { 204 addr += h; 205 206 switch (addr) { 207 WCASE(DCR_TEMAC_BASE, TEMAC_RESET); 208 WDEAD(addr); 209 } 210 } 211 212 static uint32_t 213 temac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr) 214 { 215 uint32_t val; 216 217 addr += h; 218 219 switch (addr) { 220 RCASE(DCR_TEMAC_BASE, TEMAC_RESET); 221 RDEAD(addr); 222 } 223 224 return (val); 225 } 226 227 static const struct powerpc_bus_space cdmac_bst = { 228 DCR_BST_BODY(DCR_CDMAC_BASE, cdmac_read_4, cdmac_write_4) 229 }; 230 231 static const struct powerpc_bus_space temac_bst = { 232 DCR_BST_BODY(DCR_TEMAC_BASE, temac_read_4, temac_write_4) 233 }; 234 235 static const struct powerpc_bus_space tft0_bst = { 236 DCR_BST_BODY(DCR_TFT0_BASE, tft0_read_4, tft0_write_4) 237 }; 238 239 static const struct powerpc_bus_space tft1_bst = { 240 DCR_BST_BODY(DCR_TFT1_BASE, tft1_read_4, tft1_write_4) 241 }; 242 243 static struct powerpc_bus_space opb_bst = { 244 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 245 .pbs_base = 0 /*OPB_BASE*/, 246 .pbs_offset = OPB_BASE, 247 }; 248 249 static char opb_extent_storage[EXTENT_FIXED_STORAGE_SIZE(8)] __aligned(8); 250 251 /* 252 * Master device configuration table for GSRD2 design. 253 */ 254 static const struct gsrddev { 255 const char *gdv_name; 256 const char *gdv_attr; 257 bus_space_tag_t gdv_bst; 258 bus_addr_t gdv_addr; 259 int gdv_intr; 260 int gdv_rx_dma; 261 int gdv_tx_dma; 262 int gdv_dcr; /* XXX bst flag */ 263 } gsrd_devices[] = { 264 { /* gsrd_devices[0] */ 265 .gdv_name = "xlcom", 266 .gdv_attr = "xcvbus", 267 .gdv_bst = &opb_bst, 268 .gdv_addr = OPB_XLCOM_BASE, 269 .gdv_intr = 2, 270 .gdv_rx_dma = -1, 271 .gdv_tx_dma = -1, 272 .gdv_dcr = 0, 273 }, 274 { /* gsrd_devices[1] */ 275 .gdv_name = "temac", 276 .gdv_attr = "xcvbus", 277 .gdv_bst = &temac_bst, 278 .gdv_addr = 0, 279 .gdv_intr = 1, /* unused MII intr */ 280 .gdv_rx_dma = 1, /* cdmac Rx */ 281 .gdv_tx_dma = 0, /* cdmac Tx */ 282 .gdv_dcr = 1, 283 }, 284 #ifndef DESIGN_DFC 285 { /* gsrd_devices[2] */ 286 .gdv_name = "tft", 287 .gdv_attr = "plbus", 288 .gdv_bst = &tft0_bst, 289 .gdv_addr = 0, 290 .gdv_intr = -1, 291 .gdv_rx_dma = -1, 292 .gdv_tx_dma = -1, 293 .gdv_dcr = 1, 294 }, 295 #endif 296 { /* gsrd_devices[2] */ 297 .gdv_name = "tft", 298 .gdv_attr = "plbus", 299 .gdv_bst = &tft1_bst, 300 .gdv_addr = 0, 301 .gdv_intr = -1, 302 .gdv_rx_dma = -1, 303 .gdv_tx_dma = -1, 304 .gdv_dcr = 1, 305 }, 306 #ifdef DESIGN_DFC 307 { /* gsrd_devices[3] */ 308 .gdv_name = "pstwo", 309 .gdv_attr = "xcvbus", 310 .gdv_bst = &opb_bst, 311 .gdv_addr = OPB_PSTWO0_BASE, 312 .gdv_intr = 3, 313 .gdv_rx_dma = -1, 314 .gdv_tx_dma = -1, 315 .gdv_dcr = 0, 316 }, 317 { /* gsrd_devices[4] */ 318 .gdv_name = "pstwo", 319 .gdv_attr = "xcvbus", 320 .gdv_bst = &opb_bst, 321 .gdv_addr = OPB_PSTWO1_BASE, 322 .gdv_intr = 4, 323 .gdv_rx_dma = -1, 324 .gdv_tx_dma = -1, 325 .gdv_dcr = 0, 326 }, 327 #endif 328 }; 329 330 static struct ll_dmac * 331 virtex_mpmc_mapdma(int idx, struct ll_dmac *chan) 332 { 333 if (idx == -1) 334 return (NULL); 335 336 KASSERT(idx >= 0 && idx < CDMAC_NCHAN); 337 338 chan->dmac_iot = &cdmac_bst; 339 chan->dmac_ctrl_addr = CDMAC_CTRL_BASE(idx); 340 chan->dmac_stat_addr = CDMAC_STAT_BASE(idx); 341 chan->dmac_chan = idx; 342 343 return (chan); 344 } 345 346 static int 347 cdmac_intr(void *arg) 348 { 349 uint32_t isr; 350 int did = 0; 351 352 isr = bus_space_read_4(&cdmac_bst, 0, CDMAC_INTR); 353 354 if (ISSET(isr, CDMAC_INTR_TX0) && cdmacintr[0].cih_func) { 355 (cdmacintr[0].cih_func)(cdmacintr[0].cih_arg); 356 did++; 357 } 358 if (ISSET(isr, CDMAC_INTR_RX0) && cdmacintr[1].cih_func) { 359 (cdmacintr[1].cih_func)(cdmacintr[1].cih_arg); 360 did++; 361 } 362 363 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, isr); /* ack */ 364 365 /* XXX This still happens all the time under load. */ 366 #if 0 367 if (did == 0) 368 aprint_normal("WARNING: stray cdmac isr 0x%x\n", isr); 369 #endif 370 return (0); 371 } 372 373 /* 374 * Public interface. 375 */ 376 377 void 378 virtex_autoconf(device_t self, struct plb_attach_args *paa) 379 { 380 381 struct xcvbus_attach_args vaa; 382 struct ll_dmac rx, tx; 383 int i; 384 385 /* Reset DMA channels. */ 386 bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(0), CDMAC_STAT_RESET); 387 bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(1), CDMAC_STAT_RESET); 388 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, 0); 389 390 vaa.vaa_dmat = paa->plb_dmat; 391 392 for (i = 0; i < __arraycount(gsrd_devices); i++) { 393 const struct gsrddev *g = &gsrd_devices[i]; 394 395 vaa._vaa_is_dcr = g->gdv_dcr; /* XXX bst flag */ 396 vaa.vaa_name = g->gdv_name; 397 vaa.vaa_addr = g->gdv_addr; 398 vaa.vaa_intr = g->gdv_intr; 399 vaa.vaa_iot = g->gdv_bst; 400 401 vaa.vaa_rx_dmac = virtex_mpmc_mapdma(g->gdv_rx_dma, &rx); 402 vaa.vaa_tx_dmac = virtex_mpmc_mapdma(g->gdv_tx_dma, &tx); 403 404 config_found_ia(self, g->gdv_attr, &vaa, xcvbus_print); 405 } 406 407 /* Setup the dispatch handler. */ 408 cdmac_ih = intr_establish(CDMAC_INTR_LINE, IST_LEVEL, IPL_NET, 409 cdmac_intr, NULL); 410 if (cdmac_ih == NULL) 411 panic("virtex_mpmc_done: could not establish cdmac intr"); 412 413 /* Clear (XXX?) and enable interrupts. */ 414 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, ~CDMAC_INTR_MIE); 415 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, CDMAC_INTR_MIE); 416 } 417 418 void * 419 ll_dmac_intr_establish(int chan, void (*handler)(void *), void *arg) 420 { 421 KASSERT(chan >= 0 && chan < CDMAC_NCHAN); 422 KASSERT(cdmacintr[chan].cih_func == NULL); 423 KASSERT(cdmacintr[chan].cih_arg == NULL); 424 425 cdmacintr[chan].cih_func = handler; 426 cdmacintr[chan].cih_arg = arg; 427 428 return (&cdmacintr[chan]); 429 } 430 431 void 432 ll_dmac_intr_disestablish(int chan, void *handle) 433 { 434 int s; 435 436 KASSERT(chan >= 0 && chan < CDMAC_NCHAN); 437 KASSERT(&cdmacintr[chan] == handle); 438 439 s = splnet(); 440 cdmacintr[chan].cih_func = NULL; 441 cdmacintr[chan].cih_arg = NULL; 442 splx(s); 443 } 444 445 int 446 virtex_bus_space_tag(const char *xname, bus_space_tag_t *bst) 447 { 448 if (strncmp(xname, "xlcom", 5) == 0) { 449 *bst = &opb_bst; 450 return (0); 451 } 452 453 return (ENODEV); 454 } 455 456 void 457 virtex_machdep_init(vaddr_t endva, vsize_t maxsz, struct mem_region *phys, 458 struct mem_region *avail) 459 { 460 ppc4xx_tlb_reserve(OPB_BASE, endva, maxsz, TLB_I | TLB_G); 461 endva += maxsz; 462 463 opb_bst.pbs_limit = maxsz; 464 465 if (bus_space_init(&opb_bst, "opbtag", opb_extent_storage, 466 sizeof(opb_extent_storage))) 467 panic("virtex_machdep_init: failed to initialize opb_bst"); 468 469 /* 470 * The TFT controller is broken, we can't change FB address. 471 * Hardwire it at predefined base address, create uncached 472 * mapping. 473 */ 474 475 avail[0].size = TFT_FB_BASE - avail[0].start; 476 ppc4xx_tlb_reserve(TFT_FB_BASE, endva, TFT_FB_SIZE, TLB_I | TLB_G); 477 } 478 479 void 480 device_register(device_t dev, void *aux) 481 { 482 prop_number_t pn; 483 void *fb; 484 485 if (strncmp(device_xname(dev), "tft0", 4) == 0) { 486 fb = ppc4xx_tlb_mapiodev(TFT_FB_BASE, TFT_FB_SIZE); 487 if (fb == NULL) 488 panic("device_register: framebuffer mapping gone!\n"); 489 490 pn = prop_number_create_unsigned_integer(TFT_FB_BASE); 491 if (pn == NULL) { 492 printf("WARNING: could not allocate virtex-tft-pa\n"); 493 return ; 494 } 495 if (prop_dictionary_set(device_properties(dev), 496 "virtex-tft-pa", pn) != true) 497 printf("WARNING: could not set virtex-tft-pa\n"); 498 prop_object_release(pn); 499 500 pn = prop_number_create_unsigned_integer((uintptr_t)fb); 501 if (pn == NULL) { 502 printf("WARNING: could not allocate virtex-tft-va\n"); 503 return ; 504 } 505 if (prop_dictionary_set(device_properties(dev), 506 "virtex-tft-va", pn) != true) 507 printf("WARNING: could not set virtex-tft-va\n"); 508 prop_object_release(pn); 509 } 510 } 511
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