if_temac.c revision 1.1.2.2
1 1.1.2.2 yamt /* $NetBSD: if_temac.c,v 1.1.2.2 2006/12/10 07:15:54 yamt Exp $ */ 2 1.1.2.2 yamt 3 1.1.2.2 yamt /* 4 1.1.2.2 yamt * Copyright (c) 2006 Jachym Holecek 5 1.1.2.2 yamt * All rights reserved. 6 1.1.2.2 yamt * 7 1.1.2.2 yamt * Written for DFC Design, s.r.o. 8 1.1.2.2 yamt * 9 1.1.2.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 yamt * modification, are permitted provided that the following conditions 11 1.1.2.2 yamt * are met: 12 1.1.2.2 yamt * 13 1.1.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 yamt * 16 1.1.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 17 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer in the 18 1.1.2.2 yamt * documentation and/or other materials provided with the distribution. 19 1.1.2.2 yamt * 20 1.1.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.1.2.2 yamt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.1.2.2 yamt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.1.2.2 yamt * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.1.2.2 yamt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.1.2.2 yamt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.1.2.2 yamt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.1.2.2 yamt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.1.2.2 yamt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.1.2.2 yamt * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.1.2.2 yamt */ 31 1.1.2.2 yamt 32 1.1.2.2 yamt /* 33 1.1.2.2 yamt * Driver for Xilinx LocalLink TEMAC as wired on the GSRD platform. 34 1.1.2.2 yamt * 35 1.1.2.2 yamt * TODO: 36 1.1.2.2 yamt * - Optimize 37 1.1.2.2 yamt * - Checksum offload 38 1.1.2.2 yamt * - Address filters 39 1.1.2.2 yamt * - Support jumbo frames 40 1.1.2.2 yamt */ 41 1.1.2.2 yamt 42 1.1.2.2 yamt #include <sys/cdefs.h> 43 1.1.2.2 yamt __KERNEL_RCSID(0, "$NetBSD: if_temac.c,v 1.1.2.2 2006/12/10 07:15:54 yamt Exp $"); 44 1.1.2.2 yamt 45 1.1.2.2 yamt #include "bpfilter.h" 46 1.1.2.2 yamt 47 1.1.2.2 yamt #include <sys/param.h> 48 1.1.2.2 yamt #include <sys/systm.h> 49 1.1.2.2 yamt #include <sys/mbuf.h> 50 1.1.2.2 yamt #include <sys/kernel.h> 51 1.1.2.2 yamt #include <sys/socket.h> 52 1.1.2.2 yamt #include <sys/ioctl.h> 53 1.1.2.2 yamt #include <sys/device.h> 54 1.1.2.2 yamt 55 1.1.2.2 yamt #include <uvm/uvm_extern.h> 56 1.1.2.2 yamt 57 1.1.2.2 yamt #include <net/if.h> 58 1.1.2.2 yamt #include <net/if_dl.h> 59 1.1.2.2 yamt #include <net/if_media.h> 60 1.1.2.2 yamt #include <net/if_ether.h> 61 1.1.2.2 yamt 62 1.1.2.2 yamt #if NBPFILTER > 0 63 1.1.2.2 yamt #include <net/bpf.h> 64 1.1.2.2 yamt #endif 65 1.1.2.2 yamt 66 1.1.2.2 yamt #include <machine/bus.h> 67 1.1.2.2 yamt 68 1.1.2.2 yamt #include <evbppc/virtex/idcr.h> 69 1.1.2.2 yamt #include <evbppc/virtex/dev/xcvbusvar.h> 70 1.1.2.2 yamt #include <evbppc/virtex/dev/cdmacreg.h> 71 1.1.2.2 yamt #include <evbppc/virtex/dev/temacreg.h> 72 1.1.2.2 yamt #include <evbppc/virtex/dev/temacvar.h> 73 1.1.2.2 yamt 74 1.1.2.2 yamt #include <dev/mii/miivar.h> 75 1.1.2.2 yamt 76 1.1.2.2 yamt 77 1.1.2.2 yamt /* This is outside of TEMAC's DCR window, we have to hardcode it... */ 78 1.1.2.2 yamt #define DCR_ETH_BASE 0x0030 79 1.1.2.2 yamt 80 1.1.2.2 yamt #define TEMAC_REGDEBUG 0 81 1.1.2.2 yamt #define TEMAC_RXDEBUG 0 82 1.1.2.2 yamt #define TEMAC_TXDEBUG 0 83 1.1.2.2 yamt 84 1.1.2.2 yamt #if TEMAC_RXDEBUG > 0 || TEMAC_TXDEBUG > 0 85 1.1.2.2 yamt #define TEMAC_DEBUG 1 86 1.1.2.2 yamt #else 87 1.1.2.2 yamt #define TEMAC_DEBUG 0 88 1.1.2.2 yamt #endif 89 1.1.2.2 yamt 90 1.1.2.2 yamt #if TEMAC_REGDEBUG > 0 91 1.1.2.2 yamt #define TRACEREG(arg) printf arg 92 1.1.2.2 yamt #else 93 1.1.2.2 yamt #define TRACEREG(arg) /* nop */ 94 1.1.2.2 yamt #endif 95 1.1.2.2 yamt 96 1.1.2.2 yamt /* DMA control chains take up one (16KB) page. */ 97 1.1.2.2 yamt #define TEMAC_NTXDESC 256 98 1.1.2.2 yamt #define TEMAC_NRXDESC 256 99 1.1.2.2 yamt 100 1.1.2.2 yamt #define TEMAC_TXQLEN 64 /* Software Tx queue length */ 101 1.1.2.2 yamt #define TEMAC_NTXSEG 16 /* Maximum Tx segments per packet */ 102 1.1.2.2 yamt 103 1.1.2.2 yamt #define TEMAC_NRXSEG 1 /* Maximum Rx segments per packet */ 104 1.1.2.2 yamt #define TEMAC_RXPERIOD 1 /* Interrupt every N descriptors. */ 105 1.1.2.2 yamt #define TEMAC_RXTIMO_HZ 100 /* Rx reaper frequency */ 106 1.1.2.2 yamt 107 1.1.2.2 yamt /* Next Tx descriptor and descriptor's offset WRT sc_cdaddr. */ 108 1.1.2.2 yamt #define TEMAC_TXSINC(n, i) (((n) + TEMAC_TXQLEN + (i)) % TEMAC_TXQLEN) 109 1.1.2.2 yamt #define TEMAC_TXINC(n, i) (((n) + TEMAC_NTXDESC + (i)) % TEMAC_NTXDESC) 110 1.1.2.2 yamt 111 1.1.2.2 yamt #define TEMAC_TXSNEXT(n) TEMAC_TXSINC((n), 1) 112 1.1.2.2 yamt #define TEMAC_TXNEXT(n) TEMAC_TXINC((n), 1) 113 1.1.2.2 yamt #define TEMAC_TXDOFF(n) (offsetof(struct temac_control, cd_txdesc) + \ 114 1.1.2.2 yamt (n) * sizeof(struct cdmac_descr)) 115 1.1.2.2 yamt 116 1.1.2.2 yamt /* Next Rx descriptor and descriptor's offset WRT sc_cdaddr. */ 117 1.1.2.2 yamt #define TEMAC_RXINC(n, i) (((n) + TEMAC_NRXDESC + (i)) % TEMAC_NRXDESC) 118 1.1.2.2 yamt #define TEMAC_RXNEXT(n) TEMAC_RXINC((n), 1) 119 1.1.2.2 yamt #define TEMAC_RXDOFF(n) (offsetof(struct temac_control, cd_rxdesc) + \ 120 1.1.2.2 yamt (n) * sizeof(struct cdmac_descr)) 121 1.1.2.2 yamt #define TEMAC_ISINTR(i) (((i) % TEMAC_RXPERIOD) == 0) 122 1.1.2.2 yamt #define TEMAC_ISLAST(i) ((i) == (TEMAC_NRXDESC - 1)) 123 1.1.2.2 yamt 124 1.1.2.2 yamt 125 1.1.2.2 yamt struct temac_control { 126 1.1.2.2 yamt struct cdmac_descr cd_txdesc[TEMAC_NTXDESC]; 127 1.1.2.2 yamt struct cdmac_descr cd_rxdesc[TEMAC_NRXDESC]; 128 1.1.2.2 yamt }; 129 1.1.2.2 yamt 130 1.1.2.2 yamt struct temac_txsoft { 131 1.1.2.2 yamt bus_dmamap_t txs_dmap; 132 1.1.2.2 yamt struct mbuf *txs_mbuf; 133 1.1.2.2 yamt int txs_last; 134 1.1.2.2 yamt }; 135 1.1.2.2 yamt 136 1.1.2.2 yamt struct temac_rxsoft { 137 1.1.2.2 yamt bus_dmamap_t rxs_dmap; 138 1.1.2.2 yamt struct mbuf *rxs_mbuf; 139 1.1.2.2 yamt }; 140 1.1.2.2 yamt 141 1.1.2.2 yamt struct temac_softc { 142 1.1.2.2 yamt struct device sc_dev; 143 1.1.2.2 yamt struct ethercom sc_ec; 144 1.1.2.2 yamt #define sc_if sc_ec.ec_if 145 1.1.2.2 yamt 146 1.1.2.2 yamt /* Peripheral registers */ 147 1.1.2.2 yamt bus_space_tag_t sc_iot; 148 1.1.2.2 yamt bus_space_handle_t sc_ioh; 149 1.1.2.2 yamt 150 1.1.2.2 yamt /* CDMAC channel registers */ 151 1.1.2.2 yamt bus_space_tag_t sc_dma_rxt; 152 1.1.2.2 yamt bus_space_handle_t sc_dma_rxh; /* Rx channel */ 153 1.1.2.2 yamt bus_space_handle_t sc_dma_rsh; /* Rx status */ 154 1.1.2.2 yamt 155 1.1.2.2 yamt bus_space_tag_t sc_dma_txt; 156 1.1.2.2 yamt bus_space_handle_t sc_dma_txh; /* Tx channel */ 157 1.1.2.2 yamt bus_space_handle_t sc_dma_tsh; /* Tx status */ 158 1.1.2.2 yamt 159 1.1.2.2 yamt struct temac_txsoft sc_txsoft[TEMAC_TXQLEN]; 160 1.1.2.2 yamt struct temac_rxsoft sc_rxsoft[TEMAC_NRXDESC]; 161 1.1.2.2 yamt 162 1.1.2.2 yamt struct callout sc_rx_timo; 163 1.1.2.2 yamt struct callout sc_mii_tick; 164 1.1.2.2 yamt struct mii_data sc_mii; 165 1.1.2.2 yamt 166 1.1.2.2 yamt bus_dmamap_t sc_control_dmap; 167 1.1.2.2 yamt #define sc_cdaddr sc_control_dmap->dm_segs[0].ds_addr 168 1.1.2.2 yamt 169 1.1.2.2 yamt struct temac_control *sc_control_data; 170 1.1.2.2 yamt #define sc_rxdescs sc_control_data->cd_rxdesc 171 1.1.2.2 yamt #define sc_txdescs sc_control_data->cd_txdesc 172 1.1.2.2 yamt 173 1.1.2.2 yamt int sc_txbusy; 174 1.1.2.2 yamt 175 1.1.2.2 yamt int sc_txfree; 176 1.1.2.2 yamt int sc_txcur; 177 1.1.2.2 yamt int sc_txreap; 178 1.1.2.2 yamt 179 1.1.2.2 yamt int sc_rxreap; 180 1.1.2.2 yamt 181 1.1.2.2 yamt int sc_txsfree; 182 1.1.2.2 yamt int sc_txscur; 183 1.1.2.2 yamt int sc_txsreap; 184 1.1.2.2 yamt 185 1.1.2.2 yamt int sc_dead; /* Rx/Tx DMA error (fatal) */ 186 1.1.2.2 yamt int sc_rx_drained; 187 1.1.2.2 yamt 188 1.1.2.2 yamt int sc_rx_chan; 189 1.1.2.2 yamt int sc_tx_chan; 190 1.1.2.2 yamt 191 1.1.2.2 yamt void *sc_sdhook; 192 1.1.2.2 yamt void *sc_rx_ih; 193 1.1.2.2 yamt void *sc_tx_ih; 194 1.1.2.2 yamt 195 1.1.2.2 yamt bus_dma_tag_t sc_dmat; 196 1.1.2.2 yamt }; 197 1.1.2.2 yamt 198 1.1.2.2 yamt /* Device interface. */ 199 1.1.2.2 yamt static void temac_attach(struct device *, struct device *, void *); 200 1.1.2.2 yamt 201 1.1.2.2 yamt /* Ifnet interface. */ 202 1.1.2.2 yamt static int temac_init(struct ifnet *); 203 1.1.2.2 yamt static int temac_ioctl(struct ifnet *, u_long, caddr_t); 204 1.1.2.2 yamt static void temac_start(struct ifnet *); 205 1.1.2.2 yamt static void temac_stop(struct ifnet *, int); 206 1.1.2.2 yamt 207 1.1.2.2 yamt /* Media management. */ 208 1.1.2.2 yamt static int temac_mediachange(struct ifnet *); 209 1.1.2.2 yamt static void temac_mediastatus(struct ifnet *, struct ifmediareq *); 210 1.1.2.2 yamt static int temac_mii_readreg(struct device *, int, int); 211 1.1.2.2 yamt static void temac_mii_statchg(struct device *); 212 1.1.2.2 yamt static void temac_mii_tick(void *); 213 1.1.2.2 yamt static void temac_mii_writereg(struct device *, int, int, int); 214 1.1.2.2 yamt 215 1.1.2.2 yamt /* Indirect hooks. */ 216 1.1.2.2 yamt static void temac_shutdown(void *); 217 1.1.2.2 yamt static void temac_rx_intr(void *); 218 1.1.2.2 yamt static void temac_tx_intr(void *); 219 1.1.2.2 yamt 220 1.1.2.2 yamt /* Tools. */ 221 1.1.2.2 yamt static inline void temac_rxcdsync(struct temac_softc *, int, int, int); 222 1.1.2.2 yamt static inline void temac_txcdsync(struct temac_softc *, int, int, int); 223 1.1.2.2 yamt static void temac_txreap(struct temac_softc *); 224 1.1.2.2 yamt static void temac_rxreap(struct temac_softc *); 225 1.1.2.2 yamt static int temac_rxalloc(struct temac_softc *, int, int); 226 1.1.2.2 yamt static void temac_rxtimo(void *); 227 1.1.2.2 yamt static void temac_rxdrain(struct temac_softc *); 228 1.1.2.2 yamt static void temac_reset(struct temac_softc *); 229 1.1.2.2 yamt static void temac_txkick(struct temac_softc *); 230 1.1.2.2 yamt 231 1.1.2.2 yamt /* Register access. */ 232 1.1.2.2 yamt static inline void gmi_write_8(uint32_t, uint32_t, uint32_t); 233 1.1.2.2 yamt static inline void gmi_write_4(uint32_t, uint32_t); 234 1.1.2.2 yamt static inline void gmi_read_8(uint32_t, uint32_t *, uint32_t *); 235 1.1.2.2 yamt static inline uint32_t gmi_read_4(uint32_t); 236 1.1.2.2 yamt static inline void hif_wait_stat(uint32_t); 237 1.1.2.2 yamt 238 1.1.2.2 yamt #define cdmac_rx_stat(sc) \ 239 1.1.2.2 yamt bus_space_read_4((sc)->sc_dma_rxt, (sc)->sc_dma_rsh, 0 /* XXX hack */) 240 1.1.2.2 yamt 241 1.1.2.2 yamt #define cdmac_rx_reset(sc) \ 242 1.1.2.2 yamt bus_space_write_4((sc)->sc_dma_rxt, (sc)->sc_dma_rsh, 0, CDMAC_STAT_RESET) 243 1.1.2.2 yamt 244 1.1.2.2 yamt #define cdmac_rx_start(sc, val) \ 245 1.1.2.2 yamt bus_space_write_4((sc)->sc_dma_rxt, (sc)->sc_dma_rxh, CDMAC_CURDESC, (val)) 246 1.1.2.2 yamt 247 1.1.2.2 yamt #define cdmac_tx_stat(sc) \ 248 1.1.2.2 yamt bus_space_read_4((sc)->sc_dma_txt, (sc)->sc_dma_tsh, 0 /* XXX hack */) 249 1.1.2.2 yamt 250 1.1.2.2 yamt #define cdmac_tx_reset(sc) \ 251 1.1.2.2 yamt bus_space_write_4((sc)->sc_dma_txt, (sc)->sc_dma_tsh, 0, CDMAC_STAT_RESET) 252 1.1.2.2 yamt 253 1.1.2.2 yamt #define cdmac_tx_start(sc, val) \ 254 1.1.2.2 yamt bus_space_write_4((sc)->sc_dma_txt, (sc)->sc_dma_txh, CDMAC_CURDESC, (val)) 255 1.1.2.2 yamt 256 1.1.2.2 yamt 257 1.1.2.2 yamt CFATTACH_DECL(temac, sizeof(struct temac_softc), 258 1.1.2.2 yamt xcvbus_child_match, temac_attach, NULL, NULL); 259 1.1.2.2 yamt 260 1.1.2.2 yamt 261 1.1.2.2 yamt /* 262 1.1.2.2 yamt * Private bus utilities. 263 1.1.2.2 yamt */ 264 1.1.2.2 yamt static inline void 265 1.1.2.2 yamt hif_wait_stat(uint32_t mask) 266 1.1.2.2 yamt { 267 1.1.2.2 yamt int i = 0; 268 1.1.2.2 yamt 269 1.1.2.2 yamt while (mask != (mfidcr(IDCR_HIF_STAT) & mask)) { 270 1.1.2.2 yamt if (i++ > 100) { 271 1.1.2.2 yamt printf("%s: timeout waiting for 0x%08x\n", 272 1.1.2.2 yamt __func__, mask); 273 1.1.2.2 yamt break; 274 1.1.2.2 yamt } 275 1.1.2.2 yamt delay(5); 276 1.1.2.2 yamt } 277 1.1.2.2 yamt 278 1.1.2.2 yamt TRACEREG(("%s: stat %#08x loops %d\n", __func__, mask, i)); 279 1.1.2.2 yamt } 280 1.1.2.2 yamt 281 1.1.2.2 yamt static inline void 282 1.1.2.2 yamt gmi_write_4(uint32_t addr, uint32_t lo) 283 1.1.2.2 yamt { 284 1.1.2.2 yamt mtidcr(IDCR_HIF_ARG0, lo); 285 1.1.2.2 yamt mtidcr(IDCR_HIF_CTRL, (addr & HIF_CTRL_GMIADDR) | HIF_CTRL_WRITE); 286 1.1.2.2 yamt hif_wait_stat(HIF_STAT_GMIWR); 287 1.1.2.2 yamt 288 1.1.2.2 yamt TRACEREG(("%s: %#08x <- %#08x\n", __func__, addr, lo)); 289 1.1.2.2 yamt } 290 1.1.2.2 yamt 291 1.1.2.2 yamt static inline void 292 1.1.2.2 yamt gmi_write_8(uint32_t addr, uint32_t lo, uint32_t hi) 293 1.1.2.2 yamt { 294 1.1.2.2 yamt mtidcr(IDCR_HIF_ARG1, hi); 295 1.1.2.2 yamt gmi_write_4(addr, lo); 296 1.1.2.2 yamt } 297 1.1.2.2 yamt 298 1.1.2.2 yamt static inline void 299 1.1.2.2 yamt gmi_read_8(uint32_t addr, uint32_t *lo, uint32_t *hi) 300 1.1.2.2 yamt { 301 1.1.2.2 yamt *lo = gmi_read_4(addr); 302 1.1.2.2 yamt *hi = mfidcr(IDCR_HIF_ARG1); 303 1.1.2.2 yamt } 304 1.1.2.2 yamt 305 1.1.2.2 yamt static inline uint32_t 306 1.1.2.2 yamt gmi_read_4(uint32_t addr) 307 1.1.2.2 yamt { 308 1.1.2.2 yamt uint32_t res; 309 1.1.2.2 yamt 310 1.1.2.2 yamt mtidcr(IDCR_HIF_CTRL, addr & HIF_CTRL_GMIADDR); 311 1.1.2.2 yamt hif_wait_stat(HIF_STAT_GMIRR); 312 1.1.2.2 yamt 313 1.1.2.2 yamt res = mfidcr(IDCR_HIF_ARG0); 314 1.1.2.2 yamt TRACEREG(("%s: %#08x -> %#08x\n", __func__, addr, res)); 315 1.1.2.2 yamt return (res); 316 1.1.2.2 yamt } 317 1.1.2.2 yamt 318 1.1.2.2 yamt /* 319 1.1.2.2 yamt * Generic device. 320 1.1.2.2 yamt */ 321 1.1.2.2 yamt static void 322 1.1.2.2 yamt temac_attach(struct device *parent, struct device *self, void *aux) 323 1.1.2.2 yamt { 324 1.1.2.2 yamt struct xcvbus_attach_args *vaa = aux; 325 1.1.2.2 yamt struct ll_dmac *rx = vaa->vaa_rx_dmac; 326 1.1.2.2 yamt struct ll_dmac *tx = vaa->vaa_tx_dmac; 327 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)self; 328 1.1.2.2 yamt struct ifnet *ifp = &sc->sc_if; 329 1.1.2.2 yamt struct mii_data *mii = &sc->sc_mii; 330 1.1.2.2 yamt uint8_t enaddr[ETHER_ADDR_LEN]; 331 1.1.2.2 yamt bus_dma_segment_t seg; 332 1.1.2.2 yamt int error, nseg, i; 333 1.1.2.2 yamt 334 1.1.2.2 yamt printf(": TEMAC\n"); /* XXX will be LL_TEMAC, PLB_TEMAC */ 335 1.1.2.2 yamt 336 1.1.2.2 yamt KASSERT(rx); 337 1.1.2.2 yamt KASSERT(tx); 338 1.1.2.2 yamt 339 1.1.2.2 yamt sc->sc_dmat = vaa->vaa_dmat; 340 1.1.2.2 yamt sc->sc_dead = 0; 341 1.1.2.2 yamt sc->sc_rx_drained = 1; 342 1.1.2.2 yamt sc->sc_txbusy = 0; 343 1.1.2.2 yamt sc->sc_iot = vaa->vaa_iot; 344 1.1.2.2 yamt sc->sc_dma_rxt = rx->dmac_iot; 345 1.1.2.2 yamt sc->sc_dma_txt = tx->dmac_iot; 346 1.1.2.2 yamt 347 1.1.2.2 yamt /* 348 1.1.2.2 yamt * Map HIF and receive/transmit dmac registers. 349 1.1.2.2 yamt */ 350 1.1.2.2 yamt if ((error = bus_space_map(vaa->vaa_iot, vaa->vaa_addr, TEMAC_SIZE, 0, 351 1.1.2.2 yamt &sc->sc_ioh)) != 0) { 352 1.1.2.2 yamt printf("%s: could not map registers\n", device_xname(self)); 353 1.1.2.2 yamt goto fail_0; 354 1.1.2.2 yamt } 355 1.1.2.2 yamt 356 1.1.2.2 yamt if ((error = bus_space_map(sc->sc_dma_rxt, rx->dmac_ctrl_addr, 357 1.1.2.2 yamt CDMAC_CTRL_SIZE, 0, &sc->sc_dma_rxh)) != 0) { 358 1.1.2.2 yamt printf("%s: could not map Rx control registers\n", 359 1.1.2.2 yamt device_xname(self)); 360 1.1.2.2 yamt goto fail_0; 361 1.1.2.2 yamt } 362 1.1.2.2 yamt if ((error = bus_space_map(sc->sc_dma_rxt, rx->dmac_stat_addr, 363 1.1.2.2 yamt CDMAC_STAT_SIZE, 0, &sc->sc_dma_rsh)) != 0) { 364 1.1.2.2 yamt printf("%s: could not map Rx status register\n", 365 1.1.2.2 yamt device_xname(self)); 366 1.1.2.2 yamt goto fail_0; 367 1.1.2.2 yamt } 368 1.1.2.2 yamt 369 1.1.2.2 yamt if ((error = bus_space_map(sc->sc_dma_txt, tx->dmac_ctrl_addr, 370 1.1.2.2 yamt CDMAC_CTRL_SIZE, 0, &sc->sc_dma_txh)) != 0) { 371 1.1.2.2 yamt printf("%s: could not map Tx control registers\n", 372 1.1.2.2 yamt device_xname(self)); 373 1.1.2.2 yamt goto fail_0; 374 1.1.2.2 yamt } 375 1.1.2.2 yamt if ((error = bus_space_map(sc->sc_dma_txt, tx->dmac_stat_addr, 376 1.1.2.2 yamt CDMAC_STAT_SIZE, 0, &sc->sc_dma_tsh)) != 0) { 377 1.1.2.2 yamt printf("%s: could not map Tx status register\n", 378 1.1.2.2 yamt device_xname(self)); 379 1.1.2.2 yamt goto fail_0; 380 1.1.2.2 yamt } 381 1.1.2.2 yamt 382 1.1.2.2 yamt /* 383 1.1.2.2 yamt * Allocate and initialize DMA control chains. 384 1.1.2.2 yamt */ 385 1.1.2.2 yamt if ((error = bus_dmamem_alloc(sc->sc_dmat, 386 1.1.2.2 yamt sizeof(struct temac_control), 8, 0, &seg, 1, &nseg, 0)) != 0) { 387 1.1.2.2 yamt printf("%s: could not allocate control data\n", 388 1.1.2.2 yamt sc->sc_dev.dv_xname); 389 1.1.2.2 yamt goto fail_0; 390 1.1.2.2 yamt } 391 1.1.2.2 yamt 392 1.1.2.2 yamt if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 393 1.1.2.2 yamt sizeof(struct temac_control), 394 1.1.2.2 yamt (caddr_t *)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 395 1.1.2.2 yamt printf("%s: could not map control data\n", 396 1.1.2.2 yamt sc->sc_dev.dv_xname); 397 1.1.2.2 yamt goto fail_1; 398 1.1.2.2 yamt } 399 1.1.2.2 yamt 400 1.1.2.2 yamt if ((error = bus_dmamap_create(sc->sc_dmat, 401 1.1.2.2 yamt sizeof(struct temac_control), 1, 402 1.1.2.2 yamt sizeof(struct temac_control), 0, 0, &sc->sc_control_dmap)) != 0) { 403 1.1.2.2 yamt printf("%s: could not create control data DMA map\n", 404 1.1.2.2 yamt sc->sc_dev.dv_xname); 405 1.1.2.2 yamt goto fail_2; 406 1.1.2.2 yamt } 407 1.1.2.2 yamt 408 1.1.2.2 yamt if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_control_dmap, 409 1.1.2.2 yamt sc->sc_control_data, sizeof(struct temac_control), NULL, 0)) != 0) { 410 1.1.2.2 yamt printf("%s: could not load control data DMA map\n", 411 1.1.2.2 yamt sc->sc_dev.dv_xname); 412 1.1.2.2 yamt goto fail_3; 413 1.1.2.2 yamt } 414 1.1.2.2 yamt 415 1.1.2.2 yamt /* 416 1.1.2.2 yamt * Link descriptor chains. 417 1.1.2.2 yamt */ 418 1.1.2.2 yamt memset(sc->sc_control_data, 0, sizeof(struct temac_control)); 419 1.1.2.2 yamt 420 1.1.2.2 yamt for (i = 0; i < TEMAC_NTXDESC; i++) { 421 1.1.2.2 yamt sc->sc_txdescs[i].desc_next = sc->sc_cdaddr + 422 1.1.2.2 yamt TEMAC_TXDOFF(TEMAC_TXNEXT(i)); 423 1.1.2.2 yamt sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE; 424 1.1.2.2 yamt } 425 1.1.2.2 yamt for (i = 0; i < TEMAC_NRXDESC; i++) { 426 1.1.2.2 yamt sc->sc_rxdescs[i].desc_next = sc->sc_cdaddr + 427 1.1.2.2 yamt TEMAC_RXDOFF(TEMAC_RXNEXT(i)); 428 1.1.2.2 yamt sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE; 429 1.1.2.2 yamt } 430 1.1.2.2 yamt 431 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->sc_control_dmap, 0, 432 1.1.2.2 yamt sizeof(struct temac_control), 433 1.1.2.2 yamt BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 434 1.1.2.2 yamt 435 1.1.2.2 yamt /* 436 1.1.2.2 yamt * Initialize software state for transmit/receive jobs. 437 1.1.2.2 yamt */ 438 1.1.2.2 yamt for (i = 0; i < TEMAC_TXQLEN; i++) { 439 1.1.2.2 yamt if ((error = bus_dmamap_create(sc->sc_dmat, 440 1.1.2.2 yamt ETHER_MAX_LEN_JUMBO, TEMAC_NTXSEG, ETHER_MAX_LEN_JUMBO, 441 1.1.2.2 yamt 0, 0, &sc->sc_txsoft[i].txs_dmap)) != 0) { 442 1.1.2.2 yamt printf("%s: could not create Tx DMA map %d\n", 443 1.1.2.2 yamt sc->sc_dev.dv_xname, i); 444 1.1.2.2 yamt goto fail_4; 445 1.1.2.2 yamt } 446 1.1.2.2 yamt sc->sc_txsoft[i].txs_mbuf = NULL; 447 1.1.2.2 yamt sc->sc_txsoft[i].txs_last = 0; 448 1.1.2.2 yamt } 449 1.1.2.2 yamt 450 1.1.2.2 yamt for (i = 0; i < TEMAC_NRXDESC; i++) { 451 1.1.2.2 yamt if ((error = bus_dmamap_create(sc->sc_dmat, 452 1.1.2.2 yamt MCLBYTES, TEMAC_NRXSEG, MCLBYTES, 0, 0, 453 1.1.2.2 yamt &sc->sc_rxsoft[i].rxs_dmap)) != 0) { 454 1.1.2.2 yamt printf("%s: could not create Rx DMA map %d\n", 455 1.1.2.2 yamt sc->sc_dev.dv_xname, i); 456 1.1.2.2 yamt goto fail_5; 457 1.1.2.2 yamt } 458 1.1.2.2 yamt sc->sc_rxsoft[i].rxs_mbuf = NULL; 459 1.1.2.2 yamt } 460 1.1.2.2 yamt 461 1.1.2.2 yamt /* 462 1.1.2.2 yamt * Setup transfer interrupt handlers. 463 1.1.2.2 yamt */ 464 1.1.2.2 yamt error = ENOMEM; 465 1.1.2.2 yamt 466 1.1.2.2 yamt sc->sc_rx_ih = ll_dmac_intr_establish(rx->dmac_chan, 467 1.1.2.2 yamt temac_rx_intr, sc); 468 1.1.2.2 yamt if (sc->sc_rx_ih == NULL) { 469 1.1.2.2 yamt printf("%s: could not establish Rx interrupt\n", 470 1.1.2.2 yamt device_xname(self)); 471 1.1.2.2 yamt goto fail_5; 472 1.1.2.2 yamt } 473 1.1.2.2 yamt 474 1.1.2.2 yamt sc->sc_tx_ih = ll_dmac_intr_establish(tx->dmac_chan, 475 1.1.2.2 yamt temac_tx_intr, sc); 476 1.1.2.2 yamt if (sc->sc_tx_ih == NULL) { 477 1.1.2.2 yamt printf("%s: could not establish Tx interrupt\n", 478 1.1.2.2 yamt device_xname(self)); 479 1.1.2.2 yamt goto fail_6; 480 1.1.2.2 yamt } 481 1.1.2.2 yamt 482 1.1.2.2 yamt /* XXXFreza: faked, should read unicast address filter. */ 483 1.1.2.2 yamt enaddr[0] = 0x00; 484 1.1.2.2 yamt enaddr[1] = 0x11; 485 1.1.2.2 yamt enaddr[2] = 0x17; 486 1.1.2.2 yamt enaddr[3] = 0xff; 487 1.1.2.2 yamt enaddr[4] = 0xff; 488 1.1.2.2 yamt enaddr[5] = 0x01; 489 1.1.2.2 yamt 490 1.1.2.2 yamt /* 491 1.1.2.2 yamt * Initialize the TEMAC. 492 1.1.2.2 yamt */ 493 1.1.2.2 yamt temac_reset(sc); 494 1.1.2.2 yamt 495 1.1.2.2 yamt /* Configure MDIO link. */ 496 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_MGMTCF, GMI_MGMT_CLKDIV_100MHz | GMI_MGMT_MDIO); 497 1.1.2.2 yamt 498 1.1.2.2 yamt /* Initialize PHY. */ 499 1.1.2.2 yamt mii->mii_ifp = ifp; 500 1.1.2.2 yamt mii->mii_readreg = temac_mii_readreg; 501 1.1.2.2 yamt mii->mii_writereg = temac_mii_writereg; 502 1.1.2.2 yamt mii->mii_statchg = temac_mii_statchg; 503 1.1.2.2 yamt ifmedia_init(&mii->mii_media, 0, temac_mediachange, 504 1.1.2.2 yamt temac_mediastatus); 505 1.1.2.2 yamt 506 1.1.2.2 yamt mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 507 1.1.2.2 yamt MII_OFFSET_ANY, 0); 508 1.1.2.2 yamt if (LIST_FIRST(&mii->mii_phys) == NULL) { 509 1.1.2.2 yamt ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 510 1.1.2.2 yamt ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 511 1.1.2.2 yamt } else { 512 1.1.2.2 yamt ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 513 1.1.2.2 yamt } 514 1.1.2.2 yamt 515 1.1.2.2 yamt /* Hold PHY in reset. */ 516 1.1.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_ioh, TEMAC_RESET, TEMAC_RESET_PHY); 517 1.1.2.2 yamt 518 1.1.2.2 yamt /* Reset EMAC. */ 519 1.1.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_ioh, TEMAC_RESET, 520 1.1.2.2 yamt TEMAC_RESET_EMAC); 521 1.1.2.2 yamt delay(10000); 522 1.1.2.2 yamt 523 1.1.2.2 yamt /* Reset peripheral, awakes PHY and EMAC. */ 524 1.1.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_ioh, TEMAC_RESET, 525 1.1.2.2 yamt TEMAC_RESET_PERIPH); 526 1.1.2.2 yamt delay(40000); 527 1.1.2.2 yamt 528 1.1.2.2 yamt /* (Re-)Configure MDIO link. */ 529 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_MGMTCF, GMI_MGMT_CLKDIV_100MHz | GMI_MGMT_MDIO); 530 1.1.2.2 yamt 531 1.1.2.2 yamt /* 532 1.1.2.2 yamt * Hook up with network stack. 533 1.1.2.2 yamt */ 534 1.1.2.2 yamt strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 535 1.1.2.2 yamt ifp->if_softc = sc; 536 1.1.2.2 yamt ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 1.1.2.2 yamt ifp->if_ioctl = temac_ioctl; 538 1.1.2.2 yamt ifp->if_start = temac_start; 539 1.1.2.2 yamt ifp->if_init = temac_init; 540 1.1.2.2 yamt ifp->if_stop = temac_stop; 541 1.1.2.2 yamt ifp->if_watchdog = NULL; 542 1.1.2.2 yamt IFQ_SET_READY(&ifp->if_snd); 543 1.1.2.2 yamt IFQ_SET_MAXLEN(&ifp->if_snd, TEMAC_TXQLEN); 544 1.1.2.2 yamt 545 1.1.2.2 yamt sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 546 1.1.2.2 yamt 547 1.1.2.2 yamt if_attach(ifp); 548 1.1.2.2 yamt ether_ifattach(ifp, enaddr); 549 1.1.2.2 yamt 550 1.1.2.2 yamt sc->sc_sdhook = shutdownhook_establish(temac_shutdown, sc); 551 1.1.2.2 yamt if (sc->sc_sdhook == NULL) 552 1.1.2.2 yamt printf("%s: WARNING: unable to establish shutdown hook\n", 553 1.1.2.2 yamt device_xname(self)); 554 1.1.2.2 yamt 555 1.1.2.2 yamt callout_setfunc(&sc->sc_mii_tick, temac_mii_tick, sc); 556 1.1.2.2 yamt callout_setfunc(&sc->sc_rx_timo, temac_rxtimo, sc); 557 1.1.2.2 yamt 558 1.1.2.2 yamt return ; 559 1.1.2.2 yamt 560 1.1.2.2 yamt fail_6: 561 1.1.2.2 yamt ll_dmac_intr_disestablish(rx->dmac_chan, sc->sc_rx_ih); 562 1.1.2.2 yamt i = TEMAC_NRXDESC; 563 1.1.2.2 yamt fail_5: 564 1.1.2.2 yamt for (--i; i >= 0; i--) 565 1.1.2.2 yamt bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmap); 566 1.1.2.2 yamt i = TEMAC_TXQLEN; 567 1.1.2.2 yamt fail_4: 568 1.1.2.2 yamt for (--i; i >= 0; i--) 569 1.1.2.2 yamt bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmap); 570 1.1.2.2 yamt fail_3: 571 1.1.2.2 yamt bus_dmamap_destroy(sc->sc_dmat, sc->sc_control_dmap); 572 1.1.2.2 yamt fail_2: 573 1.1.2.2 yamt bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 574 1.1.2.2 yamt sizeof(struct temac_control)); 575 1.1.2.2 yamt fail_1: 576 1.1.2.2 yamt bus_dmamem_free(sc->sc_dmat, &seg, nseg); 577 1.1.2.2 yamt fail_0: 578 1.1.2.2 yamt printf("%s: error = %d\n", device_xname(self), error); 579 1.1.2.2 yamt } 580 1.1.2.2 yamt 581 1.1.2.2 yamt /* 582 1.1.2.2 yamt * Network device. 583 1.1.2.2 yamt */ 584 1.1.2.2 yamt static int 585 1.1.2.2 yamt temac_init(struct ifnet *ifp) 586 1.1.2.2 yamt { 587 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 588 1.1.2.2 yamt uint32_t rcr, tcr; 589 1.1.2.2 yamt int i, error; 590 1.1.2.2 yamt 591 1.1.2.2 yamt /* Reset DMA channels. */ 592 1.1.2.2 yamt cdmac_tx_reset(sc); 593 1.1.2.2 yamt cdmac_rx_reset(sc); 594 1.1.2.2 yamt 595 1.1.2.2 yamt /* Set current media. */ 596 1.1.2.2 yamt mii_mediachg(&sc->sc_mii); 597 1.1.2.2 yamt callout_schedule(&sc->sc_mii_tick, hz); 598 1.1.2.2 yamt 599 1.1.2.2 yamt /* Enable EMAC engine. */ 600 1.1.2.2 yamt rcr = (gmi_read_4(TEMAC_GMI_RXCF1) | GMI_RX_ENABLE) & 601 1.1.2.2 yamt ~(GMI_RX_JUMBO | GMI_RX_FCS); 602 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_RXCF1, rcr); 603 1.1.2.2 yamt 604 1.1.2.2 yamt tcr = (gmi_read_4(TEMAC_GMI_TXCF) | GMI_TX_ENABLE) & 605 1.1.2.2 yamt ~(GMI_TX_JUMBO | GMI_TX_FCS); 606 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_TXCF, tcr); 607 1.1.2.2 yamt 608 1.1.2.2 yamt /* XXXFreza: Force promiscuous mode, for now. */ 609 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_AFM, GMI_AFM_PROMISC); 610 1.1.2.2 yamt ifp->if_flags |= IFF_PROMISC; 611 1.1.2.2 yamt 612 1.1.2.2 yamt /* Rx/Tx queues are drained -- either from attach() or stop(). */ 613 1.1.2.2 yamt sc->sc_txsfree = TEMAC_TXQLEN; 614 1.1.2.2 yamt sc->sc_txsreap = 0; 615 1.1.2.2 yamt sc->sc_txscur = 0; 616 1.1.2.2 yamt 617 1.1.2.2 yamt sc->sc_txfree = TEMAC_NTXDESC; 618 1.1.2.2 yamt sc->sc_txreap = 0; 619 1.1.2.2 yamt sc->sc_txcur = 0; 620 1.1.2.2 yamt 621 1.1.2.2 yamt sc->sc_rxreap = 0; 622 1.1.2.2 yamt 623 1.1.2.2 yamt /* Allocate and map receive buffers. */ 624 1.1.2.2 yamt if (sc->sc_rx_drained) { 625 1.1.2.2 yamt for (i = 0; i < TEMAC_NRXDESC; i++) { 626 1.1.2.2 yamt if ((error = temac_rxalloc(sc, i, 1)) != 0) { 627 1.1.2.2 yamt printf("%s: failed to allocate Rx " 628 1.1.2.2 yamt "descriptor %d\n", 629 1.1.2.2 yamt sc->sc_dev.dv_xname, i); 630 1.1.2.2 yamt 631 1.1.2.2 yamt temac_rxdrain(sc); 632 1.1.2.2 yamt return (error); 633 1.1.2.2 yamt } 634 1.1.2.2 yamt } 635 1.1.2.2 yamt sc->sc_rx_drained = 0; 636 1.1.2.2 yamt 637 1.1.2.2 yamt temac_rxcdsync(sc, 0, TEMAC_NRXDESC, 638 1.1.2.2 yamt BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 639 1.1.2.2 yamt cdmac_rx_start(sc, sc->sc_cdaddr + TEMAC_RXDOFF(0)); 640 1.1.2.2 yamt } 641 1.1.2.2 yamt 642 1.1.2.2 yamt ifp->if_flags |= IFF_RUNNING; 643 1.1.2.2 yamt ifp->if_flags &= ~IFF_OACTIVE; 644 1.1.2.2 yamt 645 1.1.2.2 yamt return (0); 646 1.1.2.2 yamt } 647 1.1.2.2 yamt 648 1.1.2.2 yamt static int 649 1.1.2.2 yamt temac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 650 1.1.2.2 yamt { 651 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 652 1.1.2.2 yamt struct ifreq *ifr = (struct ifreq *)data; 653 1.1.2.2 yamt int s, ret; 654 1.1.2.2 yamt 655 1.1.2.2 yamt s = splnet(); 656 1.1.2.2 yamt if (sc->sc_dead) { 657 1.1.2.2 yamt ret = EIO; 658 1.1.2.2 yamt } else 659 1.1.2.2 yamt switch (cmd) { 660 1.1.2.2 yamt case SIOCSIFMEDIA: 661 1.1.2.2 yamt case SIOCGIFMEDIA: 662 1.1.2.2 yamt ret = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, 663 1.1.2.2 yamt cmd); 664 1.1.2.2 yamt break; 665 1.1.2.2 yamt 666 1.1.2.2 yamt default: 667 1.1.2.2 yamt ret = ether_ioctl(ifp, cmd, data); 668 1.1.2.2 yamt break; 669 1.1.2.2 yamt } 670 1.1.2.2 yamt 671 1.1.2.2 yamt splx(s); 672 1.1.2.2 yamt return (ret); 673 1.1.2.2 yamt } 674 1.1.2.2 yamt 675 1.1.2.2 yamt static void 676 1.1.2.2 yamt temac_start(struct ifnet *ifp) 677 1.1.2.2 yamt { 678 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 679 1.1.2.2 yamt struct temac_txsoft *txs; 680 1.1.2.2 yamt struct mbuf *m; 681 1.1.2.2 yamt bus_dmamap_t dmap; 682 1.1.2.2 yamt int error, head, nsegs, i; 683 1.1.2.2 yamt 684 1.1.2.2 yamt nsegs = 0; 685 1.1.2.2 yamt head = sc->sc_txcur; 686 1.1.2.2 yamt txs = NULL; /* gcc */ 687 1.1.2.2 yamt 688 1.1.2.2 yamt if (sc->sc_dead) 689 1.1.2.2 yamt return; 690 1.1.2.2 yamt 691 1.1.2.2 yamt KASSERT(sc->sc_txfree >= 0); 692 1.1.2.2 yamt KASSERT(sc->sc_txsfree >= 0); 693 1.1.2.2 yamt 694 1.1.2.2 yamt /* 695 1.1.2.2 yamt * Push mbufs into descriptor chain until we drain the interface 696 1.1.2.2 yamt * queue or run out of descriptors. We'll mark the first segment 697 1.1.2.2 yamt * as "done" in hope that we might put CDMAC interrupt above IPL_NET 698 1.1.2.2 yamt * and have it start jobs & mark packets for GC preemtively for 699 1.1.2.2 yamt * us -- creativity due to limitations in CDMAC transfer engine 700 1.1.2.2 yamt * (it really consumes lists, not circular queues, AFAICS). 701 1.1.2.2 yamt * 702 1.1.2.2 yamt * We schedule one interrupt per Tx batch. 703 1.1.2.2 yamt */ 704 1.1.2.2 yamt while (1) { 705 1.1.2.2 yamt IFQ_POLL(&ifp->if_snd, m); 706 1.1.2.2 yamt if (m == NULL) 707 1.1.2.2 yamt break; 708 1.1.2.2 yamt 709 1.1.2.2 yamt if (sc->sc_txsfree == 0) { 710 1.1.2.2 yamt ifp->if_flags |= IFF_OACTIVE; 711 1.1.2.2 yamt break; 712 1.1.2.2 yamt } 713 1.1.2.2 yamt 714 1.1.2.2 yamt txs = &sc->sc_txsoft[sc->sc_txscur]; 715 1.1.2.2 yamt dmap = txs->txs_dmap; 716 1.1.2.2 yamt 717 1.1.2.2 yamt if (txs->txs_mbuf != NULL) 718 1.1.2.2 yamt printf("FOO\n"); 719 1.1.2.2 yamt if (txs->txs_last) 720 1.1.2.2 yamt printf("BAR\n"); 721 1.1.2.2 yamt 722 1.1.2.2 yamt if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmap, m, 723 1.1.2.2 yamt BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0) { 724 1.1.2.2 yamt if (error == EFBIG) { 725 1.1.2.2 yamt printf("%s: Tx consumes too many segments, " 726 1.1.2.2 yamt "dropped\n", sc->sc_dev.dv_xname); 727 1.1.2.2 yamt IFQ_DEQUEUE(&ifp->if_snd, m); 728 1.1.2.2 yamt m_freem(m); 729 1.1.2.2 yamt continue; 730 1.1.2.2 yamt } else { 731 1.1.2.2 yamt printf("%s: Tx stall due to resource " 732 1.1.2.2 yamt "shortage\n", sc->sc_dev.dv_xname); 733 1.1.2.2 yamt break; 734 1.1.2.2 yamt } 735 1.1.2.2 yamt } 736 1.1.2.2 yamt 737 1.1.2.2 yamt /* 738 1.1.2.2 yamt * If we're short on DMA descriptors, notify upper layers 739 1.1.2.2 yamt * and leave this packet for later. 740 1.1.2.2 yamt */ 741 1.1.2.2 yamt if (dmap->dm_nsegs > sc->sc_txfree) { 742 1.1.2.2 yamt bus_dmamap_unload(sc->sc_dmat, dmap); 743 1.1.2.2 yamt ifp->if_flags |= IFF_OACTIVE; 744 1.1.2.2 yamt break; 745 1.1.2.2 yamt } 746 1.1.2.2 yamt 747 1.1.2.2 yamt IFQ_DEQUEUE(&ifp->if_snd, m); 748 1.1.2.2 yamt 749 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 750 1.1.2.2 yamt BUS_DMASYNC_PREWRITE); 751 1.1.2.2 yamt txs->txs_mbuf = m; 752 1.1.2.2 yamt 753 1.1.2.2 yamt /* 754 1.1.2.2 yamt * Map the packet into descriptor chain. XXX We'll want 755 1.1.2.2 yamt * to fill checksum offload commands here. 756 1.1.2.2 yamt * 757 1.1.2.2 yamt * We would be in a race if we weren't blocking CDMAC intr 758 1.1.2.2 yamt * at this point -- we need to be locked against txreap() 759 1.1.2.2 yamt * because of dmasync ops. 760 1.1.2.2 yamt */ 761 1.1.2.2 yamt 762 1.1.2.2 yamt temac_txcdsync(sc, sc->sc_txcur, dmap->dm_nsegs, 763 1.1.2.2 yamt BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 764 1.1.2.2 yamt 765 1.1.2.2 yamt for (i = 0; i < dmap->dm_nsegs; i++) { 766 1.1.2.2 yamt sc->sc_txdescs[sc->sc_txcur].desc_addr = 767 1.1.2.2 yamt dmap->dm_segs[i].ds_addr; 768 1.1.2.2 yamt sc->sc_txdescs[sc->sc_txcur].desc_size = 769 1.1.2.2 yamt dmap->dm_segs[i].ds_len; 770 1.1.2.2 yamt sc->sc_txdescs[sc->sc_txcur].desc_stat = 771 1.1.2.2 yamt (i == 0 ? CDMAC_STAT_SOP : 0) | 772 1.1.2.2 yamt (i == (dmap->dm_nsegs - 1) ? CDMAC_STAT_EOP : 0); 773 1.1.2.2 yamt 774 1.1.2.2 yamt sc->sc_txcur = TEMAC_TXNEXT(sc->sc_txcur); 775 1.1.2.2 yamt } 776 1.1.2.2 yamt 777 1.1.2.2 yamt sc->sc_txfree -= dmap->dm_nsegs; 778 1.1.2.2 yamt nsegs += dmap->dm_nsegs; 779 1.1.2.2 yamt 780 1.1.2.2 yamt sc->sc_txscur = TEMAC_TXSNEXT(sc->sc_txscur); 781 1.1.2.2 yamt sc->sc_txsfree--; 782 1.1.2.2 yamt } 783 1.1.2.2 yamt 784 1.1.2.2 yamt /* Get data running if we queued any. */ 785 1.1.2.2 yamt if (nsegs > 0) { 786 1.1.2.2 yamt int tail = TEMAC_TXINC(sc->sc_txcur, -1); 787 1.1.2.2 yamt 788 1.1.2.2 yamt /* Mark the last packet in this job. */ 789 1.1.2.2 yamt txs->txs_last = 1; 790 1.1.2.2 yamt 791 1.1.2.2 yamt /* Mark the last descriptor in this job. */ 792 1.1.2.2 yamt sc->sc_txdescs[tail].desc_stat |= CDMAC_STAT_STOP | 793 1.1.2.2 yamt CDMAC_STAT_INTR; 794 1.1.2.2 yamt temac_txcdsync(sc, head, nsegs, 795 1.1.2.2 yamt BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 796 1.1.2.2 yamt 797 1.1.2.2 yamt temac_txkick(sc); 798 1.1.2.2 yamt #if TEMAC_TXDEBUG > 0 799 1.1.2.2 yamt printf("%s: start: txcur %03d -> %03d, nseg %03d\n", 800 1.1.2.2 yamt sc->sc_dev.dv_xname, head, sc->sc_txcur, nsegs); 801 1.1.2.2 yamt #endif 802 1.1.2.2 yamt } 803 1.1.2.2 yamt } 804 1.1.2.2 yamt 805 1.1.2.2 yamt static void 806 1.1.2.2 yamt temac_stop(struct ifnet *ifp, int disable) 807 1.1.2.2 yamt { 808 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 809 1.1.2.2 yamt struct temac_txsoft *txs; 810 1.1.2.2 yamt int i; 811 1.1.2.2 yamt 812 1.1.2.2 yamt #if TEMAC_DEBUG > 0 813 1.1.2.2 yamt printf("%s: stop\n", device_xname(&sc->sc_dev)); 814 1.1.2.2 yamt #endif 815 1.1.2.2 yamt 816 1.1.2.2 yamt /* Down the MII. */ 817 1.1.2.2 yamt callout_stop(&sc->sc_mii_tick); 818 1.1.2.2 yamt mii_down(&sc->sc_mii); 819 1.1.2.2 yamt 820 1.1.2.2 yamt /* Stop the engine. */ 821 1.1.2.2 yamt temac_reset(sc); 822 1.1.2.2 yamt 823 1.1.2.2 yamt /* Drain buffers queues (unconditionally). */ 824 1.1.2.2 yamt temac_rxdrain(sc); 825 1.1.2.2 yamt 826 1.1.2.2 yamt for (i = 0; i < TEMAC_TXQLEN; i++) { 827 1.1.2.2 yamt txs = &sc->sc_txsoft[i]; 828 1.1.2.2 yamt 829 1.1.2.2 yamt if (txs->txs_mbuf != NULL) { 830 1.1.2.2 yamt bus_dmamap_unload(sc->sc_dmat, txs->txs_dmap); 831 1.1.2.2 yamt m_freem(txs->txs_mbuf); 832 1.1.2.2 yamt txs->txs_mbuf = NULL; 833 1.1.2.2 yamt txs->txs_last = 0; 834 1.1.2.2 yamt } 835 1.1.2.2 yamt } 836 1.1.2.2 yamt sc->sc_txbusy = 0; 837 1.1.2.2 yamt 838 1.1.2.2 yamt /* Acknowledge we're down. */ 839 1.1.2.2 yamt ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 840 1.1.2.2 yamt } 841 1.1.2.2 yamt 842 1.1.2.2 yamt /* 843 1.1.2.2 yamt * Media management. 844 1.1.2.2 yamt */ 845 1.1.2.2 yamt static int 846 1.1.2.2 yamt temac_mediachange(struct ifnet *ifp) 847 1.1.2.2 yamt { 848 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 849 1.1.2.2 yamt 850 1.1.2.2 yamt if (ifp->if_flags & IFF_UP) 851 1.1.2.2 yamt mii_mediachg(&sc->sc_mii); 852 1.1.2.2 yamt return (0); 853 1.1.2.2 yamt } 854 1.1.2.2 yamt 855 1.1.2.2 yamt static void 856 1.1.2.2 yamt temac_mediastatus(struct ifnet *ifp, struct ifmediareq *imr) 857 1.1.2.2 yamt { 858 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)ifp->if_softc; 859 1.1.2.2 yamt 860 1.1.2.2 yamt mii_pollstat(&sc->sc_mii); 861 1.1.2.2 yamt 862 1.1.2.2 yamt imr->ifm_status = sc->sc_mii.mii_media_status; 863 1.1.2.2 yamt imr->ifm_active = sc->sc_mii.mii_media_active; 864 1.1.2.2 yamt } 865 1.1.2.2 yamt 866 1.1.2.2 yamt static int 867 1.1.2.2 yamt temac_mii_readreg(struct device *self, int phy, int reg) 868 1.1.2.2 yamt { 869 1.1.2.2 yamt mtidcr(IDCR_HIF_ARG0, (phy << 5) | reg); 870 1.1.2.2 yamt mtidcr(IDCR_HIF_CTRL, TEMAC_GMI_MII_ADDR); 871 1.1.2.2 yamt hif_wait_stat(HIF_STAT_MIIRR); 872 1.1.2.2 yamt 873 1.1.2.2 yamt return (int)mfidcr(IDCR_HIF_ARG0); 874 1.1.2.2 yamt } 875 1.1.2.2 yamt 876 1.1.2.2 yamt static void 877 1.1.2.2 yamt temac_mii_writereg(struct device *self, int phy, int reg, int val) 878 1.1.2.2 yamt { 879 1.1.2.2 yamt mtidcr(IDCR_HIF_ARG0, val); 880 1.1.2.2 yamt mtidcr(IDCR_HIF_CTRL, TEMAC_GMI_MII_WRVAL | HIF_CTRL_WRITE); 881 1.1.2.2 yamt mtidcr(IDCR_HIF_ARG0, (phy << 5) | reg); 882 1.1.2.2 yamt mtidcr(IDCR_HIF_CTRL, TEMAC_GMI_MII_ADDR | HIF_CTRL_WRITE); 883 1.1.2.2 yamt hif_wait_stat(HIF_STAT_MIIWR); 884 1.1.2.2 yamt } 885 1.1.2.2 yamt 886 1.1.2.2 yamt static void 887 1.1.2.2 yamt temac_mii_statchg(struct device *self) 888 1.1.2.2 yamt { 889 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)self; 890 1.1.2.2 yamt uint32_t rcf, tcf, mmc; 891 1.1.2.2 yamt 892 1.1.2.2 yamt /* Full/half duplex link. */ 893 1.1.2.2 yamt rcf = gmi_read_4(TEMAC_GMI_RXCF1); 894 1.1.2.2 yamt tcf = gmi_read_4(TEMAC_GMI_TXCF); 895 1.1.2.2 yamt 896 1.1.2.2 yamt if (sc->sc_mii.mii_media_active & IFM_FDX) { 897 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_RXCF1, rcf & ~GMI_RX_HDX); 898 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_TXCF, tcf & ~GMI_TX_HDX); 899 1.1.2.2 yamt } else { 900 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_RXCF1, rcf | GMI_RX_HDX); 901 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_TXCF, tcf | GMI_TX_HDX); 902 1.1.2.2 yamt } 903 1.1.2.2 yamt 904 1.1.2.2 yamt /* Link speed. */ 905 1.1.2.2 yamt mmc = gmi_read_4(TEMAC_GMI_MMC) & ~GMI_MMC_SPEED_MASK; 906 1.1.2.2 yamt 907 1.1.2.2 yamt switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 908 1.1.2.2 yamt case IFM_10_T: 909 1.1.2.2 yamt /* 910 1.1.2.2 yamt * XXXFreza: the GMAC is not happy with 10Mbit ethernet, 911 1.1.2.2 yamt * although the documentation claims it's supported. Maybe 912 1.1.2.2 yamt * it's just my equipment... 913 1.1.2.2 yamt */ 914 1.1.2.2 yamt mmc |= GMI_MMC_SPEED_10; 915 1.1.2.2 yamt break; 916 1.1.2.2 yamt case IFM_100_TX: 917 1.1.2.2 yamt mmc |= GMI_MMC_SPEED_100; 918 1.1.2.2 yamt break; 919 1.1.2.2 yamt case IFM_1000_T: 920 1.1.2.2 yamt mmc |= GMI_MMC_SPEED_1000; 921 1.1.2.2 yamt break; 922 1.1.2.2 yamt } 923 1.1.2.2 yamt 924 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_MMC, mmc); 925 1.1.2.2 yamt } 926 1.1.2.2 yamt 927 1.1.2.2 yamt static void 928 1.1.2.2 yamt temac_mii_tick(void *arg) 929 1.1.2.2 yamt { 930 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)arg; 931 1.1.2.2 yamt int s; 932 1.1.2.2 yamt 933 1.1.2.2 yamt if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 934 1.1.2.2 yamt return ; 935 1.1.2.2 yamt 936 1.1.2.2 yamt s = splnet(); 937 1.1.2.2 yamt mii_tick(&sc->sc_mii); 938 1.1.2.2 yamt splx(s); 939 1.1.2.2 yamt 940 1.1.2.2 yamt callout_schedule(&sc->sc_mii_tick, hz); 941 1.1.2.2 yamt } 942 1.1.2.2 yamt 943 1.1.2.2 yamt /* 944 1.1.2.2 yamt * External hooks. 945 1.1.2.2 yamt */ 946 1.1.2.2 yamt static void 947 1.1.2.2 yamt temac_shutdown(void *arg) 948 1.1.2.2 yamt { 949 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)arg; 950 1.1.2.2 yamt 951 1.1.2.2 yamt temac_reset(sc); 952 1.1.2.2 yamt } 953 1.1.2.2 yamt 954 1.1.2.2 yamt static void 955 1.1.2.2 yamt temac_tx_intr(void *arg) 956 1.1.2.2 yamt { 957 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)arg; 958 1.1.2.2 yamt uint32_t stat; 959 1.1.2.2 yamt 960 1.1.2.2 yamt /* XXX: We may need to splnet() here if cdmac(4) changes. */ 961 1.1.2.2 yamt 962 1.1.2.2 yamt if ((stat = cdmac_tx_stat(sc)) & CDMAC_STAT_ERROR) { 963 1.1.2.2 yamt printf("%s: transmit DMA is toast (%#08x), halted!\n", 964 1.1.2.2 yamt sc->sc_dev.dv_xname, stat); 965 1.1.2.2 yamt 966 1.1.2.2 yamt /* XXXFreza: how to signal this upstream? */ 967 1.1.2.2 yamt temac_stop(&sc->sc_if, 1); 968 1.1.2.2 yamt sc->sc_dead = 1; 969 1.1.2.2 yamt } 970 1.1.2.2 yamt 971 1.1.2.2 yamt #if TEMAC_DEBUG > 0 972 1.1.2.2 yamt printf("%s: tx intr 0x%08x\n", device_xname(&sc->sc_dev), stat); 973 1.1.2.2 yamt #endif 974 1.1.2.2 yamt temac_txreap(sc); 975 1.1.2.2 yamt } 976 1.1.2.2 yamt 977 1.1.2.2 yamt static void 978 1.1.2.2 yamt temac_rx_intr(void *arg) 979 1.1.2.2 yamt { 980 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)arg; 981 1.1.2.2 yamt uint32_t stat; 982 1.1.2.2 yamt 983 1.1.2.2 yamt /* XXX: We may need to splnet() here if cdmac(4) changes. */ 984 1.1.2.2 yamt 985 1.1.2.2 yamt if ((stat = cdmac_rx_stat(sc)) & CDMAC_STAT_ERROR) { 986 1.1.2.2 yamt printf("%s: receive DMA is toast (%#08x), halted!\n", 987 1.1.2.2 yamt sc->sc_dev.dv_xname, stat); 988 1.1.2.2 yamt 989 1.1.2.2 yamt /* XXXFreza: how to signal this upstream? */ 990 1.1.2.2 yamt temac_stop(&sc->sc_if, 1); 991 1.1.2.2 yamt sc->sc_dead = 1; 992 1.1.2.2 yamt } 993 1.1.2.2 yamt 994 1.1.2.2 yamt #if TEMAC_DEBUG > 0 995 1.1.2.2 yamt printf("%s: rx intr 0x%08x\n", device_xname(&sc->sc_dev), stat); 996 1.1.2.2 yamt #endif 997 1.1.2.2 yamt temac_rxreap(sc); 998 1.1.2.2 yamt } 999 1.1.2.2 yamt 1000 1.1.2.2 yamt /* 1001 1.1.2.2 yamt * Utils. 1002 1.1.2.2 yamt */ 1003 1.1.2.2 yamt static inline void 1004 1.1.2.2 yamt temac_txcdsync(struct temac_softc *sc, int first, int cnt, int flag) 1005 1.1.2.2 yamt { 1006 1.1.2.2 yamt if ((first + cnt) > TEMAC_NTXDESC) { 1007 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->sc_control_dmap, 1008 1.1.2.2 yamt TEMAC_TXDOFF(first), 1009 1.1.2.2 yamt sizeof(struct cdmac_descr) * (TEMAC_NTXDESC - first), 1010 1.1.2.2 yamt flag); 1011 1.1.2.2 yamt cnt = (first + cnt) % TEMAC_NTXDESC; 1012 1.1.2.2 yamt first = 0; 1013 1.1.2.2 yamt } 1014 1.1.2.2 yamt 1015 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->sc_control_dmap, 1016 1.1.2.2 yamt TEMAC_TXDOFF(first), 1017 1.1.2.2 yamt sizeof(struct cdmac_descr) * cnt, 1018 1.1.2.2 yamt flag); 1019 1.1.2.2 yamt } 1020 1.1.2.2 yamt 1021 1.1.2.2 yamt static inline void 1022 1.1.2.2 yamt temac_rxcdsync(struct temac_softc *sc, int first, int cnt, int flag) 1023 1.1.2.2 yamt { 1024 1.1.2.2 yamt if ((first + cnt) > TEMAC_NRXDESC) { 1025 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->sc_control_dmap, 1026 1.1.2.2 yamt TEMAC_RXDOFF(first), 1027 1.1.2.2 yamt sizeof(struct cdmac_descr) * (TEMAC_NRXDESC - first), 1028 1.1.2.2 yamt flag); 1029 1.1.2.2 yamt cnt = (first + cnt) % TEMAC_NRXDESC; 1030 1.1.2.2 yamt first = 0; 1031 1.1.2.2 yamt } 1032 1.1.2.2 yamt 1033 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->sc_control_dmap, 1034 1.1.2.2 yamt TEMAC_RXDOFF(first), 1035 1.1.2.2 yamt sizeof(struct cdmac_descr) * cnt, 1036 1.1.2.2 yamt flag); 1037 1.1.2.2 yamt } 1038 1.1.2.2 yamt 1039 1.1.2.2 yamt static void 1040 1.1.2.2 yamt temac_txreap(struct temac_softc *sc) 1041 1.1.2.2 yamt { 1042 1.1.2.2 yamt struct temac_txsoft *txs; 1043 1.1.2.2 yamt bus_dmamap_t dmap; 1044 1.1.2.2 yamt int sent = 0; 1045 1.1.2.2 yamt 1046 1.1.2.2 yamt /* 1047 1.1.2.2 yamt * Transmit interrupts happen on the last descriptor of Tx jobs. 1048 1.1.2.2 yamt * Hence, every time we're called (and we assume txintr is our 1049 1.1.2.2 yamt * only caller!), we reap packets upto and including the one 1050 1.1.2.2 yamt * marked as last-in-batch. 1051 1.1.2.2 yamt * 1052 1.1.2.2 yamt * XXX we rely on that we make EXACTLY one batch per intr, no more 1053 1.1.2.2 yamt */ 1054 1.1.2.2 yamt while (sc->sc_txsfree != TEMAC_TXQLEN) { 1055 1.1.2.2 yamt txs = &sc->sc_txsoft[sc->sc_txsreap]; 1056 1.1.2.2 yamt dmap = txs->txs_dmap; 1057 1.1.2.2 yamt 1058 1.1.2.2 yamt sc->sc_txreap = TEMAC_TXINC(sc->sc_txreap, dmap->dm_nsegs); 1059 1.1.2.2 yamt sc->sc_txfree += dmap->dm_nsegs; 1060 1.1.2.2 yamt 1061 1.1.2.2 yamt bus_dmamap_unload(sc->sc_dmat, txs->txs_dmap); 1062 1.1.2.2 yamt m_freem(txs->txs_mbuf); 1063 1.1.2.2 yamt txs->txs_mbuf = NULL; 1064 1.1.2.2 yamt 1065 1.1.2.2 yamt sc->sc_if.if_opackets++; 1066 1.1.2.2 yamt sent = 1; 1067 1.1.2.2 yamt 1068 1.1.2.2 yamt sc->sc_txsreap = TEMAC_TXSNEXT(sc->sc_txsreap); 1069 1.1.2.2 yamt sc->sc_txsfree++; 1070 1.1.2.2 yamt 1071 1.1.2.2 yamt if (txs->txs_last) { 1072 1.1.2.2 yamt txs->txs_last = 0; 1073 1.1.2.2 yamt sc->sc_txbusy = 0; /* channel stopped now */ 1074 1.1.2.2 yamt 1075 1.1.2.2 yamt temac_txkick(sc); 1076 1.1.2.2 yamt break; 1077 1.1.2.2 yamt } 1078 1.1.2.2 yamt } 1079 1.1.2.2 yamt 1080 1.1.2.2 yamt if (sent && (sc->sc_if.if_flags & IFF_OACTIVE)) 1081 1.1.2.2 yamt sc->sc_if.if_flags &= ~IFF_OACTIVE; 1082 1.1.2.2 yamt } 1083 1.1.2.2 yamt 1084 1.1.2.2 yamt static int 1085 1.1.2.2 yamt temac_rxalloc(struct temac_softc *sc, int which, int verbose) 1086 1.1.2.2 yamt { 1087 1.1.2.2 yamt struct temac_rxsoft *rxs; 1088 1.1.2.2 yamt struct mbuf *m; 1089 1.1.2.2 yamt uint32_t stat; 1090 1.1.2.2 yamt int error; 1091 1.1.2.2 yamt 1092 1.1.2.2 yamt rxs = &sc->sc_rxsoft[which]; 1093 1.1.2.2 yamt 1094 1.1.2.2 yamt /* The mbuf itself is not our problem, just clear DMA related stuff. */ 1095 1.1.2.2 yamt if (rxs->rxs_mbuf != NULL) { 1096 1.1.2.2 yamt bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmap); 1097 1.1.2.2 yamt rxs->rxs_mbuf = NULL; 1098 1.1.2.2 yamt } 1099 1.1.2.2 yamt 1100 1.1.2.2 yamt /* 1101 1.1.2.2 yamt * We would like to store mbuf and dmap in application specific 1102 1.1.2.2 yamt * fields of the descriptor, but that doesn't work for Rx. Shame 1103 1.1.2.2 yamt * on Xilinx for this (and for the useless timer architecture). 1104 1.1.2.2 yamt * 1105 1.1.2.2 yamt * Hence each descriptor needs its own soft state. We may want 1106 1.1.2.2 yamt * to merge multiple rxs's into a monster mbuf when we support 1107 1.1.2.2 yamt * jumbo frames though. Also, we use single set of indexing 1108 1.1.2.2 yamt * variables for both sc_rxdescs[] and sc_rxsoft[]. 1109 1.1.2.2 yamt */ 1110 1.1.2.2 yamt MGETHDR(m, M_DONTWAIT, MT_DATA); 1111 1.1.2.2 yamt if (m == NULL) { 1112 1.1.2.2 yamt if (verbose) 1113 1.1.2.2 yamt printf("%s: out of Rx header mbufs\n", 1114 1.1.2.2 yamt sc->sc_dev.dv_xname); 1115 1.1.2.2 yamt return (ENOBUFS); 1116 1.1.2.2 yamt } 1117 1.1.2.2 yamt MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 1118 1.1.2.2 yamt 1119 1.1.2.2 yamt MCLGET(m, M_DONTWAIT); 1120 1.1.2.2 yamt if ((m->m_flags & M_EXT) == 0) { 1121 1.1.2.2 yamt if (verbose) 1122 1.1.2.2 yamt printf("%s: out of Rx cluster mbufs\n", 1123 1.1.2.2 yamt sc->sc_dev.dv_xname); 1124 1.1.2.2 yamt m_freem(m); 1125 1.1.2.2 yamt return (ENOBUFS); 1126 1.1.2.2 yamt } 1127 1.1.2.2 yamt 1128 1.1.2.2 yamt rxs->rxs_mbuf = m; 1129 1.1.2.2 yamt m->m_pkthdr.len = m->m_len = MCLBYTES; 1130 1.1.2.2 yamt 1131 1.1.2.2 yamt /* Make sure the payload after ethernet header is 4-aligned. */ 1132 1.1.2.2 yamt m_adj(m, 2); 1133 1.1.2.2 yamt 1134 1.1.2.2 yamt error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmap, m, 1135 1.1.2.2 yamt BUS_DMA_NOWAIT); 1136 1.1.2.2 yamt if (error) { 1137 1.1.2.2 yamt if (verbose) 1138 1.1.2.2 yamt printf("%s: could not map Rx descriptor %d, " 1139 1.1.2.2 yamt "error = %d\n", sc->sc_dev.dv_xname, which, error); 1140 1.1.2.2 yamt 1141 1.1.2.2 yamt rxs->rxs_mbuf = NULL; 1142 1.1.2.2 yamt m_freem(m); 1143 1.1.2.2 yamt 1144 1.1.2.2 yamt return (error); 1145 1.1.2.2 yamt } 1146 1.1.2.2 yamt 1147 1.1.2.2 yamt stat = \ 1148 1.1.2.2 yamt (TEMAC_ISINTR(which) ? CDMAC_STAT_INTR : 0) | 1149 1.1.2.2 yamt (TEMAC_ISLAST(which) ? CDMAC_STAT_STOP : 0); 1150 1.1.2.2 yamt 1151 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmap, 0, 1152 1.1.2.2 yamt rxs->rxs_dmap->dm_mapsize, BUS_DMASYNC_PREREAD); 1153 1.1.2.2 yamt 1154 1.1.2.2 yamt /* Descriptor post-sync, if needed, left to the caller. */ 1155 1.1.2.2 yamt 1156 1.1.2.2 yamt sc->sc_rxdescs[which].desc_addr = rxs->rxs_dmap->dm_segs[0].ds_addr; 1157 1.1.2.2 yamt sc->sc_rxdescs[which].desc_size = rxs->rxs_dmap->dm_segs[0].ds_len; 1158 1.1.2.2 yamt sc->sc_rxdescs[which].desc_stat = stat; 1159 1.1.2.2 yamt 1160 1.1.2.2 yamt /* Descriptor pre-sync, if needed, left to the caller. */ 1161 1.1.2.2 yamt 1162 1.1.2.2 yamt return (0); 1163 1.1.2.2 yamt } 1164 1.1.2.2 yamt 1165 1.1.2.2 yamt static void 1166 1.1.2.2 yamt temac_rxreap(struct temac_softc *sc) 1167 1.1.2.2 yamt { 1168 1.1.2.2 yamt struct ifnet *ifp = &sc->sc_if; 1169 1.1.2.2 yamt uint32_t stat, rxstat, rxsize; 1170 1.1.2.2 yamt struct mbuf *m; 1171 1.1.2.2 yamt int nseg, head, tail; 1172 1.1.2.2 yamt 1173 1.1.2.2 yamt head = sc->sc_rxreap; 1174 1.1.2.2 yamt tail = 0; /* gcc */ 1175 1.1.2.2 yamt nseg = 0; 1176 1.1.2.2 yamt 1177 1.1.2.2 yamt /* 1178 1.1.2.2 yamt * Collect finished entries on the Rx list, kick DMA if we hit 1179 1.1.2.2 yamt * the end. DMA will always stop on the last descriptor in chain, 1180 1.1.2.2 yamt * so it will never hit a reap-in-progress descriptor. 1181 1.1.2.2 yamt */ 1182 1.1.2.2 yamt while (1) { 1183 1.1.2.2 yamt /* Maybe we previously failed to refresh this one? */ 1184 1.1.2.2 yamt if (sc->sc_rxsoft[sc->sc_rxreap].rxs_mbuf == NULL) { 1185 1.1.2.2 yamt if (temac_rxalloc(sc, sc->sc_rxreap, 0) != 0) 1186 1.1.2.2 yamt break; 1187 1.1.2.2 yamt 1188 1.1.2.2 yamt sc->sc_rxreap = TEMAC_RXNEXT(sc->sc_rxreap); 1189 1.1.2.2 yamt continue; 1190 1.1.2.2 yamt } 1191 1.1.2.2 yamt temac_rxcdsync(sc, sc->sc_rxreap, 1, 1192 1.1.2.2 yamt BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1193 1.1.2.2 yamt 1194 1.1.2.2 yamt stat = sc->sc_rxdescs[sc->sc_rxreap].desc_stat; 1195 1.1.2.2 yamt m = NULL; 1196 1.1.2.2 yamt 1197 1.1.2.2 yamt if ((stat & CDMAC_STAT_DONE) == 0) 1198 1.1.2.2 yamt break; 1199 1.1.2.2 yamt 1200 1.1.2.2 yamt /* Count any decriptor we've collected, regardless of status. */ 1201 1.1.2.2 yamt nseg ++; 1202 1.1.2.2 yamt 1203 1.1.2.2 yamt /* XXXFreza: This won't work for jumbo frames. */ 1204 1.1.2.2 yamt 1205 1.1.2.2 yamt if ((stat & (CDMAC_STAT_EOP | CDMAC_STAT_SOP)) != 1206 1.1.2.2 yamt (CDMAC_STAT_EOP | CDMAC_STAT_SOP)) { 1207 1.1.2.2 yamt printf("%s: Rx packet doesn't fit in " 1208 1.1.2.2 yamt "one descriptor, stat = %#08x\n", 1209 1.1.2.2 yamt sc->sc_dev.dv_xname, stat); 1210 1.1.2.2 yamt goto badframe; 1211 1.1.2.2 yamt } 1212 1.1.2.2 yamt 1213 1.1.2.2 yamt /* Dissect TEMAC footer if this is end of packet. */ 1214 1.1.2.2 yamt rxstat = sc->sc_rxdescs[sc->sc_rxreap].desc_rxstat; 1215 1.1.2.2 yamt rxsize = sc->sc_rxdescs[sc->sc_rxreap].desc_rxsize & 1216 1.1.2.2 yamt RXSIZE_MASK; 1217 1.1.2.2 yamt 1218 1.1.2.2 yamt if ((rxstat & RXSTAT_GOOD) == 0 || 1219 1.1.2.2 yamt (rxstat & RXSTAT_SICK) != 0) { 1220 1.1.2.2 yamt printf("%s: corrupt Rx packet, rxstat = %#08x\n", 1221 1.1.2.2 yamt sc->sc_dev.dv_xname, rxstat); 1222 1.1.2.2 yamt goto badframe; 1223 1.1.2.2 yamt } 1224 1.1.2.2 yamt 1225 1.1.2.2 yamt /* We are now bound to succeed. */ 1226 1.1.2.2 yamt bus_dmamap_sync(sc->sc_dmat, 1227 1.1.2.2 yamt sc->sc_rxsoft[sc->sc_rxreap].rxs_dmap, 0, 1228 1.1.2.2 yamt sc->sc_rxsoft[sc->sc_rxreap].rxs_dmap->dm_mapsize, 1229 1.1.2.2 yamt BUS_DMASYNC_POSTREAD); 1230 1.1.2.2 yamt 1231 1.1.2.2 yamt m = sc->sc_rxsoft[sc->sc_rxreap].rxs_mbuf; 1232 1.1.2.2 yamt m->m_pkthdr.rcvif = ifp; 1233 1.1.2.2 yamt m->m_pkthdr.len = m->m_len = rxsize; 1234 1.1.2.2 yamt 1235 1.1.2.2 yamt badframe: 1236 1.1.2.2 yamt /* Get ready for more work. */ 1237 1.1.2.2 yamt tail = sc->sc_rxreap; 1238 1.1.2.2 yamt sc->sc_rxreap = TEMAC_RXNEXT(sc->sc_rxreap); 1239 1.1.2.2 yamt 1240 1.1.2.2 yamt /* On failures we reuse the descriptor and go ahead. */ 1241 1.1.2.2 yamt if (m == NULL) { 1242 1.1.2.2 yamt sc->sc_rxdescs[tail].desc_stat = 1243 1.1.2.2 yamt (TEMAC_ISINTR(tail) ? CDMAC_STAT_INTR : 0) | 1244 1.1.2.2 yamt (TEMAC_ISLAST(tail) ? CDMAC_STAT_STOP : 0); 1245 1.1.2.2 yamt 1246 1.1.2.2 yamt ifp->if_ierrors++; 1247 1.1.2.2 yamt continue; 1248 1.1.2.2 yamt } 1249 1.1.2.2 yamt 1250 1.1.2.2 yamt #if NBPFILTER > 0 1251 1.1.2.2 yamt if (ifp->if_bpf != NULL) 1252 1.1.2.2 yamt bpf_mtap(ifp->if_bpf, m); 1253 1.1.2.2 yamt #endif 1254 1.1.2.2 yamt 1255 1.1.2.2 yamt ifp->if_ipackets++; 1256 1.1.2.2 yamt (ifp->if_input)(ifp, m); 1257 1.1.2.2 yamt 1258 1.1.2.2 yamt /* Refresh descriptor, bail out if we're out of buffers. */ 1259 1.1.2.2 yamt if (temac_rxalloc(sc, tail, 1) != 0) { 1260 1.1.2.2 yamt sc->sc_rxreap = TEMAC_RXINC(sc->sc_rxreap, -1); 1261 1.1.2.2 yamt printf("%s: Rx give up for now\n", sc->sc_dev.dv_xname); 1262 1.1.2.2 yamt break; 1263 1.1.2.2 yamt } 1264 1.1.2.2 yamt } 1265 1.1.2.2 yamt 1266 1.1.2.2 yamt /* We may now have a contiguous ready-to-go chunk of descriptors. */ 1267 1.1.2.2 yamt if (nseg > 0) { 1268 1.1.2.2 yamt #if TEMAC_RXDEBUG > 0 1269 1.1.2.2 yamt printf("%s: rxreap: rxreap %03d -> %03d, nseg %03d\n", 1270 1.1.2.2 yamt sc->sc_dev.dv_xname, head, sc->sc_rxreap, nseg); 1271 1.1.2.2 yamt #endif 1272 1.1.2.2 yamt temac_rxcdsync(sc, head, nseg, 1273 1.1.2.2 yamt BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1274 1.1.2.2 yamt 1275 1.1.2.2 yamt if (TEMAC_ISLAST(tail)) 1276 1.1.2.2 yamt cdmac_rx_start(sc, sc->sc_cdaddr + TEMAC_RXDOFF(0)); 1277 1.1.2.2 yamt } 1278 1.1.2.2 yamt 1279 1.1.2.2 yamt /* Ensure maximum Rx latency is kept under control. */ 1280 1.1.2.2 yamt callout_schedule(&sc->sc_rx_timo, hz / TEMAC_RXTIMO_HZ); 1281 1.1.2.2 yamt } 1282 1.1.2.2 yamt 1283 1.1.2.2 yamt static void 1284 1.1.2.2 yamt temac_rxtimo(void *arg) 1285 1.1.2.2 yamt { 1286 1.1.2.2 yamt struct temac_softc *sc = (struct temac_softc *)arg; 1287 1.1.2.2 yamt int s; 1288 1.1.2.2 yamt 1289 1.1.2.2 yamt /* We run TEMAC_RXTIMO_HZ times/sec to ensure Rx doesn't stall. */ 1290 1.1.2.2 yamt s = splnet(); 1291 1.1.2.2 yamt temac_rxreap(sc); 1292 1.1.2.2 yamt splx(s); 1293 1.1.2.2 yamt } 1294 1.1.2.2 yamt 1295 1.1.2.2 yamt static void 1296 1.1.2.2 yamt temac_reset(struct temac_softc *sc) 1297 1.1.2.2 yamt { 1298 1.1.2.2 yamt uint32_t rcr, tcr; 1299 1.1.2.2 yamt 1300 1.1.2.2 yamt /* Kill CDMAC channels. */ 1301 1.1.2.2 yamt cdmac_tx_reset(sc); 1302 1.1.2.2 yamt cdmac_rx_reset(sc); 1303 1.1.2.2 yamt 1304 1.1.2.2 yamt /* Disable receiver. */ 1305 1.1.2.2 yamt rcr = gmi_read_4(TEMAC_GMI_RXCF1) & ~GMI_RX_ENABLE; 1306 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_RXCF1, rcr); 1307 1.1.2.2 yamt 1308 1.1.2.2 yamt /* Disable transmitter. */ 1309 1.1.2.2 yamt tcr = gmi_read_4(TEMAC_GMI_TXCF) & ~GMI_TX_ENABLE; 1310 1.1.2.2 yamt gmi_write_4(TEMAC_GMI_TXCF, tcr); 1311 1.1.2.2 yamt } 1312 1.1.2.2 yamt 1313 1.1.2.2 yamt static void 1314 1.1.2.2 yamt temac_rxdrain(struct temac_softc *sc) 1315 1.1.2.2 yamt { 1316 1.1.2.2 yamt struct temac_rxsoft *rxs; 1317 1.1.2.2 yamt int i; 1318 1.1.2.2 yamt 1319 1.1.2.2 yamt for (i = 0; i < TEMAC_NRXDESC; i++) { 1320 1.1.2.2 yamt rxs = &sc->sc_rxsoft[i]; 1321 1.1.2.2 yamt 1322 1.1.2.2 yamt if (rxs->rxs_mbuf != NULL) { 1323 1.1.2.2 yamt bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmap); 1324 1.1.2.2 yamt m_freem(rxs->rxs_mbuf); 1325 1.1.2.2 yamt rxs->rxs_mbuf = NULL; 1326 1.1.2.2 yamt } 1327 1.1.2.2 yamt } 1328 1.1.2.2 yamt 1329 1.1.2.2 yamt sc->sc_rx_drained = 1; 1330 1.1.2.2 yamt } 1331 1.1.2.2 yamt 1332 1.1.2.2 yamt static void 1333 1.1.2.2 yamt temac_txkick(struct temac_softc *sc) 1334 1.1.2.2 yamt { 1335 1.1.2.2 yamt if (sc->sc_txsoft[sc->sc_txsreap].txs_mbuf != NULL && 1336 1.1.2.2 yamt sc->sc_txbusy == 0) { 1337 1.1.2.2 yamt cdmac_tx_start(sc, sc->sc_cdaddr + TEMAC_TXDOFF(sc->sc_txreap)); 1338 1.1.2.2 yamt sc->sc_txbusy = 1; 1339 1.1.2.2 yamt } 1340 1.1.2.2 yamt } 1341
Indexes created Tue Oct 28 07:09:57 GMT 2025