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      1  1.1  freza /* 	$NetBSD: pstworeg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
      2  1.1  freza 
      3  1.1  freza /*
      4  1.1  freza  * Copyright (c) 2006 Jachym Holecek
      5  1.1  freza  * All rights reserved.
      6  1.1  freza  *
      7  1.1  freza  * Written for DFC Design, s.r.o.
      8  1.1  freza  *
      9  1.1  freza  * Redistribution and use in source and binary forms, with or without
     10  1.1  freza  * modification, are permitted provided that the following conditions
     11  1.1  freza  * are met:
     12  1.1  freza  *
     13  1.1  freza  * 1. Redistributions of source code must retain the above copyright
     14  1.1  freza  *    notice, this list of conditions and the following disclaimer.
     15  1.1  freza  *
     16  1.1  freza  * 2. Redistributions in binary form must reproduce the above copyright
     17  1.1  freza  *    notice, this list of conditions and the following disclaimer in the
     18  1.1  freza  *    documentation and/or other materials provided with the distribution.
     19  1.1  freza  *
     20  1.1  freza  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  1.1  freza  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  1.1  freza  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  1.1  freza  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  1.1  freza  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  1.1  freza  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  1.1  freza  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  1.1  freza  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  1.1  freza  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  1.1  freza  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  1.1  freza  */
     31  1.1  freza 
     32  1.1  freza #ifndef _VIRTEX_DEV_PSTWOREG_H_
     33  1.1  freza #define _VIRTEX_DEV_PSTWOREG_H_
     34  1.1  freza 
     35  1.1  freza /*
     36  1.1  freza  * PeeCee style PS2 serdes core. Doesn't save us much work, really.
     37  1.1  freza  * Each instance handles one PS2 port, the user has to know if it's
     38  1.1  freza  * mouse or keyboard.
     39  1.1  freza  */
     40  1.1  freza 
     41  1.1  freza #define PSTWO_SIZE 		0x1c
     42  1.1  freza 
     43  1.1  freza /* Deal with inconsistent notation in Xilinx datasheets. Whee. */
     44  1.1  freza #define PSTWO_BIT(n) 		(0x80000000U >> (n))
     45  1.1  freza 
     46  1.1  freza #define PSTWO_CTRL 		0x0000 		/* wo */
     47  1.1  freza #define CTRL_RESET 		PSTWO_BIT(7) 	/* Component reset when set */
     48  1.1  freza 
     49  1.1  freza #define PSTWO_STAT 		0x0004 		/* ro */
     50  1.1  freza #define STAT_TX_BUSY 		PSTWO_BIT(6) 	/* Transmitting byte */
     51  1.1  freza #define STAT_RX_DONE 		PSTWO_BIT(7) 	/* Received a byte */
     52  1.1  freza 
     53  1.1  freza #define PSTWO_RX_DATA 		0x0008 		/* ro */
     54  1.1  freza #define PSTWO_TX_DATA 		0x000c 		/* wo */
     55  1.1  freza #define DATA_RECV(x) 		((x) >> 24) 	/* RX */
     56  1.1  freza #define DATA_SEND(x) 		((x) << 24) 	/* TX */
     57  1.1  freza 
     58  1.1  freza #define PSTWO_INTR_STAT 	0x0010 		/* ro */
     59  1.1  freza #define PSTWO_INTR_ACK 		0x0014 		/* wo (reads as STAT) */
     60  1.1  freza #define PSTWO_INTR_MSET 	0x0018 		/* wo (reads as MASK) */
     61  1.1  freza #define PSTWO_INTR_MCLR 	0x001c 		/* wo (reads as MASK) */
     62  1.1  freza #define PSTWO_INTR_MASK 	PSTWO_INTR_MSET
     63  1.1  freza 
     64  1.1  freza /* PSTWO_INTR_ bits */
     65  1.1  freza #define INTR_RX_FULL 		PSTWO_BIT(2) 	/* Received byte */
     66  1.1  freza #define INTR_RX_ERR 		PSTWO_BIT(3) 	/* Received corrupt packet */
     67  1.1  freza #define INTR_RX_OVER 		PSTWO_BIT(4) 	/* RX overrun */
     68  1.1  freza #define INTR_TX_DONE 		PSTWO_BIT(5) 	/* TX packet acknowledged */
     69  1.1  freza #define INTR_TX_SENT 		PSTWO_BIT(6) 	/* TX packet sent */
     70  1.1  freza #define INTR_TX_TIMO 		PSTWO_BIT(7) 	/* Clock lost while TX */
     71  1.1  freza #define INTR_ANY 		(INTR_RX_FULL | INTR_RX_ERR | INTR_RX_OVER | \
     72  1.1  freza 				 INTR_TX_DONE | INTR_TX_SENT | INTR_TX_TIMO)
     73  1.1  freza 
     74  1.1  freza #endif /*_VIRTEX_DEV_PSTWOREG_H_*/
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