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      1  1.1  freza /* 	$NetBSD: xlcomreg.h,v 1.1 2006/12/02 22:18:47 freza Exp $ */
      2  1.1  freza 
      3  1.1  freza /*
      4  1.1  freza  * Copyright (c) 2006 Jachym Holecek
      5  1.1  freza  * All rights reserved.
      6  1.1  freza  *
      7  1.1  freza  * Written for DFC Design, s.r.o.
      8  1.1  freza  *
      9  1.1  freza  * Redistribution and use in source and binary forms, with or without
     10  1.1  freza  * modification, are permitted provided that the following conditions
     11  1.1  freza  * are met:
     12  1.1  freza  *
     13  1.1  freza  * 1. Redistributions of source code must retain the above copyright
     14  1.1  freza  *    notice, this list of conditions and the following disclaimer.
     15  1.1  freza  *
     16  1.1  freza  * 2. Redistributions in binary form must reproduce the above copyright
     17  1.1  freza  *    notice, this list of conditions and the following disclaimer in the
     18  1.1  freza  *    documentation and/or other materials provided with the distribution.
     19  1.1  freza  *
     20  1.1  freza  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  1.1  freza  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  1.1  freza  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  1.1  freza  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  1.1  freza  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  1.1  freza  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  1.1  freza  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  1.1  freza  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  1.1  freza  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  1.1  freza  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  1.1  freza  */
     31  1.1  freza 
     32  1.1  freza #ifndef _VIRTEX_DEV_XLCOMREG_H_
     33  1.1  freza #define _VIRTEX_DEV_XLCOMREG_H_
     34  1.1  freza 
     35  1.1  freza /*
     36  1.1  freza  * Xilinx UART Lite (opb_uartlite_0 in EDK) registers. Note that all
     37  1.1  freza  * line parameter are hardcoded at synthesis time. There is no hardware
     38  1.1  freza  * flow control, just RX and TX signals.
     39  1.1  freza  */
     40  1.1  freza 
     41  1.1  freza #define XLCOM_SIZE 		0x0c
     42  1.1  freza 
     43  1.1  freza /* 16B FIFOs */
     44  1.1  freza #define XLCOM_RX_FIFO 		0x0000
     45  1.1  freza #define XLCOM_TX_FIFO 		0x0004
     46  1.1  freza 
     47  1.1  freza #define XLCOM_STAT 		0x0008 		/* ro */
     48  1.1  freza #define STAT_PARITY_ERR 	0x80
     49  1.1  freza #define STAT_FRAME_ERR 		0x40
     50  1.1  freza #define STAT_OVERRUN_ERR 	0x20
     51  1.1  freza #define STAT_INTR_EN 		0x10 		/* Interrupt enabled */
     52  1.1  freza #define STAT_TX_FULL 		0x08
     53  1.1  freza #define STAT_TX_EMPTY 		0x04
     54  1.1  freza #define STAT_RX_FULL 		0x02
     55  1.1  freza #define STAT_RX_DATA 	 	0x01 		/* RX FIFO has valid data */
     56  1.1  freza 
     57  1.1  freza #define XLCOM_CNTL 		0x000c 		/* wo */
     58  1.1  freza #define CNTL_INTR_EN 		0x10
     59  1.1  freza #define CNTL_RX_CLEAR 		0x02 		/* Reset/clear FIFOs */
     60  1.1  freza #define CNTL_TX_CLEAR 		0x01
     61  1.1  freza 
     62  1.1  freza #endif /*_VIRTEX_DEV_XLCOMREG_H_*/
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