virtex_start.S revision 1.1
1 /* $NetBSD: virtex_start.S,v 1.1 2006/12/02 22:18:47 freza Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Jachym Holecek 5 * All rights reserved. 6 * 7 * Written for DFC Design, s.r.o. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file is based on startup code of Walnut and Explora boards. 34 */ 35 36 #define _NOREGNAMES 37 38 #include "opt_ddb.h" 39 #include "opt_ipkdb.h" 40 #include "opt_lockdebug.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_ppcarch.h" 43 #include "opt_ppcparam.h" 44 #include "opt_virtex.h" 45 #include "assym.h" 46 #include "ksyms.h" 47 48 #include <sys/syscall.h> 49 50 #include <machine/param.h> 51 #include <machine/psl.h> 52 #include <machine/trap.h> 53 #include <machine/asm.h> 54 55 #include <powerpc/spr.h> 56 #include <powerpc/ibm4xx/dcr405gp.h> 57 #include <powerpc/ibm4xx/pmap.h> 58 59 60 /* N megabytes. */ 61 #define MB(n) ((n)*1024*1024) 62 63 /* Set bit (beginning with MSB) for each 128MB of RAM. */ 64 #define PHYSMEM_REGIONS_MASK ~((1 << (32 - MB(PHYSMEM)/MB(128))) - 1) 65 66 67 /* Initialized by INIT_CPUINFO(), used by machdep.c */ 68 GLOBAL(proc0paddr) 69 .long 0 /* proc0 p_addr */ 70 71 /* For kvm_mkdb, supposed to mark the start of kernel text. */ 72 .text 73 .globl _C_LABEL(kernel_text) 74 _C_LABEL(kernel_text): 75 76 /* Startup entry. This must be the first thing in the text segment! */ 77 .text 78 .globl __start 79 __start: 80 /* Disable MMU/exceptions */ 81 lis %r0, 0 82 mtmsr %r0 83 84 /* Disable timers */ 85 lis %r0, 0 86 mttcr %r0 87 88 sync 89 isync 90 91 /* Disable caches */ 92 mtdccr %r0 93 mticcr %r0 94 sync 95 isync 96 97 /* Invalidate I$, operands ignored on the 405 */ 98 li %r0,0 /* just in case... */ 99 iccci %r0,%r0 100 101 /* Invalidate D$, hardcoded for 16KB size, 32B line */ 102 li %r7,256 /* # of congruence classes */ 103 mtctr %r7 104 li %r6,0 105 1: 106 dccci %r0,%r6 /* invalidates both ways */ 107 addi %r6,%r6,32 108 bdnz 1b 109 110 /* 111 * Errata 213: Incorrect data may be flushed from the data cache. 112 * Cores: PPC405D5X1, PPC405D5X2 113 * Workaround: #1, CCR0 modification sequence #2 114 * Note: Meaning of bits we need to set is undocumented. 115 */ 116 sync 117 mfccr0 %r0 118 oris %r0,%r0,0x50000000@h 119 mtccr0 %r0 120 isync 121 122 /* 123 * Errata 58: Load string instructions may write incorrect 124 * data into the last GPR targeted in operation. 125 * Cores: PPC405GP 126 * Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 127 */ 128 mtdcr DCR_OCM0_DSCNTL,%r0 /* Disable Data access to OCM */ 129 130 #if 0 131 /* Allow cacheing for whole RAM. */ 132 lis %r0,PHYSMEM_REGIONS_MASK@ha 133 ori %r0,%r0,PHYSMEM_REGIONS_MASK@l 134 #else 135 #ifndef PPC_4XX_NOCACHE 136 /* Allow cacheing for only the first 1GB of RAM */ 137 lis %r0,0xff00 138 mtdccr %r0 139 mticcr %r0 140 #endif /* PPC_4XX_NOCACHE */ 141 #endif 142 143 /* Invalidate all TLB entries */ 144 tlbia 145 sync 146 isync 147 148 /* Set kernel MMU context, we'll enable MMU in initppc() */ 149 li %r0,KERNEL_PID 150 mtpid %r0 151 sync 152 isync 153 154 /* Setup endkernel argument for initppc() and INIT_CPUINFO */ 155 lis %r4,_C_LABEL(end)@h 156 ori %r4,%r4,_C_LABEL(end)@l 157 158 /* Clear .bss segment */ 159 lis %r7,_C_LABEL(edata)-4@h 160 ori %r7,%r7,_C_LABEL(edata)-4@l 161 li %r3,0 162 2: stwu %r3,4(%r7) 163 cmpw %r7,%r4 164 bne+ 2b 165 166 #if NKSYMS || defined(DDB) || defined(LKM) 167 /* We don't have a symbol table, so set startsym = endsym = end */ 168 lis %r7,_C_LABEL(startsym)@ha 169 ori %r7,%r7,_C_LABEL(startsym)@l 170 stw %r4,0(%r7) 171 lis %r7,_C_LABEL(endsym)@ha 172 ori %r7,%r7,_C_LABEL(endsym)@l 173 stw %r4,0(%r7) 174 #endif 175 176 /* INIT_CPUINFO will 'addi', so clean up. */ 177 lis %r1,0 178 179 INIT_CPUINFO(4,1,9,0) 180 181 /* startkernel argument for initppc */ 182 lis %r3,__start@h 183 addi %r3,%r3,__start@l 184 185 bl _C_LABEL(initppc) 186 bl _C_LABEL(main) 187 188 loop: /* UNREACHED */ 189 b loop 190 191 #include <powerpc/ibm4xx/4xx_locore.S> 192
Indexes created Thu Oct 02 07:10:07 GMT 2025