virtex_start.S revision 1.3
1 /* $NetBSD: virtex_start.S,v 1.3 2009/02/13 22:41:01 apb Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Jachym Holecek 5 * All rights reserved. 6 * 7 * Written for DFC Design, s.r.o. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This file is based on startup code of Walnut and Explora boards. 34 */ 35 36 #define _NOREGNAMES 37 38 #include "opt_ddb.h" 39 #include "opt_ipkdb.h" 40 #include "opt_lockdebug.h" 41 #include "opt_modular.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_ppcarch.h" 44 #include "opt_ppcparam.h" 45 #include "opt_virtex.h" 46 #include "assym.h" 47 #include "ksyms.h" 48 49 #include <sys/syscall.h> 50 51 #include <machine/param.h> 52 #include <machine/psl.h> 53 #include <machine/trap.h> 54 #include <machine/asm.h> 55 56 #include <powerpc/spr.h> 57 #include <powerpc/ibm4xx/dcr405gp.h> 58 #include <powerpc/ibm4xx/pmap.h> 59 60 61 /* N megabytes. */ 62 #define MB(n) ((n)*1024*1024) 63 64 /* Set bit (beginning with MSB) for each 128MB of RAM. */ 65 #define PHYSMEM_REGIONS_MASK ~((1 << (32 - MB(PHYSMEM)/MB(128))) - 1) 66 67 68 /* Initialized by INIT_CPUINFO(), used by machdep.c */ 69 GLOBAL(proc0paddr) 70 .long 0 /* proc0 p_addr */ 71 72 /* For kvm_mkdb, supposed to mark the start of kernel text. */ 73 .text 74 .globl _C_LABEL(kernel_text) 75 _C_LABEL(kernel_text): 76 77 /* Startup entry. This must be the first thing in the text segment! */ 78 .text 79 .globl __start 80 __start: 81 /* Disable MMU/exceptions */ 82 lis %r0, 0 83 mtmsr %r0 84 85 /* Disable timers */ 86 lis %r0, 0 87 mttcr %r0 88 89 sync 90 isync 91 92 /* Disable caches */ 93 mtdccr %r0 94 mticcr %r0 95 sync 96 isync 97 98 /* Invalidate I$, operands ignored on the 405 */ 99 li %r0,0 /* just in case... */ 100 iccci %r0,%r0 101 102 /* Invalidate D$, hardcoded for 16KB size, 32B line */ 103 li %r7,256 /* # of congruence classes */ 104 mtctr %r7 105 li %r6,0 106 1: 107 dccci %r0,%r6 /* invalidates both ways */ 108 addi %r6,%r6,32 109 bdnz 1b 110 111 /* 112 * Errata 213: Incorrect data may be flushed from the data cache. 113 * Cores: PPC405D5X1, PPC405D5X2 114 * Workaround: #1, CCR0 modification sequence #2 115 * Note: Meaning of bits we need to set is undocumented. 116 */ 117 sync 118 mfccr0 %r0 119 oris %r0,%r0,0x50000000@h 120 mtccr0 %r0 121 isync 122 123 /* 124 * Errata 58: Load string instructions may write incorrect 125 * data into the last GPR targeted in operation. 126 * Cores: PPC405GP 127 * Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 128 */ 129 mtdcr DCR_OCM0_DSCNTL,%r0 /* Disable Data access to OCM */ 130 131 #if 0 132 /* Allow cacheing for whole RAM. */ 133 lis %r0,PHYSMEM_REGIONS_MASK@ha 134 ori %r0,%r0,PHYSMEM_REGIONS_MASK@l 135 #else 136 #ifndef PPC_4XX_NOCACHE 137 /* Allow cacheing for only the first 1GB of RAM */ 138 lis %r0,0xff00 139 mtdccr %r0 140 mticcr %r0 141 #endif /* PPC_4XX_NOCACHE */ 142 #endif 143 144 /* Invalidate all TLB entries */ 145 tlbia 146 sync 147 isync 148 149 /* Set kernel MMU context, we'll enable MMU in initppc() */ 150 li %r0,KERNEL_PID 151 mtpid %r0 152 sync 153 isync 154 155 /* Setup endkernel argument for initppc() and INIT_CPUINFO */ 156 lis %r4,_C_LABEL(end)@h 157 ori %r4,%r4,_C_LABEL(end)@l 158 159 /* Clear .bss segment */ 160 lis %r7,_C_LABEL(edata)-4@h 161 ori %r7,%r7,_C_LABEL(edata)-4@l 162 li %r3,0 163 2: stwu %r3,4(%r7) 164 cmpw %r7,%r4 165 bne+ 2b 166 167 #if NKSYMS || defined(DDB) || defined(MODULAR) 168 /* We don't have a symbol table, so set startsym = endsym = end */ 169 lis %r7,_C_LABEL(startsym)@ha 170 ori %r7,%r7,_C_LABEL(startsym)@l 171 stw %r4,0(%r7) 172 lis %r7,_C_LABEL(endsym)@ha 173 ori %r7,%r7,_C_LABEL(endsym)@l 174 stw %r4,0(%r7) 175 #endif 176 177 /* INIT_CPUINFO will 'addi', so clean up. */ 178 lis %r1,0 179 180 INIT_CPUINFO(4,1,9,0) 181 182 /* startkernel argument for initppc */ 183 lis %r3,__start@h 184 addi %r3,%r3,__start@l 185 186 bl _C_LABEL(initppc) 187 bl _C_LABEL(main) 188 189 loop: /* UNREACHED */ 190 b loop 191 192 #include <powerpc/ibm4xx/4xx_locore.S> 193
Indexes created Wed Oct 01 19:09:53 GMT 2025