rtcsram.c revision 1.1.2.2
1 /* $NetBSD: rtcsram.c,v 1.1.2.2 2024/02/03 11:47:04 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rtcsram.c,v 1.1.2.2 2024/02/03 11:47:04 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <dev/clock_subr.h> 37 38 #include <lib/libkern/libkern.h> 39 40 #include "exi.h" 41 42 #define WII_RTCSRAM_ID 0xfffff308 43 44 #define RTC_BASE 0x20000000 45 #define SRAM_BASE 0x20000100 46 47 #define WRITE_OFFSET 0x80000000 48 49 struct rtcsram_sram { 50 uint16_t checksum[2]; 51 uint16_t ead[2]; 52 int32_t counter_bias; 53 int8_t display_offset_h; 54 uint8_t ntd; 55 uint8_t language; 56 uint8_t flags; 57 uint16_t flash_id[12]; 58 uint32_t wireless_keyboard_id; 59 uint32_t wireless_pad_id[2]; 60 uint8_t last_dvd_errorcode; 61 uint8_t padding1; 62 uint16_t flash_id_checksum[2]; 63 uint16_t padding2; 64 } __aligned(32); 65 CTASSERT(sizeof(struct rtcsram_sram) == 64); 66 67 struct rtcsram_softc { 68 struct todr_chip_handle sc_todr; 69 70 uint8_t sc_chan; 71 uint8_t sc_device; 72 73 struct rtcsram_sram sc_sram; 74 }; 75 76 static int rtcsram_match(device_t, cfdata_t, void *); 77 static void rtcsram_attach(device_t, device_t, void *); 78 79 static uint32_t rtcsram_read_4(struct rtcsram_softc *, uint32_t); 80 static void rtcsram_write_4(struct rtcsram_softc *, uint32_t, uint32_t); 81 static void rtcsram_read_buf(struct rtcsram_softc *, uint32_t, void *, 82 size_t); 83 84 static int rtcsram_gettime(todr_chip_handle_t, struct timeval *); 85 static int rtcsram_settime(todr_chip_handle_t, struct timeval *); 86 87 CFATTACH_DECL_NEW(rtcsram, sizeof(struct rtcsram_softc), 88 rtcsram_match, rtcsram_attach, NULL, NULL); 89 90 static int 91 rtcsram_match(device_t parent, cfdata_t cf, void *aux) 92 { 93 struct exi_attach_args * const eaa = aux; 94 95 return eaa->eaa_id == WII_RTCSRAM_ID; 96 } 97 98 static void 99 rtcsram_attach(device_t parent, device_t self, void *aux) 100 { 101 struct rtcsram_softc * const sc = device_private(self); 102 struct exi_attach_args * const eaa = aux; 103 104 aprint_naive("\n"); 105 aprint_normal(": RTC/SRAM\n"); 106 107 sc->sc_chan = eaa->eaa_chan; 108 sc->sc_device = eaa->eaa_device; 109 110 /* Read RTC counter bias from SRAM. */ 111 rtcsram_read_buf(sc, SRAM_BASE, &sc->sc_sram, sizeof(sc->sc_sram)); 112 aprint_debug_dev(self, "counter bias %d\n", sc->sc_sram.counter_bias); 113 hexdump(aprint_debug, device_xname(self), &sc->sc_sram, 114 sizeof(sc->sc_sram)); 115 116 sc->sc_todr.cookie = sc; 117 sc->sc_todr.todr_gettime = rtcsram_gettime; 118 sc->sc_todr.todr_settime = rtcsram_settime; 119 todr_attach(&sc->sc_todr); 120 } 121 122 static uint32_t 123 rtcsram_read_4(struct rtcsram_softc *sc, uint32_t offset) 124 { 125 uint32_t val; 126 127 exi_select(sc->sc_chan, sc->sc_device); 128 exi_send_imm(sc->sc_chan, sc->sc_device, &offset, sizeof(offset)); 129 exi_recv_imm(sc->sc_chan, sc->sc_device, &val, sizeof(val)); 130 exi_unselect(sc->sc_chan); 131 132 return val; 133 } 134 135 static void 136 rtcsram_write_4(struct rtcsram_softc *sc, uint32_t offset, uint32_t val) 137 { 138 offset |= WRITE_OFFSET; 139 140 exi_select(sc->sc_chan, sc->sc_device); 141 exi_send_imm(sc->sc_chan, sc->sc_device, &offset, sizeof(offset)); 142 exi_send_imm(sc->sc_chan, sc->sc_device, &val, sizeof(val)); 143 exi_unselect(sc->sc_chan); 144 } 145 146 static void 147 rtcsram_read_buf(struct rtcsram_softc *sc, uint32_t offset, void *data, 148 size_t datalen) 149 { 150 exi_select(sc->sc_chan, sc->sc_device); 151 exi_send_imm(sc->sc_chan, sc->sc_device, &offset, sizeof(offset)); 152 exi_recv_dma(sc->sc_chan, sc->sc_device, data, datalen); 153 exi_unselect(sc->sc_chan); 154 } 155 156 static int 157 rtcsram_gettime(todr_chip_handle_t ch, struct timeval *tv) 158 { 159 struct rtcsram_softc * const sc = ch->cookie; 160 uint32_t val; 161 162 val = rtcsram_read_4(sc, RTC_BASE); 163 tv->tv_sec = (uint64_t)val + sc->sc_sram.counter_bias; 164 tv->tv_usec = 0; 165 166 return 0; 167 } 168 169 static int 170 rtcsram_settime(todr_chip_handle_t ch, struct timeval *tv) 171 { 172 struct rtcsram_softc * const sc = ch->cookie; 173 174 rtcsram_write_4(sc, RTC_BASE, tv->tv_sec - sc->sc_sram.counter_bias); 175 176 return 0; 177 } 178
Indexes created Fri Oct 03 02:09:57 GMT 2025