locore.S revision 1.1
1 /* $NetBSD: locore.S,v 1.1 2002/02/24 18:19:41 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1993, 1994, 1995, 1997 5 * Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)locore.s 7.3 (Berkeley) 5/13/91 41 */ 42 43 #include "opt_ddb.h" 44 #include "opt_lockdebug.h" 45 #include "opt_memsize.h" 46 47 #include "assym.h" 48 49 #include <sys/errno.h> 50 #include <sys/syscall.h> 51 52 #include <sh3/locore.h> 53 #include <machine/asm.h> 54 #include <machine/cputypes.h> 55 #include <machine/param.h> 56 #include <machine/pte.h> 57 #include <machine/trap.h> 58 59 #define INIT_STACK IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000 60 61 #ifdef SH4 62 #define SHREG_BBRA 0xff200008 63 #define SHREG_CCR 0xff00001c 64 #define SHREG_EXPEVT 0xff000024 65 #define SHREG_INTEVT 0xff000028 66 #define SHREG_MMUCR 0xff000010 67 #define SHREG_TTB 0xff000008 68 #else 69 #define SHREG_BBRA 0xffffffb8 70 #define SHREG_CCR 0xffffffec 71 #define SHREG_EXPEVT 0xffffffd4 72 #define SHREG_INTEVT 0xffffffd8 73 #define SHREG_MMUCR 0xffffffe0 74 #define SHREG_TTB 0xfffffff8 75 #endif 76 77 NENTRY(start) 78 /* Set SP to initial position */ 79 mov.l XLtmpstk, r15 80 81 __INTR_MASK_r0_r1 82 83 /* Set Register Bank to Bank 0 */ 84 mov.l SR_init, r0 85 ldc r0, sr 86 87 xor r0, r0 88 mov.l XL_SHREG_MMUCR, r2 89 mov.l r0, @r2 /* MMU OFF */ 90 91 bra start1 92 nop 93 .align 2 94 SR_init: .long 0x500000F0 95 XL_SHREG_MMUCR: .long SHREG_MMUCR 96 start1: 97 98 #ifdef ROMIMAGE 99 /* Initialize BUS State Control Regs. */ 100 mov.l _ROM_START, r3 101 mov.l XL_ram_start, r4 102 mov.l @r4, r4 103 sub r3, r4 104 /* Set Bus State Controler */ 105 mov.l XLInitializeBsc, r0 106 sub r4, r0 107 jsr @r0 108 nop 109 110 /* Move kernel image from ROM area to RAM area */ 111 mov.l ___end, r0 112 mov.l ___start, r1 113 mov.l _KERNBASE, r2 114 sub r2, r0 115 sub r2, r1 116 sub r1, r0 117 add #4, r0 /* size of bytes to be copied */ 118 shlr2 r0 /* number of long word */ 119 mov.l _ROM_START, r3 120 add r3, r1 /* src address */ 121 mov.l ___start, r3 122 sub r2, r3 123 mov.l XL_ram_start, r4 124 mov.l @r4, r4 125 add r4, r3 /* dest address */ 126 1: 127 mov.l @r1+, r4 128 mov.l r4, @r3 129 add #4, r3 130 dt r0 /* decrement and Test */ 131 bf 1b 132 /* kernel image copy end */ 133 134 mov.l LXstart_in_RAM, r0 135 jmp @r0 /* jump to RAM area */ 136 nop 137 138 .align 2 139 LXstart_in_RAM: 140 .long start_in_RAM 141 XL_ram_start: 142 .long _C_LABEL(ram_start) 143 #else 144 #ifndef DONT_INIT_BSC 145 /* Set Bus State Controler */ 146 mov.l XLInitializeBsc, r0 147 jsr @r0 148 nop 149 #endif 150 #endif 151 152 start_in_RAM: 153 mova 1f, r0 154 mov r0, r4 155 mov.l XLinitSH3, r0 156 jsr @r0 /* call initSH3() */ 157 nop 158 159 .align 2 160 1: 161 162 #ifdef SH4 163 /* CCR must be accessed from P2 area */ 164 mova cache_on, r0 165 mov r0, r5 166 mov.l XLtoP2, r1 167 add r1, r5 168 mova main_label, r0 169 mov r0, r2 170 mov.l XL_SHREG_CCR, r3 171 mov.l XL_CCRVAL, r4 172 jmp @r5 173 nop 174 175 .align 2 176 cache_on: 177 mov.l r4, @r3 /* Write to CCR */ 178 nop 179 nop 180 nop 181 nop 182 nop 183 nop 184 nop 185 nop 186 jmp @r2 187 nop 188 189 .align 2 190 main_label: 191 #endif 192 mov.l XLmain, r0 193 jsr @r0 /* call main() */ 194 nop 195 196 .align 2 197 198 #ifndef DONT_INIT_BSC 199 XLInitializeBsc:.long _C_LABEL(InitializeBsc) 200 #endif 201 ___start: .long start 202 ___etext: .long _etext 203 ___end: .long _end 204 XLtmpstk: .long INIT_STACK 205 _KERNBASE: .long KERNBASE 206 _ROM_START: .long IOM_ROM_BEGIN 207 XLinitSH3: .long _C_LABEL(initSH3) 208 XLmain: .long _C_LABEL(main) 209 XLtoP2: .long 0x20000000 210 XL_SHREG_CCR: .long SHREG_CCR 211 #ifdef SH4 212 #if 1 213 XL_CCRVAL: .long 0x0909 /* Operand cache ON */ 214 #else 215 XL_CCRVAL: .long 0x0000 /* cache OFF */ 216 #endif 217 #endif 218 219 load_and_reset: 220 mov.l XL_start_address, r0 221 mov r0, r8 222 mov.l @r4+, r1 /* r1 = osimage size */ 223 mov.l @r4+, r2 /* r2 = check sum */ 224 shlr2 r1 /* r1 = osimage size in dword */ 225 1: 226 mov.l @r4+, r3 227 mov.l r3, @r0 228 add #4, r0 229 dt r1 230 bf 1b 231 232 jmp @r8 /* jump to start address */ 233 nop 234 235 .align 2 236 XL_start_address: 237 .long IOM_RAM_BEGIN + 0x00010000 238 load_and_reset_end: 239 240 ENTRY(XLoadAndReset) 241 __INTR_MASK_r0_r1 242 /* copy trampoline code to RAM area top */ 243 mov.l XL_load_and_reset, r0 244 mov.l XL_load_and_reset_end, r1 245 mov.l XL_load_trampoline_addr, r2 246 mov r2, r8 247 sub r0, r1 /* r1 = bytes to be copied */ 248 1: mov.b @r0+, r3 249 mov.b r3, @r2 250 add #1, r2 251 dt r1 252 bf 1b 253 254 jmp @r8 /* jump to trampoline code */ 255 nop 256 257 .align 2 258 XL_load_trampoline_addr: 259 .long IOM_RAM_BEGIN + 0x00008000 260 XL_load_and_reset: 261 .long load_and_reset 262 XL_load_and_reset_end: 263 .long load_and_reset_end 264 265 ENTRY(Sh3Reset) 266 mov.l XL_reset_vector, r8 267 jmp @r8 268 nop 269 270 .align 2 271 XL_reset_vector: 272 .long 0xa0000000 273 274 /* 275 * void interrupt_exp(int, int, int, int, stuct trapframe) 276 * __attribute__((__noreturn__)): 277 * on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved, 278 * stack is already setuped. 279 */ 280 .align 2 281 recurse: 282 stc sr, r4 283 ldc r5, spc 284 ldc r4, ssr 285 RECURSEENTRY 286 bra 1f 287 nop 288 NENTRY(interrupt_exp) 289 1: 290 MOV (INTEVT, r0) 291 mov.l @r0, r0 292 mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */ 293 __INTR_MASK_r0_r1 /* mask all interrupt */ 294 __EXCEPTION_UNBLOCK_r0_r1 /* enable exception for TLB handling */ 295 mov.l _L.intrhandler, r0 296 jsr @r0 297 nop 298 tst r0, r0 /* intrhandler() == 0, fast intr return */ 299 bt 2f 300 301 mov.l _L.check_ipending, r0 302 jsr @r0 303 nop 304 tst r0, r0 305 bf 1b /* handle pending interrupt. */ 306 307 /* Check for ASTs on exit to user mode. */ 308 mov.l _L.ast, r0 309 jsr @r0 310 mov r15, r4 311 2: 312 EXCEPTION_RETURN 313 /* NOTREACHED */ 314 .align 2 315 REG_SYMBOL(INTEVT) 316 _L.intrhandler: .long _C_LABEL(intrhandler) 317 _L.ast: .long _C_LABEL(ast) 318 319 NENTRY(Xspllower) 320 sts.l pr, @-r15 321 322 restart: 323 __INTR_MASK_r0_r1 324 __EXCEPTION_UNBLOCK_r0_r1 325 mov.l _L.check_ipending, r0 326 jsr @r0 327 nop 328 tst r0, r0 329 bt 1f 330 331 mov.l _L.restart, r5 332 mov.l _L.recurse, r0 333 jmp @r0 334 nop 335 336 1: 337 __INTR_UNMASK_r0_r1 338 lds.l @r15+, pr 339 rts 340 nop 341 342 .align 2 343 _L.check_ipending: .long _C_LABEL(check_ipending) 344 _L.recurse: .long recurse 345 _L.restart: .long restart 346 347 .data 348 .align 2 349 .globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 350 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames) 351 _C_LABEL(intrcnt): 352 _C_LABEL(eintrcnt): 353 _C_LABEL(intrnames): 354 _C_LABEL(eintrnames): 355
Indexes created Sat Oct 18 08:10:09 GMT 2025