Home | History | Annotate | Line # | Download | only in evbsh3
locore.S revision 1.11
      1 /*	$NetBSD: locore.S,v 1.11 2006/10/07 01:21:47 tsutsui Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1990 The Regents of the University of California.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to Berkeley by
      8  * William Jolitz.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)locore.s	7.3 (Berkeley) 5/13/91
     35  */
     36 
     37 /*-
     38  * Copyright (c) 1993, 1994, 1995, 1997
     39  *	Charles M. Hannum.  All rights reserved.
     40  *
     41  * This code is derived from software contributed to Berkeley by
     42  * William Jolitz.
     43  *
     44  * Redistribution and use in source and binary forms, with or without
     45  * modification, are permitted provided that the following conditions
     46  * are met:
     47  * 1. Redistributions of source code must retain the above copyright
     48  *    notice, this list of conditions and the following disclaimer.
     49  * 2. Redistributions in binary form must reproduce the above copyright
     50  *    notice, this list of conditions and the following disclaimer in the
     51  *    documentation and/or other materials provided with the distribution.
     52  * 3. All advertising materials mentioning features or use of this software
     53  *    must display the following acknowledgement:
     54  *	This product includes software developed by the University of
     55  *	California, Berkeley and its contributors.
     56  * 4. Neither the name of the University nor the names of its contributors
     57  *    may be used to endorse or promote products derived from this software
     58  *    without specific prior written permission.
     59  *
     60  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     61  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     62  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     63  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     64  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     65  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     66  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     67  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     68  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     69  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     70  * SUCH DAMAGE.
     71  *
     72  *	@(#)locore.s	7.3 (Berkeley) 5/13/91
     73  */
     74 
     75 #include "opt_cputype.h"
     76 #include "opt_memsize.h"
     77 #include "assym.h"
     78 
     79 #if defined(SH3) && defined(SH4)
     80 #error "evbsh3 port don't support SH3,SH4 common kernel."
     81 #endif
     82 
     83 #include <sh3/asm.h>
     84 #include <sh3/exception.h>
     85 #include <sh3/locore.h>
     86 #include <sh3/mmu_sh3.h>
     87 #include <sh3/mmu_sh4.h>
     88 #include <sh3/cache_sh3.h>
     89 #include <sh3/cache_sh4.h>
     90 
     91 #define	INIT_STACK							\
     92 	((IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000) | 0x80000000)
     93 
     94 NENTRY(start)
     95 ALTENTRY(kernel_text)
     96 	/* Set SP to initial position */
     97 	mov.l	XLtmpstk, r15
     98 
     99 	/* Mask all interrupt */
    100 	__INTR_MASK(r0, r1)
    101 
    102 	/* Set Register Bank to Bank 0 */
    103 	mov.l	SR_init, r0
    104 	ldc	r0, sr
    105 
    106 	/* MMU off */
    107 	xor	r0, r0
    108 	MOV	(MMUCR, r2)
    109 	mov.l	r0, @r2
    110 
    111 	bra	start1
    112 	nop
    113 	.align	2
    114 SR_init:	.long	0x500000F0
    115 REG_SYMBOL(MMUCR)
    116 start1:
    117 
    118 #ifdef ROMIMAGE
    119 	/* Initialize BUS State Control Regs. */
    120 	mov.l	_ROM_START, r3
    121 	mov.l	XL_ram_start, r4
    122 	mov.l	@r4, r4
    123 	sub	r3, r4
    124 	/* Set Bus State Controller */
    125 	mov.l	XLInitializeBsc, r0
    126 	sub	r4, r0
    127 	jsr	@r0
    128 	nop
    129 
    130 	/* Move kernel image from ROM area to RAM area */
    131 	mov.l	___end, r0
    132 	mov.l	___start, r1
    133 	mov.l	_KERNBASE, r2
    134 	sub	r2, r0
    135 	sub	r2, r1
    136 	sub	r1, r0
    137 	add	#4, r0		/* size of bytes to be copied */
    138 	shlr2	r0		/* number of long word */
    139 	mov.l	_ROM_START, r3
    140 	add	r3, r1		/* src address */
    141 	mov.l	___start, r3
    142 	sub	r2, r3
    143 	mov.l	XL_ram_start, r4
    144 	mov.l	@r4, r4
    145 	add	r4, r3		/* dest address */
    146 1:
    147 	mov.l	@r1+, r4
    148 	mov.l	r4, @r3
    149 	add	#4, r3
    150 	dt	r0		/* decrement and Test */
    151 	bf	1b
    152 	/* kernel image copy end */
    153 
    154 	mov.l	LXstart_in_RAM, r0
    155 	jmp	@r0		/* jump to RAM area */
    156 	nop
    157 
    158 	.align	2
    159 LXstart_in_RAM:
    160 	.long	start_in_RAM
    161 XL_ram_start:
    162 	.long	_C_LABEL(ram_start)
    163 #else /* ROMIMAGE */
    164 #ifndef	DONT_INIT_BSC
    165 	/* Set Bus State Controller */
    166 	mov.l	XLInitializeBsc, r0
    167 	jsr	@r0
    168 	nop
    169 #endif /* !DONT_INIT_BSC */
    170 #endif /* ROMIMAGE */
    171 
    172 start_in_RAM:
    173 	mova	1f, r0
    174 	mov	r0, r4
    175 	mov.l	XLinitSH3, r0
    176 	jsr	@r0		/* call initSH3() */
    177 	nop
    178 
    179 	.align	2
    180 1:
    181 
    182 #ifdef SH4
    183 	/* CCR must be accessed from P2 area */
    184 	mova	cache_on, r0
    185 	mov	r0, r5
    186 	mov.l	XLtoP2, r1
    187 	add	r1, r5
    188 	mova	main_label, r0
    189 	mov	r0, r2
    190 	MOV	(CCR, r3)
    191 	mov.l	XL_CCRVAL, r4
    192 	jmp	@r5
    193 	nop
    194 
    195 	.align	2
    196 cache_on:
    197 	mov.l	r4, @r3 /* Write to CCR */
    198 	nop
    199 	nop
    200 	nop
    201 	nop
    202 	nop
    203 	nop
    204 	nop
    205 	nop
    206 	jmp @r2
    207 	nop
    208 
    209 	.align	2
    210 main_label:
    211 #endif /* SH4 */
    212 	mov.l	XLmain, r0
    213 	jsr	@r0		/* call main() */
    214 	nop
    215 
    216 		.align	2
    217 
    218 #ifndef	DONT_INIT_BSC
    219 XLInitializeBsc:.long	_C_LABEL(InitializeBsc)
    220 #endif /* DONT_INIT_BSC */
    221 ___start:	.long	start
    222 ___etext:	.long	_C_LABEL(etext)
    223 ___end:		.long	_C_LABEL(end)
    224 XLtmpstk:	.long	INIT_STACK
    225 _KERNBASE:	.long	0x8c000000
    226 _ROM_START:	.long	IOM_ROM_BEGIN
    227 XLinitSH3:	.long	_C_LABEL(initSH3)
    228 XLmain:		.long	_C_LABEL(main)
    229 XLtoP2:		.long	0x20000000
    230 REG_SYMBOL(CCR)
    231 #ifdef SH4
    232 XL_CCRVAL:	.long	0x0909 /* Operand cache ON */
    233 #endif /* SH4 */
    234 
    235 load_and_reset:
    236 	mov.l	XL_start_address, r0
    237 	mov	r0, r8
    238 	mov.l	@r4+, r1	/* r1 = osimage size */
    239 	mov.l	@r4+, r2	/* r2 = check sum */
    240 	shlr2	r1		/* r1 = osimage size in dword */
    241 1:
    242 	mov.l	@r4+, r3
    243 	mov.l	r3, @r0
    244 	add	#4, r0
    245 	dt	r1
    246 	bf	1b
    247 
    248 	jmp	@r8		/* jump to start address */
    249 	nop
    250 
    251 	.align	2
    252 XL_start_address:
    253 	.long	IOM_RAM_BEGIN + 0x00010000
    254 load_and_reset_end:
    255 
    256 ENTRY(XLoadAndReset)
    257 	__INTR_MASK(r0, r1)
    258 	/* copy trampoline code to RAM area top */
    259 	mov.l	XL_load_and_reset, r0
    260 	mov.l	XL_load_and_reset_end, r1
    261 	mov.l	XL_load_trampoline_addr, r2
    262 	mov	r2, r8
    263 	sub	r0, r1		/* r1 = bytes to be copied */
    264 1:	mov.b	@r0+, r3
    265 	mov.b	r3, @r2
    266 	add	#1, r2
    267 	dt	r1
    268 	bf	1b
    269 
    270 	jmp	@r8		/* jump to trampoline code */
    271 	nop
    272 
    273 	.align	2
    274 XL_load_trampoline_addr:
    275 	.long	IOM_RAM_BEGIN + 0x00008000
    276 XL_load_and_reset:
    277 	.long	load_and_reset
    278 XL_load_and_reset_end:
    279 	.long	load_and_reset_end
    280