locore.S revision 1.16
1 /* $NetBSD: locore.S,v 1.16 2023/09/29 06:09:20 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)locore.s 7.3 (Berkeley) 5/13/91 35 */ 36 37 /*- 38 * Copyright (c) 1993, 1994, 1995, 1997 39 * Charles M. Hannum. All rights reserved. 40 * 41 * This code is derived from software contributed to Berkeley by 42 * William Jolitz. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by the University of 55 * California, Berkeley and its contributors. 56 * 4. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)locore.s 7.3 (Berkeley) 5/13/91 73 */ 74 75 #include "opt_cputype.h" 76 #include "opt_memsize.h" 77 #include "assym.h" 78 79 #if defined(SH3) && defined(SH4) 80 #error "evbsh3 port don't support SH3,SH4 common kernel." 81 #endif 82 83 #include <sh3/asm.h> 84 #include <sh3/cache_sh3.h> 85 #include <sh3/cache_sh4.h> 86 #include <sh3/exception.h> 87 #include <sh3/locore.h> 88 #include <sh3/mmu_sh3.h> 89 #include <sh3/mmu_sh4.h> 90 #include <sh3/psl.h> 91 92 #define INIT_STACK \ 93 ((IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000) | 0x80000000) 94 95 NENTRY(start) 96 ALTENTRY(kernel_text) 97 /* Set SP to initial position */ 98 mov.l XLtmpstk, r15 99 100 /* Set Status Register */ 101 mov.l SR_init, r0 102 ldc r0, sr 103 104 /* MMU off */ 105 xor r0, r0 106 MOV (MMUCR, r2) 107 mov.l r0, @r2 108 109 bra start1 110 nop 111 .align 2 112 SR_init: .long PSL_MD | PSL_BL | PSL_IMASK 113 REG_SYMBOL(MMUCR) 114 start1: 115 116 #ifdef ROMIMAGE 117 /* Initialize BUS State Control Regs. */ 118 mov.l _ROM_START, r3 119 mov.l XL_ram_start, r4 120 mov.l @r4, r4 121 sub r3, r4 122 /* Set Bus State Controller */ 123 mov.l XLInitializeBsc, r0 124 sub r4, r0 125 jsr @r0 126 nop 127 128 /* Move kernel image from ROM area to RAM area */ 129 mov.l ___end, r0 130 mov.l ___start, r1 131 mov.l _KERNBASE, r2 132 sub r2, r0 133 sub r2, r1 134 sub r1, r0 135 add #4, r0 /* size of bytes to be copied */ 136 shlr2 r0 /* number of long word */ 137 mov.l _ROM_START, r3 138 add r3, r1 /* src address */ 139 mov.l ___start, r3 140 sub r2, r3 141 mov.l XL_ram_start, r4 142 mov.l @r4, r4 143 add r4, r3 /* dest address */ 144 1: 145 mov.l @r1+, r4 146 mov.l r4, @r3 147 add #4, r3 148 dt r0 /* decrement and Test */ 149 bf 1b 150 /* kernel image copy end */ 151 152 mov.l LXstart_in_RAM, r0 153 jmp @r0 /* jump to RAM area */ 154 nop 155 156 .align 2 157 LXstart_in_RAM: 158 .long start_in_RAM 159 XL_ram_start: 160 .long _C_LABEL(ram_start) 161 #else /* ROMIMAGE */ 162 #ifndef DONT_INIT_BSC 163 /* Set Bus State Controller */ 164 mov.l XLInitializeBsc, r0 165 jsr @r0 166 nop 167 #endif /* !DONT_INIT_BSC */ 168 #endif /* ROMIMAGE */ 169 170 start_in_RAM: 171 mova 1f, r0 172 mov r0, r4 173 mov.l XLinitSH3, r0 174 jsr @r0 /* call initSH3() */ 175 nop 176 177 .align 2 178 1: 179 180 #ifdef SH4 181 /* CCR must be accessed from P2 area */ 182 mova cache_on, r0 183 mov r0, r5 184 mov.l XLtoP2, r1 185 add r1, r5 186 mova main_label, r0 187 mov r0, r2 188 MOV (CCR, r3) 189 mov.l XL_CCRVAL, r4 190 jmp @r5 191 nop 192 193 .align 2 194 cache_on: 195 mov.l r4, @r3 /* Write to CCR */ 196 nop 197 nop 198 nop 199 nop 200 nop 201 nop 202 nop 203 nop 204 jmp @r2 205 nop 206 207 .align 2 208 main_label: 209 #endif /* SH4 */ 210 mov.l XLmain, r0 211 jsr @r0 /* call main() */ 212 nop 213 214 .align 2 215 216 #ifndef DONT_INIT_BSC 217 XLInitializeBsc:.long _C_LABEL(InitializeBsc) 218 #endif /* DONT_INIT_BSC */ 219 ___start: .long start 220 ___etext: .long _C_LABEL(etext) 221 ___end: .long _C_LABEL(end) 222 XLtmpstk: .long INIT_STACK 223 _KERNBASE: .long 0x8c000000 224 #ifdef ROMIMAGE 225 _ROM_START: .long IOM_ROM_BEGIN 226 #endif 227 XLinitSH3: .long _C_LABEL(initSH3) 228 XLmain: .long _C_LABEL(main) 229 XLtoP2: .long 0x20000000 230 REG_SYMBOL(CCR) 231 #ifdef SH4 /* invalidate and enable instruction and operand caches */ 232 XL_CCRVAL: .long SH4_CCR_ICI | SH4_CCR_ICE | SH4_CCR_OCI | SH4_CCR_OCE 233 #endif /* SH4 */ 234 235 load_and_reset: 236 mov.l XL_start_address, r0 237 mov r0, r8 238 mov.l @r4+, r1 /* r1 = osimage size */ 239 mov.l @r4+, r2 /* r2 = check sum */ 240 shlr2 r1 /* r1 = osimage size in dword */ 241 1: 242 mov.l @r4+, r3 243 mov.l r3, @r0 244 add #4, r0 245 dt r1 246 bf 1b 247 248 jmp @r8 /* jump to start address */ 249 nop 250 251 .align 2 252 XL_start_address: 253 .long IOM_RAM_BEGIN + 0x00010000 254 load_and_reset_end: 255 256 ENTRY(XLoadAndReset) 257 __INTR_MASK(r0, r1) 258 /* copy trampoline code to RAM area top */ 259 mov.l XL_load_and_reset, r0 260 mov.l XL_load_and_reset_end, r1 261 mov.l XL_load_trampoline_addr, r2 262 mov r2, r8 263 sub r0, r1 /* r1 = bytes to be copied */ 264 1: mov.b @r0+, r3 265 mov.b r3, @r2 266 add #1, r2 267 dt r1 268 bf 1b 269 270 jmp @r8 /* jump to trampoline code */ 271 nop 272 273 .align 2 274 XL_load_trampoline_addr: 275 .long IOM_RAM_BEGIN + 0x00008000 276 XL_load_and_reset: 277 .long load_and_reset 278 XL_load_and_reset_end: 279 .long load_and_reset_end 280
Indexes created Tue Oct 21 15:09:54 GMT 2025