locore.S revision 1.2
1 /* $NetBSD: locore.S,v 1.2 2002/02/28 01:53:42 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1993, 1994, 1995, 1997 5 * Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)locore.s 7.3 (Berkeley) 5/13/91 41 */ 42 43 #include "opt_memsize.h" 44 #include "assym.h" 45 46 #if defined(SH3) && defined(SH4) 47 #error "evbsh3 port don't support SH3,SH4 common kernel." 48 #endif 49 50 #include <sh3/asm.h> 51 #include <sh3/locore.h> 52 #include <sh3/trapreg.h> 53 #include <sh3/mmu_sh3.h> 54 #include <sh3/mmu_sh4.h> 55 #include <sh3/cache_sh3.h> 56 #include <sh3/cache_sh4.h> 57 58 #define INIT_STACK IOM_RAM_BEGIN + IOM_RAM_SIZE - 0x00001000 59 60 NENTRY(start) 61 /* Set SP to initial position */ 62 mov.l XLtmpstk, r15 63 64 /* Mask all interrupt */ 65 __INTR_MASK(r0, r1) 66 67 /* Set Register Bank to Bank 0 */ 68 mov.l SR_init, r0 69 ldc r0, sr 70 71 /* MMU off */ 72 xor r0, r0 73 MOV (MMUCR, r2) 74 mov.l r0, @r2 75 76 bra start1 77 nop 78 .align 2 79 SR_init: .long 0x500000F0 80 REG_SYMBOL(MMUCR) 81 start1: 82 83 #ifdef ROMIMAGE 84 /* Initialize BUS State Control Regs. */ 85 mov.l _ROM_START, r3 86 mov.l XL_ram_start, r4 87 mov.l @r4, r4 88 sub r3, r4 89 /* Set Bus State Controler */ 90 mov.l XLInitializeBsc, r0 91 sub r4, r0 92 jsr @r0 93 nop 94 95 /* Move kernel image from ROM area to RAM area */ 96 mov.l ___end, r0 97 mov.l ___start, r1 98 mov.l _KERNBASE, r2 99 sub r2, r0 100 sub r2, r1 101 sub r1, r0 102 add #4, r0 /* size of bytes to be copied */ 103 shlr2 r0 /* number of long word */ 104 mov.l _ROM_START, r3 105 add r3, r1 /* src address */ 106 mov.l ___start, r3 107 sub r2, r3 108 mov.l XL_ram_start, r4 109 mov.l @r4, r4 110 add r4, r3 /* dest address */ 111 1: 112 mov.l @r1+, r4 113 mov.l r4, @r3 114 add #4, r3 115 dt r0 /* decrement and Test */ 116 bf 1b 117 /* kernel image copy end */ 118 119 mov.l LXstart_in_RAM, r0 120 jmp @r0 /* jump to RAM area */ 121 nop 122 123 .align 2 124 LXstart_in_RAM: 125 .long start_in_RAM 126 XL_ram_start: 127 .long _C_LABEL(ram_start) 128 #else /* ROMIMAGE */ 129 #ifndef DONT_INIT_BSC 130 /* Set Bus State Controler */ 131 mov.l XLInitializeBsc, r0 132 jsr @r0 133 nop 134 #endif /* !DONT_INIT_BSC */ 135 #endif /* ROMIMAGE */ 136 137 start_in_RAM: 138 mova 1f, r0 139 mov r0, r4 140 mov.l XLinitSH3, r0 141 jsr @r0 /* call initSH3() */ 142 nop 143 144 .align 2 145 1: 146 147 #ifdef SH4 148 /* CCR must be accessed from P2 area */ 149 mova cache_on, r0 150 mov r0, r5 151 mov.l XLtoP2, r1 152 add r1, r5 153 mova main_label, r0 154 mov r0, r2 155 MOV (CCR, r3) 156 mov.l XL_CCRVAL, r4 157 jmp @r5 158 nop 159 160 .align 2 161 cache_on: 162 mov.l r4, @r3 /* Write to CCR */ 163 nop 164 nop 165 nop 166 nop 167 nop 168 nop 169 nop 170 nop 171 jmp @r2 172 nop 173 174 .align 2 175 main_label: 176 #endif /* SH4 */ 177 mov.l XLmain, r0 178 jsr @r0 /* call main() */ 179 nop 180 181 .align 2 182 183 #ifndef DONT_INIT_BSC 184 XLInitializeBsc:.long _C_LABEL(InitializeBsc) 185 #endif /* DONT_INIT_BSC */ 186 ___start: .long start 187 ___etext: .long _etext 188 ___end: .long _end 189 XLtmpstk: .long INIT_STACK 190 _KERNBASE: .long 0x8c000000 191 _ROM_START: .long IOM_ROM_BEGIN 192 XLinitSH3: .long _C_LABEL(initSH3) 193 XLmain: .long _C_LABEL(main) 194 XLtoP2: .long 0x20000000 195 REG_SYMBOL(CCR) 196 #ifdef SH4 197 XL_CCRVAL: .long 0x0909 /* Operand cache ON */ 198 #endif /* SH4 */ 199 200 load_and_reset: 201 mov.l XL_start_address, r0 202 mov r0, r8 203 mov.l @r4+, r1 /* r1 = osimage size */ 204 mov.l @r4+, r2 /* r2 = check sum */ 205 shlr2 r1 /* r1 = osimage size in dword */ 206 1: 207 mov.l @r4+, r3 208 mov.l r3, @r0 209 add #4, r0 210 dt r1 211 bf 1b 212 213 jmp @r8 /* jump to start address */ 214 nop 215 216 .align 2 217 XL_start_address: 218 .long IOM_RAM_BEGIN + 0x00010000 219 load_and_reset_end: 220 221 ENTRY(XLoadAndReset) 222 __INTR_MASK(r0, r1) 223 /* copy trampoline code to RAM area top */ 224 mov.l XL_load_and_reset, r0 225 mov.l XL_load_and_reset_end, r1 226 mov.l XL_load_trampoline_addr, r2 227 mov r2, r8 228 sub r0, r1 /* r1 = bytes to be copied */ 229 1: mov.b @r0+, r3 230 mov.b r3, @r2 231 add #1, r2 232 dt r1 233 bf 1b 234 235 jmp @r8 /* jump to trampoline code */ 236 nop 237 238 .align 2 239 XL_load_trampoline_addr: 240 .long IOM_RAM_BEGIN + 0x00008000 241 XL_load_and_reset: 242 .long load_and_reset 243 XL_load_and_reset_end: 244 .long load_and_reset_end 245 246 /* 247 * void interrupt_exp(int, int, int, int, stuct trapframe) 248 * __attribute__((__noreturn__)): 249 * on entry, SR.BL = 1, SR_RB = 0, all regsiters are saved, 250 * stack is already setuped. 251 */ 252 .align 2 253 recurse: 254 stc sr, r4 255 ldc r5, spc 256 ldc r4, ssr 257 RECURSEENTRY 258 bra 1f 259 nop 260 NENTRY(interrupt_exp) 261 1: 262 MOV (INTEVT, r0) 263 mov.l @r0, r0 264 mov.l r0, @(TF_TRAPNO, r15) /* trapframe->tf_trapno = INTEVT */ 265 __INTR_MASK(r0, r1) /* mask all interrupt */ 266 __EXCEPTION_UNBLOCK(r0, r1) /* enable exception for TLB handling */ 267 mov.l _L.intrhandler, r0 268 jsr @r0 269 nop 270 tst r0, r0 /* intrhandler() == 0, fast intr return */ 271 bt 2f 272 273 mov.l _L.check_ipending, r0 274 jsr @r0 275 nop 276 tst r0, r0 277 bf 1b /* handle pending interrupt. */ 278 279 /* Check for ASTs on exit to user mode. */ 280 mov.l _L.ast, r0 281 jsr @r0 282 mov r15, r4 283 2: 284 EXCEPTION_RETURN 285 /* NOTREACHED */ 286 .align 2 287 REG_SYMBOL(INTEVT) 288 _L.intrhandler: .long _C_LABEL(intrhandler) 289 _L.ast: .long _C_LABEL(ast) 290 291 NENTRY(Xspllower) 292 sts.l pr, @-r15 293 294 restart: 295 __INTR_MASK(r0, r1) 296 __EXCEPTION_UNBLOCK(r0, r1) 297 mov.l _L.check_ipending, r0 298 jsr @r0 299 nop 300 tst r0, r0 301 bt 1f 302 303 mov.l _L.restart, r5 304 mov.l _L.recurse, r0 305 jmp @r0 306 nop 307 308 1: 309 __INTR_UNMASK(r0, r1) 310 lds.l @r15+, pr 311 rts 312 nop 313 314 .align 2 315 _L.check_ipending: .long _C_LABEL(check_ipending) 316 _L.recurse: .long recurse 317 _L.restart: .long restart 318 319 .data 320 .align 2 321 .globl _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 322 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames) 323 _C_LABEL(intrcnt): 324 _C_LABEL(eintrcnt): 325 _C_LABEL(intrnames): 326 _C_LABEL(eintrnames): 327
Indexes created Wed Oct 15 07:09:58 GMT 2025