machdep.c revision 1.53 
1/*	$NetBSD: machdep.c,v 1.53 2005/04/01 11:59:26 yamt Exp $	*/
2
3/*-
4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 *    must display the following acknowledgement:
21 *	This product includes software developed by the NetBSD
22 *	Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 *    contributors may be used to endorse or promote products derived
25 *    from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40/*-
41 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
42 * All rights reserved.
43 *
44 * This code is derived from software contributed to Berkeley by
45 * William Jolitz.
46 *
47 * Redistribution and use in source and binary forms, with or without
48 * modification, are permitted provided that the following conditions
49 * are met:
50 * 1. Redistributions of source code must retain the above copyright
51 *    notice, this list of conditions and the following disclaimer.
52 * 2. Redistributions in binary form must reproduce the above copyright
53 *    notice, this list of conditions and the following disclaimer in the
54 *    documentation and/or other materials provided with the distribution.
55 * 3. Neither the name of the University nor the names of its contributors
56 *    may be used to endorse or promote products derived from this software
57 *    without specific prior written permission.
58 *
59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * SUCH DAMAGE.
70 *
71 *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
72 */
73
74#include <sys/cdefs.h>
75__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.53 2005/04/01 11:59:26 yamt Exp $");
76
77#include "opt_ddb.h"
78#include "opt_kgdb.h"
79#include "opt_memsize.h"
80#include "opt_initbsc.h"
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/kernel.h>
85#include <sys/user.h>
86#include <sys/mount.h>
87#include <sys/reboot.h>
88#include <sys/sysctl.h>
89#include <sys/ksyms.h>
90
91#include <uvm/uvm_extern.h>
92
93#include <dev/cons.h>
94
95#include <sh3/bscreg.h>
96#include <sh3/cpgreg.h>
97#include <sh3/cache_sh3.h>
98#include <sh3/cache_sh4.h>
99#include <sh3/exception.h>
100
101#include <machine/bus.h>
102#include <machine/intr.h>
103
104#ifdef DDB
105#include <machine/db_machdep.h>
106#include <ddb/db_extern.h>
107#endif
108
109#include "ksyms.h"
110
111/* the following is used externally (sysctl_hw) */
112char machine[] = MACHINE;		/* evbsh3 */
113char machine_arch[] = MACHINE_ARCH;	/* sh3eb or sh3el */
114
115void initSH3 __P((void *));
116void LoadAndReset __P((char *));
117void XLoadAndReset __P((char *));
118
119/*
120 * Machine-dependent startup code
121 *
122 * This is called from main() in kern/main.c.
123 */
124void
125cpu_startup()
126{
127
128	sh_startup();
129}
130
131/*
132 * machine dependent system variables.
133 */
134static int
135sysctl_machdep_loadandreset(SYSCTLFN_ARGS)
136{
137	char *osimage;
138	int error;
139
140	error = sysctl_lookup(SYSCTLFN_CALL(rnode));
141	if (error || newp == NULL)
142		return (error);
143
144	osimage = (char *)(*(u_long *)newp);
145	LoadAndReset(osimage);
146	/* not reach here */
147	return (0);
148}
149
150SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup")
151{
152
153	sysctl_createv(clog, 0, NULL, NULL,
154		       CTLFLAG_PERMANENT,
155		       CTLTYPE_NODE, "machdep", NULL,
156		       NULL, 0, NULL, 0,
157		       CTL_MACHDEP, CTL_EOL);
158
159	sysctl_createv(clog, 0, NULL, NULL,
160		       CTLFLAG_PERMANENT,
161		       CTLTYPE_STRUCT, "console_device", NULL,
162		       sysctl_consdev, 0, NULL, sizeof(dev_t),
163		       CTL_MACHDEP, CPU_CONSDEV, CTL_EOL);
164/*
165<atatat> okay...your turn to play.
166<atatat> pick a number.
167<kjk> 98752.
168*/
169	sysctl_createv(clog, 0, NULL, NULL,
170		       CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE,
171		       CTLTYPE_INT, "load_and_reset", NULL,
172		       sysctl_machdep_loadandreset, 98752, NULL, 0,
173		       CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL);
174}
175
176void
177cpu_reboot(howto, bootstr)
178	int howto;
179	char *bootstr;
180{
181	static int waittime = -1;
182
183	if (cold) {
184		howto |= RB_HALT;
185		goto haltsys;
186	}
187
188	boothowto = howto;
189	if ((howto & RB_NOSYNC) == 0 && waittime < 0) {
190		waittime = 0;
191		vfs_shutdown();
192		/*
193		 * If we've been adjusting the clock, the todr
194		 * will be out of synch; adjust it now.
195		 */
196		/* resettodr(); */
197	}
198
199	/* Disable interrupts. */
200	splhigh();
201
202	/* Do a dump if requested. */
203	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
204		dumpsys();
205
206haltsys:
207	doshutdownhooks();
208
209	if (howto & RB_HALT) {
210		printf("\n");
211		printf("The operating system has halted.\n");
212		printf("Please press any key to reboot.\n\n");
213		cngetc();
214	}
215
216	printf("rebooting...\n");
217	cpu_reset();
218	for(;;)
219		;
220	/*NOTREACHED*/
221}
222
223void
224initSH3(void *pc)	/* XXX return address */
225{
226	extern char _edata[], _end[];
227	vaddr_t kernend;
228
229	/* Clear bss */
230	memset(_edata, 0, _end - _edata);
231
232	/* Initilize CPU ops. */
233#if defined(SH3) && defined(SH4)
234#error "don't define both SH3 and SH4"
235#elif defined(SH3)
236#if defined(SH7708)
237	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708);
238#elif defined(SH7708S)
239	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S);
240#elif defined(SH7708R)
241	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R);
242#elif defined(SH7709)
243	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709);
244#elif defined(SH7709A)
245	sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A);
246#else
247#error "unsupported SH3 variants"
248#endif
249#elif defined(SH4)
250#if defined(SH7750)
251	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750);
252#elif defined(SH7750S)
253	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S);
254#else
255#error "unsupported SH4 variants"
256#endif
257#else
258#error "define SH3 or SH4"
259#endif
260	/* Console */
261	consinit();
262
263	/* Load memory to UVM */
264	kernend = atop(round_page(SH3_P1SEG_TO_PHYS(_end)));
265	physmem = atop(IOM_RAM_SIZE);
266	uvm_page_physload(
267		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
268		kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE),
269		VM_FREELIST_DEFAULT);
270
271	/* Initialize proc0 u-area */
272	sh_proc0_init();
273
274	/* Initialize pmap and start to address translation */
275	pmap_bootstrap();
276
277#if NKSYMS || defined(DDB) || defined(LKM)
278	ksyms_init(0, NULL, NULL);
279#endif
280
281	/*
282	 * XXX We can't return here, because we change stack pointer.
283	 *     So jump to return address directly.
284	 */
285	__asm __volatile (
286		"jmp	@%0;"
287		"mov	%1, r15"
288		:: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank));
289}
290
291/*
292 * consinit:
293 * initialize the system console.
294 * XXX - shouldn't deal with this initted thing, but then,
295 * it shouldn't be called from init386 either.
296 */
297void
298consinit()
299{
300	static int initted;
301
302	if (initted)
303		return;
304	initted = 1;
305
306	cninit();
307}
308
309int
310bus_space_map (t, addr, size, flags, bshp)
311	bus_space_tag_t t;
312	bus_addr_t addr;
313	bus_size_t size;
314	int flags;
315	bus_space_handle_t *bshp;
316{
317
318	*bshp = (bus_space_handle_t)addr;
319
320	return 0;
321}
322
323int
324sh_memio_subregion(t, bsh, offset, size, nbshp)
325	bus_space_tag_t t;
326	bus_space_handle_t bsh;
327	bus_size_t offset, size;
328	bus_space_handle_t *nbshp;
329{
330
331	*nbshp = bsh + offset;
332	return (0);
333}
334
335int
336sh_memio_alloc(t, rstart, rend, size, alignment, boundary, flags,
337	       bpap, bshp)
338	bus_space_tag_t t;
339	bus_addr_t rstart, rend;
340	bus_size_t size, alignment, boundary;
341	int flags;
342	bus_addr_t *bpap;
343	bus_space_handle_t *bshp;
344{
345	*bshp = *bpap = rstart;
346
347	return (0);
348}
349
350void
351sh_memio_free(t, bsh, size)
352	bus_space_tag_t t;
353	bus_space_handle_t bsh;
354	bus_size_t size;
355{
356
357}
358
359void
360sh_memio_unmap(t, bsh, size)
361	bus_space_tag_t t;
362	bus_space_handle_t bsh;
363	bus_size_t size;
364{
365	return;
366}
367
368#ifdef SH4_PCMCIA
369
370int
371shpcmcia_memio_map(t, bpa, size, flags, bshp)
372	bus_space_tag_t t;
373	bus_addr_t bpa;
374	bus_size_t size;
375	int flags;
376	bus_space_handle_t *bshp;
377{
378	int error;
379	struct extent *ex;
380	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
381
382	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
383	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
384	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
385		*bshp = (bus_space_handle_t)bpa;
386
387		return 0;
388	}
389
390	ex = iomem_ex;
391
392#if 0
393	/*
394	 * Before we go any further, let's make sure that this
395	 * region is available.
396	 */
397	error = extent_alloc_region(ex, bpa, size,
398				    EX_NOWAIT | EX_MALLOCOK );
399	if (error){
400		printf("sh3_pcmcia_memio_map:extent_alloc_region error\n");
401		return (error);
402	}
403#endif
404
405	/*
406	 * For memory space, map the bus physical address to
407	 * a kernel virtual address.
408	 */
409	error = shpcmcia_mem_add_mapping(bpa, size, (int)t, bshp );
410#if 0
411	if (error) {
412		if (extent_free(ex, bpa, size, EX_NOWAIT | EX_MALLOCOK )) {
413			printf("sh3_pcmcia_memio_map: pa 0x%lx, size 0x%lx\n",
414			       bpa, size);
415			printf("sh3_pcmcia_memio_map: can't free region\n");
416		}
417	}
418#endif
419
420	return (error);
421}
422
423int
424shpcmcia_mem_add_mapping(bpa, size, type, bshp)
425	bus_addr_t bpa;
426	bus_size_t size;
427	int type;
428	bus_space_handle_t *bshp;
429{
430	u_long pa, endpa;
431	vaddr_t va;
432	pt_entry_t *pte;
433	unsigned int m = 0;
434	int io_type = type & ~SH3_BUS_SPACE_PCMCIA_8BIT;
435
436	pa = sh3_trunc_page(bpa);
437	endpa = sh3_round_page(bpa + size);
438
439#ifdef DIAGNOSTIC
440	if (endpa <= pa)
441		panic("sh3_pcmcia_mem_add_mapping: overflow");
442#endif
443
444	va = uvm_km_alloc(kernel_map, endpa - pa, 0, UVM_KMF_VAONLY);
445	if (va == 0){
446		printf("shpcmcia_add_mapping: nomem \n");
447		return (ENOMEM);
448	}
449
450	*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
451
452#define MODE(t, s)							\
453	(t) & SH3_BUS_SPACE_PCMCIA_8BIT ?				\
454		_PG_PCMCIA_ ## s ## 8 :					\
455		_PG_PCMCIA_ ## s ## 16
456	switch (io_type) {
457	default:
458		panic("unknown pcmcia space.");
459		/* NOTREACHED */
460	case SH3_BUS_SPACE_PCMCIA_IO:
461		m = MODE(type, IO);
462		break;
463	case SH3_BUS_SPACE_PCMCIA_MEM:
464		m = MODE(type, MEM);
465		break;
466	case SH3_BUS_SPACE_PCMCIA_ATT:
467		m = MODE(type, ATTR);
468		break;
469	}
470#undef MODE
471
472	for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
473		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
474		pte = __pmap_kpte_lookup(va);
475		KDASSERT(pte);
476		*pte |= m;  /* PTEA PCMCIA assistant bit */
477		sh_tlb_update(0, va, *pte);
478	}
479
480	return 0;
481}
482
483void
484shpcmcia_memio_unmap(t, bsh, size)
485	bus_space_tag_t t;
486	bus_space_handle_t bsh;
487	bus_size_t size;
488{
489	struct extent *ex;
490	u_long va, endva;
491	bus_addr_t bpa;
492	bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT;
493
494	if (pt != SH3_BUS_SPACE_PCMCIA_IO &&
495	    pt != SH3_BUS_SPACE_PCMCIA_MEM &&
496	    pt != SH3_BUS_SPACE_PCMCIA_ATT) {
497		return ;
498	}
499
500	ex = iomem_ex;
501
502	va = sh3_trunc_page(bsh);
503	endva = sh3_round_page(bsh + size);
504
505#ifdef DIAGNOSTIC
506	if (endva <= va)
507		panic("sh3_pcmcia_memio_unmap: overflow");
508#endif
509
510	pmap_extract(pmap_kernel(), va, &bpa);
511	bpa += bsh & PGOFSET;
512
513	/*
514	 * Free the kernel virtual mapping.
515	 */
516	pmap_kremove(va, endva - va);
517	pmap_update(pmap_kernel());
518	uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
519
520#if 0
521	if (extent_free(ex, bpa, size,
522			EX_NOWAIT | EX_MALLOCOK)) {
523		printf("sh3_pcmcia_memio_unmap: %s 0x%lx, size 0x%lx\n",
524		       "pa", bpa, size);
525		printf("sh3_pcmcia_memio_unmap: can't free region\n");
526	}
527#endif
528}
529
530void
531shpcmcia_memio_free(t, bsh, size)
532	bus_space_tag_t t;
533	bus_space_handle_t bsh;
534	bus_size_t size;
535{
536
537	/* sh3_pcmcia_memio_unmap() does all that we need to do. */
538	shpcmcia_memio_unmap(t, bsh, size);
539}
540
541int
542shpcmcia_memio_subregion(t, bsh, offset, size, nbshp)
543	bus_space_tag_t t;
544	bus_space_handle_t bsh;
545	bus_size_t offset, size;
546	bus_space_handle_t *nbshp;
547{
548
549	*nbshp = bsh + offset;
550	return (0);
551}
552
553#endif /* SH4_PCMCIA */
554
555#if !defined(DONT_INIT_BSC)
556/*
557 * InitializeBsc
558 * : BSC(Bus State Controller)
559 */
560void InitializeBsc __P((void));
561
562void
563InitializeBsc()
564{
565
566	/*
567	 * Drive RAS,CAS in stand by mode and bus release mode
568	 * Area0 = Normal memory, Area5,6=Normal(no burst)
569	 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory
570	 * Area4 = Normal Memory
571	 * Area6 = Normal memory
572	 */
573#if defined(SH3)
574	_reg_write_2(SH3_BCR1, BSC_BCR1_VAL);
575#elif defined(SH4)
576	_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
577#endif
578
579	/*
580	 * Bus Width
581	 * Area4: Bus width = 16bit
582	 * Area6,5 = 16bit
583	 * Area1 = 8bit
584	 * Area2,3: Bus width = 32bit
585	 */
586	_reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
587
588	/*
589	 * Idle cycle number in transition area and read to write
590	 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3
591	 * Area1 = 3, Area0 = 3
592	 */
593#if defined(SH3)
594	_reg_write_2(SH3_WCR1, BSC_WCR1_VAL);
595#elif defined(SH4)
596	_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
597#endif
598
599	/*
600	 * Wait cycle
601	 * Area 6 = 6
602	 * Area 5 = 2
603	 * Area 4 = 10
604	 * Area 3 = 3
605	 * Area 2,1 = 3
606	 * Area 0 = 6
607	 */
608#if defined(SH3)
609	_reg_write_2(SH3_WCR2, BSC_WCR2_VAL);
610#elif defined(SH4)
611	_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
612#endif
613
614#if defined(SH4) && defined(BSC_WCR3_VAL)
615	_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
616#endif
617
618	/*
619	 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle,
620	 * write pre-charge=1cycle
621	 * CAS before RAS refresh RAS assert time = 3 cycle
622	 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON
623	 * CAS before RAS refresh ON, EDO DRAM
624	 */
625#if defined(SH3)
626	_reg_write_2(SH3_MCR, BSC_MCR_VAL);
627#elif defined(SH4)
628	_reg_write_4(SH4_MCR, BSC_MCR_VAL);
629#endif
630
631#if defined(BSC_SDMR2_VAL)
632	_reg_write_1(BSC_SDMR2_VAL, 0);
633#endif
634
635#if defined(BSC_SDMR3_VAL)
636#if !(defined(COMPUTEXEVB) && defined(SH7709A))
637	_reg_write_1(BSC_SDMR3_VAL, 0);
638#else
639	_reg_write_2(0x1a000000, 0);	/* ADDSET */
640	_reg_write_1(BSC_SDMR3_VAL, 0);
641	_reg_write_2(0x18000000, 0);	/* ADDRST */
642#endif /* !(COMPUTEXEVB && SH7709A) */
643#endif /* BSC_SDMR3_VAL */
644
645	/*
646	 * PCMCIA Control Register
647	 * OE/WE assert delay 3.5 cycle
648	 * OE/WE negate-address delay 3.5 cycle
649	 */
650#ifdef BSC_PCR_VAL
651	_reg_write_2(SH_(PCR), BSC_PCR_VAL);
652#endif
653
654	/*
655	 * Refresh Timer Control/Status Register
656	 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt
657	 * Count Limit = 1024
658	 * In following statement, the reason why high byte = 0xa5(a4 in RFCR)
659	 * is the rule of SH3 in writing these register.
660	 */
661	_reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
662
663	/*
664	 * Refresh Timer Counter
665	 * Initialize to 0
666	 */
667#ifdef BSC_RTCNT_VAL
668	_reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
669#endif
670
671	/* set Refresh Time Constant Register */
672	_reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
673
674	/* init Refresh Count Register */
675#ifdef BSC_RFCR_VAL
676	_reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
677#endif
678
679	/*
680	 * Clock Pulse Generator
681	 */
682	/* Set Clock mode (make internal clock double speed) */
683	_reg_write_2(SH_(FRQCR), FRQCR_VAL);
684
685	/*
686	 * Cache
687	 */
688#ifndef CACHE_DISABLE
689	/* Cache ON */
690	_reg_write_4(SH_(CCR), 0x1);
691#endif
692}
693#endif /* !DONT_INIT_BSC */
694
695
696 /* XXX This value depends on physical available memory */
697#define OSIMAGE_BUF_ADDR	(IOM_RAM_BEGIN + 0x00400000)
698
699void
700LoadAndReset(osimage)
701	char *osimage;
702{
703	void *buf_addr;
704	u_long size;
705	u_long *src;
706	u_long *dest;
707	u_long csum = 0;
708	u_long csum2 = 0;
709	u_long size2;
710
711	printf("LoadAndReset: copy start\n");
712	buf_addr = (void *)OSIMAGE_BUF_ADDR;
713
714	size = *(u_long *)osimage;
715	src = (u_long *)osimage;
716	dest = buf_addr;
717
718	size = (size + sizeof(u_long) * 2 + 3) >> 2;
719	size2 = size;
720
721	while (size--) {
722		csum += *src;
723		*dest++ = *src++;
724	}
725
726	dest = buf_addr;
727	while (size2--)
728		csum2 += *dest++;
729
730	printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2);
731	printf("start XLoadAndReset\n");
732
733	/* mask all externel interrupt (XXX) */
734
735	XLoadAndReset(buf_addr);
736}
737
738void
739intc_intr(int ssr, int spc, int ssp)
740{
741	struct intc_intrhand *ih;
742	struct clockframe cf;
743	int s, evtcode;
744
745	switch (cpu_product) {
746	case CPU_PRODUCT_7708:
747	case CPU_PRODUCT_7708S:
748	case CPU_PRODUCT_7708R:
749		evtcode = _reg_read_4(SH3_INTEVT);
750		break;
751	case CPU_PRODUCT_7709:
752	case CPU_PRODUCT_7709A:
753		evtcode = _reg_read_4(SH7709_INTEVT2);
754		break;
755	case CPU_PRODUCT_7750:
756	case CPU_PRODUCT_7750S:
757		evtcode = _reg_read_4(SH4_INTEVT);
758		break;
759	default:
760#ifdef DIAGNOSTIC
761		panic("intr_intc: cpu_product %d unhandled!", cpu_product);
762#endif
763		return;
764	}
765
766	ih = EVTCODE_IH(evtcode);
767	KDASSERT(ih->ih_func);
768	/*
769	 * On entry, all interrrupts are disabled,
770	 * and exception is enabled for P3 access. (kernel stack is P3,
771	 * SH3 may or may not cause TLB miss when access stack.)
772	 * Enable higher level interrupt here.
773	 */
774	s = _cpu_intr_resume(ih->ih_level);
775
776	switch (evtcode) {
777	default:
778		(*ih->ih_func)(ih->ih_arg);
779		break;
780	case SH_INTEVT_TMU0_TUNI0:
781		cf.spc = spc;
782		cf.ssr = ssr;
783		cf.ssp = ssp;
784		(*ih->ih_func)(&cf);
785		break;
786	case SH_INTEVT_NMI:
787		printf("NMI ignored.\n");
788		break;
789	}
790}
791
792