machdep.c revision 1.67
1/* $NetBSD: machdep.c,v 1.67 2009/03/18 10:22:28 cegger Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/*- 34 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * William Jolitz. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 65 */ 66 67#include <sys/cdefs.h> 68__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.67 2009/03/18 10:22:28 cegger Exp $"); 69 70#include "opt_ddb.h" 71#include "opt_kgdb.h" 72#include "opt_memsize.h" 73#include "opt_initbsc.h" 74 75#include <sys/param.h> 76#include <sys/systm.h> 77#include <sys/kernel.h> 78#include <sys/user.h> 79#include <sys/mount.h> 80#include <sys/reboot.h> 81#include <sys/sysctl.h> 82#include <sys/ksyms.h> 83#include <sys/device.h> 84 85#include <uvm/uvm_extern.h> 86 87#include <dev/cons.h> 88 89#include <sh3/bscreg.h> 90#include <sh3/cpgreg.h> 91#include <sh3/cache_sh3.h> 92#include <sh3/cache_sh4.h> 93#include <sh3/exception.h> 94 95#include <machine/bus.h> 96#include <machine/intr.h> 97 98#ifdef DDB 99#include <machine/db_machdep.h> 100#include <ddb/db_extern.h> 101#endif 102 103#include "ksyms.h" 104 105/* the following is used externally (sysctl_hw) */ 106char machine[] = MACHINE; /* evbsh3 */ 107char machine_arch[] = MACHINE_ARCH; /* sh3eb or sh3el */ 108 109void initSH3(void *); 110void LoadAndReset(const char *); 111void XLoadAndReset(char *); 112 113/* 114 * Machine-dependent startup code 115 * 116 * This is called from main() in kern/main.c. 117 */ 118void 119cpu_startup(void) 120{ 121 122 sh_startup(); 123} 124 125/* 126 * machine dependent system variables. 127 */ 128static int 129sysctl_machdep_loadandreset(SYSCTLFN_ARGS) 130{ 131 const char *osimage; 132 int error; 133 134 error = sysctl_lookup(SYSCTLFN_CALL(__UNCONST(rnode))); 135 if (error || newp == NULL) 136 return (error); 137 138 osimage = (const char *)(*(const u_long *)newp); 139 LoadAndReset(osimage); 140 /* not reach here */ 141 return (0); 142} 143 144SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 145{ 146 147 sysctl_createv(clog, 0, NULL, NULL, 148 CTLFLAG_PERMANENT, 149 CTLTYPE_NODE, "machdep", NULL, 150 NULL, 0, NULL, 0, 151 CTL_MACHDEP, CTL_EOL); 152 153 sysctl_createv(clog, 0, NULL, NULL, 154 CTLFLAG_PERMANENT, 155 CTLTYPE_STRUCT, "console_device", NULL, 156 sysctl_consdev, 0, NULL, sizeof(dev_t), 157 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 158/* 159<atatat> okay...your turn to play. 160<atatat> pick a number. 161<kjk> 98752. 162*/ 163 sysctl_createv(clog, 0, NULL, NULL, 164 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 165 CTLTYPE_INT, "load_and_reset", NULL, 166 sysctl_machdep_loadandreset, 98752, NULL, 0, 167 CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL); 168} 169 170void 171cpu_reboot(int howto, char *bootstr) 172{ 173 static int waittime = -1; 174 175 if (cold) { 176 howto |= RB_HALT; 177 goto haltsys; 178 } 179 180 boothowto = howto; 181 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 182 waittime = 0; 183 vfs_shutdown(); 184 /* 185 * If we've been adjusting the clock, the todr 186 * will be out of synch; adjust it now. 187 */ 188 /* resettodr(); */ 189 } 190 191 /* Disable interrupts. */ 192 splhigh(); 193 194 /* Do a dump if requested. */ 195 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 196 dumpsys(); 197 198haltsys: 199 doshutdownhooks(); 200 201 pmf_system_shutdown(boothowto); 202 203 if (howto & RB_HALT) { 204 printf("\n"); 205 printf("The operating system has halted.\n"); 206 printf("Please press any key to reboot.\n\n"); 207 cngetc(); 208 } 209 210 printf("rebooting...\n"); 211 cpu_reset(); 212 for(;;) 213 ; 214 /*NOTREACHED*/ 215} 216 217void 218initSH3(void *pc) /* XXX return address */ 219{ 220 extern char edata[], end[]; 221 vaddr_t kernend; 222 223 /* Clear bss */ 224 memset(edata, 0, end - edata); 225 226 /* Initilize CPU ops. */ 227#if defined(SH3) && defined(SH4) 228#error "don't define both SH3 and SH4" 229#elif defined(SH3) 230#if defined(SH7708) 231 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708); 232#elif defined(SH7708S) 233 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S); 234#elif defined(SH7708R) 235 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R); 236#elif defined(SH7709) 237 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709); 238#elif defined(SH7709A) 239 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A); 240#else 241#error "unsupported SH3 variants" 242#endif 243#elif defined(SH4) 244#if defined(SH7750) 245 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750); 246#elif defined(SH7750S) 247 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S); 248#else 249#error "unsupported SH4 variants" 250#endif 251#else 252#error "define SH3 or SH4" 253#endif 254 /* Console */ 255 consinit(); 256 257 /* Load memory to UVM */ 258 kernend = atop(round_page(SH3_P1SEG_TO_PHYS(end))); 259 physmem = atop(IOM_RAM_SIZE); 260 uvm_page_physload( 261 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 262 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 263 VM_FREELIST_DEFAULT); 264 265 /* Initialize proc0 u-area */ 266 sh_proc0_init(); 267 268 /* Initialize pmap and start to address translation */ 269 pmap_bootstrap(); 270 271# /* 272 * XXX We can't return here, because we change stack pointer. 273 * So jump to return address directly. 274 */ 275 __asm volatile ( 276 "jmp @%0;" 277 "mov %1, r15" 278 :: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank)); 279} 280 281/* 282 * consinit: 283 * initialize the system console. 284 * XXX - shouldn't deal with this initted thing, but then, 285 * it shouldn't be called from init386 either. 286 */ 287void 288consinit(void) 289{ 290 static int initted; 291 292 if (initted) 293 return; 294 initted = 1; 295 296 cninit(); 297} 298 299int 300bus_space_map (bus_space_tag_t t, bus_addr_t addr, bus_size_t size, int flags, bus_space_handle_t *bshp) 301{ 302 303 *bshp = (bus_space_handle_t)addr; 304 305 return 0; 306} 307 308int 309sh_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 310{ 311 312 *nbshp = bsh + offset; 313 return (0); 314} 315 316int 317sh_memio_alloc(t, rstart, rend, size, alignment, boundary, flags, 318 bpap, bshp) 319 bus_space_tag_t t; 320 bus_addr_t rstart, rend; 321 bus_size_t size, alignment, boundary; 322 int flags; 323 bus_addr_t *bpap; 324 bus_space_handle_t *bshp; 325{ 326 *bshp = *bpap = rstart; 327 328 return (0); 329} 330 331void 332sh_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 333{ 334 335} 336 337void 338sh_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 339{ 340 return; 341} 342 343#ifdef SH4_PCMCIA 344 345int 346shpcmcia_memio_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) 347{ 348 int error; 349 struct extent *ex; 350 bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT; 351 352 if (pt != SH3_BUS_SPACE_PCMCIA_IO && 353 pt != SH3_BUS_SPACE_PCMCIA_MEM && 354 pt != SH3_BUS_SPACE_PCMCIA_ATT) { 355 *bshp = (bus_space_handle_t)bpa; 356 357 return 0; 358 } 359 360 ex = iomem_ex; 361 362#if 0 363 /* 364 * Before we go any further, let's make sure that this 365 * region is available. 366 */ 367 error = extent_alloc_region(ex, bpa, size, 368 EX_NOWAIT | EX_MALLOCOK ); 369 if (error){ 370 printf("sh3_pcmcia_memio_map:extent_alloc_region error\n"); 371 return (error); 372 } 373#endif 374 375 /* 376 * For memory space, map the bus physical address to 377 * a kernel virtual address. 378 */ 379 error = shpcmcia_mem_add_mapping(bpa, size, (int)t, bshp ); 380#if 0 381 if (error) { 382 if (extent_free(ex, bpa, size, EX_NOWAIT | EX_MALLOCOK )) { 383 printf("sh3_pcmcia_memio_map: pa 0x%lx, size 0x%lx\n", 384 bpa, size); 385 printf("sh3_pcmcia_memio_map: can't free region\n"); 386 } 387 } 388#endif 389 390 return (error); 391} 392 393int 394shpcmcia_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int type, bus_space_handle_t *bshp) 395{ 396 u_long pa, endpa; 397 vaddr_t va; 398 pt_entry_t *pte; 399 unsigned int m = 0; 400 int io_type = type & ~SH3_BUS_SPACE_PCMCIA_8BIT; 401 402 pa = sh3_trunc_page(bpa); 403 endpa = sh3_round_page(bpa + size); 404 405#ifdef DIAGNOSTIC 406 if (endpa <= pa) 407 panic("sh3_pcmcia_mem_add_mapping: overflow"); 408#endif 409 410 va = uvm_km_alloc(kernel_map, endpa - pa, 0, 411 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 412 if (va == 0){ 413 printf("shpcmcia_add_mapping: nomem \n"); 414 return (ENOMEM); 415 } 416 417 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 418 419#define MODE(t, s) \ 420 (t) & SH3_BUS_SPACE_PCMCIA_8BIT ? \ 421 _PG_PCMCIA_ ## s ## 8 : \ 422 _PG_PCMCIA_ ## s ## 16 423 switch (io_type) { 424 default: 425 panic("unknown pcmcia space."); 426 /* NOTREACHED */ 427 case SH3_BUS_SPACE_PCMCIA_IO: 428 m = MODE(type, IO); 429 break; 430 case SH3_BUS_SPACE_PCMCIA_MEM: 431 m = MODE(type, MEM); 432 break; 433 case SH3_BUS_SPACE_PCMCIA_ATT: 434 m = MODE(type, ATTR); 435 break; 436 } 437#undef MODE 438 439 for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 440 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 441 pte = __pmap_kpte_lookup(va); 442 KDASSERT(pte); 443 *pte |= m; /* PTEA PCMCIA assistant bit */ 444 sh_tlb_update(0, va, *pte); 445 } 446 447 return 0; 448} 449 450void 451shpcmcia_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 452{ 453 struct extent *ex; 454 u_long va, endva; 455 bus_addr_t bpa; 456 bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT; 457 458 if (pt != SH3_BUS_SPACE_PCMCIA_IO && 459 pt != SH3_BUS_SPACE_PCMCIA_MEM && 460 pt != SH3_BUS_SPACE_PCMCIA_ATT) { 461 return ; 462 } 463 464 ex = iomem_ex; 465 466 va = sh3_trunc_page(bsh); 467 endva = sh3_round_page(bsh + size); 468 469#ifdef DIAGNOSTIC 470 if (endva <= va) 471 panic("sh3_pcmcia_memio_unmap: overflow"); 472#endif 473 474 pmap_extract(pmap_kernel(), va, &bpa); 475 bpa += bsh & PGOFSET; 476 477 /* 478 * Free the kernel virtual mapping. 479 */ 480 pmap_kremove(va, endva - va); 481 pmap_update(pmap_kernel()); 482 uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY); 483 484#if 0 485 if (extent_free(ex, bpa, size, 486 EX_NOWAIT | EX_MALLOCOK)) { 487 printf("sh3_pcmcia_memio_unmap: %s 0x%lx, size 0x%lx\n", 488 "pa", bpa, size); 489 printf("sh3_pcmcia_memio_unmap: can't free region\n"); 490 } 491#endif 492} 493 494void 495shpcmcia_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 496{ 497 498 /* sh3_pcmcia_memio_unmap() does all that we need to do. */ 499 shpcmcia_memio_unmap(t, bsh, size); 500} 501 502int 503shpcmcia_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 504{ 505 506 *nbshp = bsh + offset; 507 return (0); 508} 509 510#endif /* SH4_PCMCIA */ 511 512#if !defined(DONT_INIT_BSC) 513/* 514 * InitializeBsc 515 * : BSC(Bus State Controller) 516 */ 517void InitializeBsc(void); 518 519void 520InitializeBsc(void) 521{ 522 523 /* 524 * Drive RAS,CAS in stand by mode and bus release mode 525 * Area0 = Normal memory, Area5,6=Normal(no burst) 526 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory 527 * Area4 = Normal Memory 528 * Area6 = Normal memory 529 */ 530#if defined(SH3) 531 _reg_write_2(SH3_BCR1, BSC_BCR1_VAL); 532#elif defined(SH4) 533 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL); 534#endif 535 536 /* 537 * Bus Width 538 * Area4: Bus width = 16bit 539 * Area6,5 = 16bit 540 * Area1 = 8bit 541 * Area2,3: Bus width = 32bit 542 */ 543 _reg_write_2(SH_(BCR2), BSC_BCR2_VAL); 544 545 /* 546 * Idle cycle number in transition area and read to write 547 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3 548 * Area1 = 3, Area0 = 3 549 */ 550#if defined(SH3) 551 _reg_write_2(SH3_WCR1, BSC_WCR1_VAL); 552#elif defined(SH4) 553 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL); 554#endif 555 556 /* 557 * Wait cycle 558 * Area 6 = 6 559 * Area 5 = 2 560 * Area 4 = 10 561 * Area 3 = 3 562 * Area 2,1 = 3 563 * Area 0 = 6 564 */ 565#if defined(SH3) 566 _reg_write_2(SH3_WCR2, BSC_WCR2_VAL); 567#elif defined(SH4) 568 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL); 569#endif 570 571#if defined(SH4) && defined(BSC_WCR3_VAL) 572 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL); 573#endif 574 575 /* 576 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle, 577 * write pre-charge=1cycle 578 * CAS before RAS refresh RAS assert time = 3 cycle 579 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON 580 * CAS before RAS refresh ON, EDO DRAM 581 */ 582#if defined(SH3) 583 _reg_write_2(SH3_MCR, BSC_MCR_VAL); 584#elif defined(SH4) 585 _reg_write_4(SH4_MCR, BSC_MCR_VAL); 586#endif 587 588#if defined(BSC_SDMR2_VAL) 589 _reg_write_1(BSC_SDMR2_VAL, 0); 590#endif 591 592#if defined(BSC_SDMR3_VAL) 593#if !(defined(COMPUTEXEVB) && defined(SH7709A)) 594 _reg_write_1(BSC_SDMR3_VAL, 0); 595#else 596 _reg_write_2(0x1a000000, 0); /* ADDSET */ 597 _reg_write_1(BSC_SDMR3_VAL, 0); 598 _reg_write_2(0x18000000, 0); /* ADDRST */ 599#endif /* !(COMPUTEXEVB && SH7709A) */ 600#endif /* BSC_SDMR3_VAL */ 601 602 /* 603 * PCMCIA Control Register 604 * OE/WE assert delay 3.5 cycle 605 * OE/WE negate-address delay 3.5 cycle 606 */ 607#ifdef BSC_PCR_VAL 608 _reg_write_2(SH_(PCR), BSC_PCR_VAL); 609#endif 610 611 /* 612 * Refresh Timer Control/Status Register 613 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt 614 * Count Limit = 1024 615 * In following statement, the reason why high byte = 0xa5(a4 in RFCR) 616 * is the rule of SH3 in writing these register. 617 */ 618 _reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL); 619 620 /* 621 * Refresh Timer Counter 622 * Initialize to 0 623 */ 624#ifdef BSC_RTCNT_VAL 625 _reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL); 626#endif 627 628 /* set Refresh Time Constant Register */ 629 _reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL); 630 631 /* init Refresh Count Register */ 632#ifdef BSC_RFCR_VAL 633 _reg_write_2(SH_(RFCR), BSC_RFCR_VAL); 634#endif 635 636 /* 637 * Clock Pulse Generator 638 */ 639 /* Set Clock mode (make internal clock double speed) */ 640 _reg_write_2(SH_(FRQCR), FRQCR_VAL); 641 642 /* 643 * Cache 644 */ 645#ifndef CACHE_DISABLE 646 /* Cache ON */ 647 _reg_write_4(SH_(CCR), 0x1); 648#endif 649} 650#endif /* !DONT_INIT_BSC */ 651 652 653 /* XXX This value depends on physical available memory */ 654#define OSIMAGE_BUF_ADDR (IOM_RAM_BEGIN + 0x00400000) 655 656void 657LoadAndReset(const char *osimage) 658{ 659 void *buf_addr; 660 u_long size; 661 const u_long *src; 662 u_long *dest; 663 u_long csum = 0; 664 u_long csum2 = 0; 665 u_long size2; 666 667 printf("LoadAndReset: copy start\n"); 668 buf_addr = (void *)OSIMAGE_BUF_ADDR; 669 670 size = *(const u_long *)osimage; 671 src = (const u_long *)osimage; 672 dest = buf_addr; 673 674 size = (size + sizeof(u_long) * 2 + 3) >> 2; 675 size2 = size; 676 677 while (size--) { 678 csum += *src; 679 *dest++ = *src++; 680 } 681 682 dest = buf_addr; 683 while (size2--) 684 csum2 += *dest++; 685 686 printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2); 687 printf("start XLoadAndReset\n"); 688 689 /* mask all externel interrupt (XXX) */ 690 691 XLoadAndReset(buf_addr); 692} 693 694void 695intc_intr(int ssr, int spc, int ssp) 696{ 697 struct intc_intrhand *ih; 698 struct clockframe cf; 699 int s, evtcode; 700 701 switch (cpu_product) { 702 case CPU_PRODUCT_7708: 703 case CPU_PRODUCT_7708S: 704 case CPU_PRODUCT_7708R: 705 evtcode = _reg_read_4(SH3_INTEVT); 706 break; 707 case CPU_PRODUCT_7709: 708 case CPU_PRODUCT_7709A: 709 evtcode = _reg_read_4(SH7709_INTEVT2); 710 break; 711 case CPU_PRODUCT_7750: 712 case CPU_PRODUCT_7750S: 713 evtcode = _reg_read_4(SH4_INTEVT); 714 break; 715 default: 716#ifdef DIAGNOSTIC 717 panic("intr_intc: cpu_product %d unhandled!", cpu_product); 718#endif 719 return; 720 } 721 722 ih = EVTCODE_IH(evtcode); 723 KDASSERT(ih->ih_func); 724 /* 725 * On entry, all interrrupts are disabled, 726 * and exception is enabled for P3 access. (kernel stack is P3, 727 * SH3 may or may not cause TLB miss when access stack.) 728 * Enable higher level interrupt here. 729 */ 730 s = _cpu_intr_resume(ih->ih_level); 731 732 switch (evtcode) { 733 default: 734 (*ih->ih_func)(ih->ih_arg); 735 break; 736 case SH_INTEVT_TMU0_TUNI0: 737 cf.spc = spc; 738 cf.ssr = ssr; 739 cf.ssp = ssp; 740 (*ih->ih_func)(&cf); 741 break; 742 case SH_INTEVT_NMI: 743 printf("NMI ignored.\n"); 744 break; 745 } 746} 747 748