machdep.c revision 1.68
1/* $NetBSD: machdep.c,v 1.68 2009/05/16 10:17:38 nonaka Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/*- 34 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * William Jolitz. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 65 */ 66 67#include <sys/cdefs.h> 68__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.68 2009/05/16 10:17:38 nonaka Exp $"); 69 70#include "opt_ddb.h" 71#include "opt_kgdb.h" 72#include "opt_memsize.h" 73#include "opt_initbsc.h" 74 75#include <sys/param.h> 76#include <sys/systm.h> 77#include <sys/kernel.h> 78#include <sys/user.h> 79#include <sys/mount.h> 80#include <sys/reboot.h> 81#include <sys/sysctl.h> 82#include <sys/ksyms.h> 83#include <sys/device.h> 84 85#include <uvm/uvm_extern.h> 86 87#include <dev/cons.h> 88 89#include <sh3/bscreg.h> 90#include <sh3/cpgreg.h> 91#include <sh3/cache_sh3.h> 92#include <sh3/cache_sh4.h> 93#include <sh3/exception.h> 94 95#include <machine/bus.h> 96#include <machine/intr.h> 97 98#ifdef DDB 99#include <machine/db_machdep.h> 100#include <ddb/db_extern.h> 101#endif 102 103#include "ksyms.h" 104 105/* the following is used externally (sysctl_hw) */ 106char machine[] = MACHINE; /* evbsh3 */ 107char machine_arch[] = MACHINE_ARCH; /* sh3eb or sh3el */ 108 109void initSH3(void *); 110void LoadAndReset(const char *); 111void XLoadAndReset(char *); 112 113/* 114 * Machine-dependent startup code 115 * 116 * This is called from main() in kern/main.c. 117 */ 118void 119cpu_startup(void) 120{ 121 122 sh_startup(); 123} 124 125/* 126 * machine dependent system variables. 127 */ 128static int 129sysctl_machdep_loadandreset(SYSCTLFN_ARGS) 130{ 131 const char *osimage; 132 int error; 133 134 error = sysctl_lookup(SYSCTLFN_CALL(__UNCONST(rnode))); 135 if (error || newp == NULL) 136 return (error); 137 138 osimage = (const char *)(*(const u_long *)newp); 139 LoadAndReset(osimage); 140 /* not reach here */ 141 return (0); 142} 143 144SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 145{ 146 147 sysctl_createv(clog, 0, NULL, NULL, 148 CTLFLAG_PERMANENT, 149 CTLTYPE_NODE, "machdep", NULL, 150 NULL, 0, NULL, 0, 151 CTL_MACHDEP, CTL_EOL); 152 153 sysctl_createv(clog, 0, NULL, NULL, 154 CTLFLAG_PERMANENT, 155 CTLTYPE_STRUCT, "console_device", NULL, 156 sysctl_consdev, 0, NULL, sizeof(dev_t), 157 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 158/* 159<atatat> okay...your turn to play. 160<atatat> pick a number. 161<kjk> 98752. 162*/ 163 sysctl_createv(clog, 0, NULL, NULL, 164 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 165 CTLTYPE_INT, "load_and_reset", NULL, 166 sysctl_machdep_loadandreset, 98752, NULL, 0, 167 CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL); 168} 169 170void 171cpu_reboot(int howto, char *bootstr) 172{ 173 static int waittime = -1; 174 175 if (cold) { 176 howto |= RB_HALT; 177 goto haltsys; 178 } 179 180 boothowto = howto; 181 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 182 waittime = 0; 183 vfs_shutdown(); 184 /* 185 * If we've been adjusting the clock, the todr 186 * will be out of synch; adjust it now. 187 */ 188 /* resettodr(); */ 189 } 190 191 /* Disable interrupts. */ 192 splhigh(); 193 194 /* Do a dump if requested. */ 195 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 196 dumpsys(); 197 198haltsys: 199 doshutdownhooks(); 200 201 pmf_system_shutdown(boothowto); 202 203 if (howto & RB_HALT) { 204 printf("\n"); 205 printf("The operating system has halted.\n"); 206 printf("Please press any key to reboot.\n\n"); 207 cngetc(); 208 } 209 210 printf("rebooting...\n"); 211 cpu_reset(); 212 for(;;) 213 ; 214 /*NOTREACHED*/ 215} 216 217void 218initSH3(void *pc) /* XXX return address */ 219{ 220 extern char edata[], end[]; 221 vaddr_t kernend; 222 223 /* Clear bss */ 224 memset(edata, 0, end - edata); 225 226 /* Initilize CPU ops. */ 227#if defined(SH3) && defined(SH4) 228#error "don't define both SH3 and SH4" 229#elif defined(SH3) 230#if defined(SH7708) 231 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708); 232#elif defined(SH7708S) 233 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S); 234#elif defined(SH7708R) 235 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R); 236#elif defined(SH7709) 237 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709); 238#elif defined(SH7709A) 239 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A); 240#elif defined(SH7706) 241 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7706); 242#else 243#error "unsupported SH3 variants" 244#endif 245#elif defined(SH4) 246#if defined(SH7750) 247 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750); 248#elif defined(SH7750S) 249 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S); 250#elif defined(SH7750R) 251 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750R); 252#elif defined(SH7751) 253 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751); 254#elif defined(SH7751R) 255 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751R); 256#else 257#error "unsupported SH4 variants" 258#endif 259#else 260#error "define SH3 or SH4" 261#endif 262 /* Console */ 263 consinit(); 264 265 /* Load memory to UVM */ 266 kernend = atop(round_page(SH3_P1SEG_TO_PHYS(end))); 267 physmem = atop(IOM_RAM_SIZE); 268 uvm_page_physload( 269 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 270 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 271 VM_FREELIST_DEFAULT); 272 273 /* Initialize proc0 u-area */ 274 sh_proc0_init(); 275 276 /* Initialize pmap and start to address translation */ 277 pmap_bootstrap(); 278 279 /* 280 * XXX We can't return here, because we change stack pointer. 281 * So jump to return address directly. 282 */ 283 __asm volatile ( 284 "jmp @%0;" 285 "mov %1, r15" 286 :: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank)); 287} 288 289/* 290 * consinit: 291 * initialize the system console. 292 * XXX - shouldn't deal with this initted thing, but then, 293 * it shouldn't be called from init386 either. 294 */ 295void 296consinit(void) 297{ 298 static int initted; 299 300 if (initted) 301 return; 302 initted = 1; 303 304 cninit(); 305} 306 307int 308bus_space_map (bus_space_tag_t t, bus_addr_t addr, bus_size_t size, int flags, bus_space_handle_t *bshp) 309{ 310 311 *bshp = (bus_space_handle_t)addr; 312 313 return 0; 314} 315 316int 317sh_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 318{ 319 320 *nbshp = bsh + offset; 321 return (0); 322} 323 324int 325sh_memio_alloc(t, rstart, rend, size, alignment, boundary, flags, 326 bpap, bshp) 327 bus_space_tag_t t; 328 bus_addr_t rstart, rend; 329 bus_size_t size, alignment, boundary; 330 int flags; 331 bus_addr_t *bpap; 332 bus_space_handle_t *bshp; 333{ 334 *bshp = *bpap = rstart; 335 336 return (0); 337} 338 339void 340sh_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 341{ 342 343} 344 345void 346sh_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 347{ 348 return; 349} 350 351#ifdef SH4_PCMCIA 352 353int 354shpcmcia_memio_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) 355{ 356 int error; 357 struct extent *ex; 358 bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT; 359 360 if (pt != SH3_BUS_SPACE_PCMCIA_IO && 361 pt != SH3_BUS_SPACE_PCMCIA_MEM && 362 pt != SH3_BUS_SPACE_PCMCIA_ATT) { 363 *bshp = (bus_space_handle_t)bpa; 364 365 return 0; 366 } 367 368 ex = iomem_ex; 369 370#if 0 371 /* 372 * Before we go any further, let's make sure that this 373 * region is available. 374 */ 375 error = extent_alloc_region(ex, bpa, size, 376 EX_NOWAIT | EX_MALLOCOK ); 377 if (error){ 378 printf("sh3_pcmcia_memio_map:extent_alloc_region error\n"); 379 return (error); 380 } 381#endif 382 383 /* 384 * For memory space, map the bus physical address to 385 * a kernel virtual address. 386 */ 387 error = shpcmcia_mem_add_mapping(bpa, size, (int)t, bshp ); 388#if 0 389 if (error) { 390 if (extent_free(ex, bpa, size, EX_NOWAIT | EX_MALLOCOK )) { 391 printf("sh3_pcmcia_memio_map: pa 0x%lx, size 0x%lx\n", 392 bpa, size); 393 printf("sh3_pcmcia_memio_map: can't free region\n"); 394 } 395 } 396#endif 397 398 return (error); 399} 400 401int 402shpcmcia_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int type, bus_space_handle_t *bshp) 403{ 404 u_long pa, endpa; 405 vaddr_t va; 406 pt_entry_t *pte; 407 unsigned int m = 0; 408 int io_type = type & ~SH3_BUS_SPACE_PCMCIA_8BIT; 409 410 pa = sh3_trunc_page(bpa); 411 endpa = sh3_round_page(bpa + size); 412 413#ifdef DIAGNOSTIC 414 if (endpa <= pa) 415 panic("sh3_pcmcia_mem_add_mapping: overflow"); 416#endif 417 418 va = uvm_km_alloc(kernel_map, endpa - pa, 0, 419 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 420 if (va == 0){ 421 printf("shpcmcia_add_mapping: nomem \n"); 422 return (ENOMEM); 423 } 424 425 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 426 427#define MODE(t, s) \ 428 (t) & SH3_BUS_SPACE_PCMCIA_8BIT ? \ 429 _PG_PCMCIA_ ## s ## 8 : \ 430 _PG_PCMCIA_ ## s ## 16 431 switch (io_type) { 432 default: 433 panic("unknown pcmcia space."); 434 /* NOTREACHED */ 435 case SH3_BUS_SPACE_PCMCIA_IO: 436 m = MODE(type, IO); 437 break; 438 case SH3_BUS_SPACE_PCMCIA_MEM: 439 m = MODE(type, MEM); 440 break; 441 case SH3_BUS_SPACE_PCMCIA_ATT: 442 m = MODE(type, ATTR); 443 break; 444 } 445#undef MODE 446 447 for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) { 448 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 449 pte = __pmap_kpte_lookup(va); 450 KDASSERT(pte); 451 *pte |= m; /* PTEA PCMCIA assistant bit */ 452 sh_tlb_update(0, va, *pte); 453 } 454 455 return 0; 456} 457 458void 459shpcmcia_memio_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 460{ 461 struct extent *ex; 462 u_long va, endva; 463 bus_addr_t bpa; 464 bus_space_tag_t pt = t & ~SH3_BUS_SPACE_PCMCIA_8BIT; 465 466 if (pt != SH3_BUS_SPACE_PCMCIA_IO && 467 pt != SH3_BUS_SPACE_PCMCIA_MEM && 468 pt != SH3_BUS_SPACE_PCMCIA_ATT) { 469 return ; 470 } 471 472 ex = iomem_ex; 473 474 va = sh3_trunc_page(bsh); 475 endva = sh3_round_page(bsh + size); 476 477#ifdef DIAGNOSTIC 478 if (endva <= va) 479 panic("sh3_pcmcia_memio_unmap: overflow"); 480#endif 481 482 pmap_extract(pmap_kernel(), va, &bpa); 483 bpa += bsh & PGOFSET; 484 485 /* 486 * Free the kernel virtual mapping. 487 */ 488 pmap_kremove(va, endva - va); 489 pmap_update(pmap_kernel()); 490 uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY); 491 492#if 0 493 if (extent_free(ex, bpa, size, 494 EX_NOWAIT | EX_MALLOCOK)) { 495 printf("sh3_pcmcia_memio_unmap: %s 0x%lx, size 0x%lx\n", 496 "pa", bpa, size); 497 printf("sh3_pcmcia_memio_unmap: can't free region\n"); 498 } 499#endif 500} 501 502void 503shpcmcia_memio_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 504{ 505 506 /* sh3_pcmcia_memio_unmap() does all that we need to do. */ 507 shpcmcia_memio_unmap(t, bsh, size); 508} 509 510int 511shpcmcia_memio_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 512{ 513 514 *nbshp = bsh + offset; 515 return (0); 516} 517 518#endif /* SH4_PCMCIA */ 519 520#if !defined(DONT_INIT_BSC) 521/* 522 * InitializeBsc 523 * : BSC(Bus State Controller) 524 */ 525void InitializeBsc(void); 526 527void 528InitializeBsc(void) 529{ 530 531 /* 532 * Drive RAS,CAS in stand by mode and bus release mode 533 * Area0 = Normal memory, Area5,6=Normal(no burst) 534 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory 535 * Area4 = Normal Memory 536 * Area6 = Normal memory 537 */ 538#if defined(SH3) 539 _reg_write_2(SH3_BCR1, BSC_BCR1_VAL); 540#elif defined(SH4) 541 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL); 542#endif 543 544 /* 545 * Bus Width 546 * Area4: Bus width = 16bit 547 * Area6,5 = 16bit 548 * Area1 = 8bit 549 * Area2,3: Bus width = 32bit 550 */ 551 _reg_write_2(SH_(BCR2), BSC_BCR2_VAL); 552 553 /* 554 * Idle cycle number in transition area and read to write 555 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3 556 * Area1 = 3, Area0 = 3 557 */ 558#if defined(SH3) 559 _reg_write_2(SH3_WCR1, BSC_WCR1_VAL); 560#elif defined(SH4) 561 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL); 562#endif 563 564 /* 565 * Wait cycle 566 * Area 6 = 6 567 * Area 5 = 2 568 * Area 4 = 10 569 * Area 3 = 3 570 * Area 2,1 = 3 571 * Area 0 = 6 572 */ 573#if defined(SH3) 574 _reg_write_2(SH3_WCR2, BSC_WCR2_VAL); 575#elif defined(SH4) 576 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL); 577#endif 578 579#if defined(SH4) && defined(BSC_WCR3_VAL) 580 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL); 581#endif 582 583 /* 584 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle, 585 * write pre-charge=1cycle 586 * CAS before RAS refresh RAS assert time = 3 cycle 587 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON 588 * CAS before RAS refresh ON, EDO DRAM 589 */ 590#if defined(SH3) 591 _reg_write_2(SH3_MCR, BSC_MCR_VAL); 592#elif defined(SH4) 593 _reg_write_4(SH4_MCR, BSC_MCR_VAL); 594#endif 595 596#if defined(BSC_SDMR2_VAL) 597 _reg_write_1(BSC_SDMR2_VAL, 0); 598#endif 599 600#if defined(BSC_SDMR3_VAL) 601#if !(defined(COMPUTEXEVB) && defined(SH7709A)) 602 _reg_write_1(BSC_SDMR3_VAL, 0); 603#else 604 _reg_write_2(0x1a000000, 0); /* ADDSET */ 605 _reg_write_1(BSC_SDMR3_VAL, 0); 606 _reg_write_2(0x18000000, 0); /* ADDRST */ 607#endif /* !(COMPUTEXEVB && SH7709A) */ 608#endif /* BSC_SDMR3_VAL */ 609 610 /* 611 * PCMCIA Control Register 612 * OE/WE assert delay 3.5 cycle 613 * OE/WE negate-address delay 3.5 cycle 614 */ 615#ifdef BSC_PCR_VAL 616 _reg_write_2(SH_(PCR), BSC_PCR_VAL); 617#endif 618 619 /* 620 * Refresh Timer Control/Status Register 621 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt 622 * Count Limit = 1024 623 * In following statement, the reason why high byte = 0xa5(a4 in RFCR) 624 * is the rule of SH3 in writing these register. 625 */ 626 _reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL); 627 628 /* 629 * Refresh Timer Counter 630 * Initialize to 0 631 */ 632#ifdef BSC_RTCNT_VAL 633 _reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL); 634#endif 635 636 /* set Refresh Time Constant Register */ 637 _reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL); 638 639 /* init Refresh Count Register */ 640#ifdef BSC_RFCR_VAL 641 _reg_write_2(SH_(RFCR), BSC_RFCR_VAL); 642#endif 643 644 /* 645 * Clock Pulse Generator 646 */ 647 /* Set Clock mode (make internal clock double speed) */ 648 _reg_write_2(SH_(FRQCR), FRQCR_VAL); 649 650 /* 651 * Cache 652 */ 653#ifndef CACHE_DISABLE 654 /* Cache ON */ 655 _reg_write_4(SH_(CCR), 0x1); 656#endif 657} 658#endif /* !DONT_INIT_BSC */ 659 660 661 /* XXX This value depends on physical available memory */ 662#define OSIMAGE_BUF_ADDR (IOM_RAM_BEGIN + 0x00400000) 663 664void 665LoadAndReset(const char *osimage) 666{ 667 void *buf_addr; 668 u_long size; 669 const u_long *src; 670 u_long *dest; 671 u_long csum = 0; 672 u_long csum2 = 0; 673 u_long size2; 674 675 printf("LoadAndReset: copy start\n"); 676 buf_addr = (void *)OSIMAGE_BUF_ADDR; 677 678 size = *(const u_long *)osimage; 679 src = (const u_long *)osimage; 680 dest = buf_addr; 681 682 size = (size + sizeof(u_long) * 2 + 3) >> 2; 683 size2 = size; 684 685 while (size--) { 686 csum += *src; 687 *dest++ = *src++; 688 } 689 690 dest = buf_addr; 691 while (size2--) 692 csum2 += *dest++; 693 694 printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2); 695 printf("start XLoadAndReset\n"); 696 697 /* mask all externel interrupt (XXX) */ 698 699 XLoadAndReset(buf_addr); 700} 701 702void 703intc_intr(int ssr, int spc, int ssp) 704{ 705 struct intc_intrhand *ih; 706 struct clockframe cf; 707 int s, evtcode; 708 709 switch (cpu_product) { 710 case CPU_PRODUCT_7708: 711 case CPU_PRODUCT_7708S: 712 case CPU_PRODUCT_7708R: 713 evtcode = _reg_read_4(SH3_INTEVT); 714 break; 715 case CPU_PRODUCT_7709: 716 case CPU_PRODUCT_7709A: 717 case CPU_PRODUCT_7706: 718 evtcode = _reg_read_4(SH7709_INTEVT2); 719 break; 720 case CPU_PRODUCT_7750: 721 case CPU_PRODUCT_7750S: 722 case CPU_PRODUCT_7750R: 723 case CPU_PRODUCT_7751: 724 case CPU_PRODUCT_7751R: 725 evtcode = _reg_read_4(SH4_INTEVT); 726 break; 727 default: 728#ifdef DIAGNOSTIC 729 panic("intr_intc: cpu_product %d unhandled!", cpu_product); 730#endif 731 return; 732 } 733 734 ih = EVTCODE_IH(evtcode); 735 KDASSERT(ih->ih_func); 736 /* 737 * On entry, all interrrupts are disabled, 738 * and exception is enabled for P3 access. (kernel stack is P3, 739 * SH3 may or may not cause TLB miss when access stack.) 740 * Enable higher level interrupt here. 741 */ 742 s = _cpu_intr_resume(ih->ih_level); 743 744 switch (evtcode) { 745 default: 746 (*ih->ih_func)(ih->ih_arg); 747 break; 748 case SH_INTEVT_TMU0_TUNI0: 749 cf.spc = spc; 750 cf.ssr = ssr; 751 cf.ssp = ssp; 752 (*ih->ih_func)(&cf); 753 break; 754 case SH_INTEVT_NMI: 755 printf("NMI ignored.\n"); 756 break; 757 } 758} 759 760