machdep.c revision 1.71
1/* $NetBSD: machdep.c,v 1.71 2010/04/06 15:54:30 nonaka Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/*- 34 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * William Jolitz. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 65 */ 66 67#include <sys/cdefs.h> 68__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.71 2010/04/06 15:54:30 nonaka Exp $"); 69 70#include "opt_ddb.h" 71#include "opt_kgdb.h" 72#include "opt_memsize.h" 73#include "opt_initbsc.h" 74#include "opt_kloader.h" 75#include "opt_kloader_kernel_path.h" 76 77#include <sys/param.h> 78#include <sys/systm.h> 79#include <sys/kernel.h> 80#include <sys/mount.h> 81#include <sys/reboot.h> 82#include <sys/sysctl.h> 83#include <sys/ksyms.h> 84#include <sys/device.h> 85 86#include <uvm/uvm_extern.h> 87 88#include <dev/cons.h> 89 90#include <sh3/bscreg.h> 91#include <sh3/cpgreg.h> 92#include <sh3/cache_sh3.h> 93#include <sh3/cache_sh4.h> 94#include <sh3/exception.h> 95 96#include <machine/bus.h> 97#include <machine/intr.h> 98 99#ifdef DDB 100#include <machine/db_machdep.h> 101#include <ddb/db_extern.h> 102#endif 103 104#ifdef KLOADER 105#include <machine/kloader.h> 106#endif 107 108#include "ksyms.h" 109 110/* the following is used externally (sysctl_hw) */ 111char machine[] = MACHINE; /* evbsh3 */ 112char machine_arch[] = MACHINE_ARCH; /* sh3eb or sh3el */ 113 114#ifdef KLOADER 115struct kloader_bootinfo kbootinfo; 116#endif 117 118void initSH3(void *); 119void LoadAndReset(const char *); 120void XLoadAndReset(char *); 121 122/* 123 * Machine-dependent startup code 124 * 125 * This is called from main() in kern/main.c. 126 */ 127void 128cpu_startup(void) 129{ 130 131 sh_startup(); 132} 133 134/* 135 * machine dependent system variables. 136 */ 137static int 138sysctl_machdep_loadandreset(SYSCTLFN_ARGS) 139{ 140 const char *osimage; 141 int error; 142 143 error = sysctl_lookup(SYSCTLFN_CALL(__UNCONST(rnode))); 144 if (error || newp == NULL) 145 return (error); 146 147 osimage = (const char *)(*(const u_long *)newp); 148 LoadAndReset(osimage); 149 /* not reach here */ 150 return (0); 151} 152 153SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") 154{ 155 156 sysctl_createv(clog, 0, NULL, NULL, 157 CTLFLAG_PERMANENT, 158 CTLTYPE_NODE, "machdep", NULL, 159 NULL, 0, NULL, 0, 160 CTL_MACHDEP, CTL_EOL); 161 162 sysctl_createv(clog, 0, NULL, NULL, 163 CTLFLAG_PERMANENT, 164 CTLTYPE_STRUCT, "console_device", NULL, 165 sysctl_consdev, 0, NULL, sizeof(dev_t), 166 CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); 167/* 168<atatat> okay...your turn to play. 169<atatat> pick a number. 170<kjk> 98752. 171*/ 172 sysctl_createv(clog, 0, NULL, NULL, 173 CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, 174 CTLTYPE_INT, "load_and_reset", NULL, 175 sysctl_machdep_loadandreset, 98752, NULL, 0, 176 CTL_MACHDEP, CPU_LOADANDRESET, CTL_EOL); 177} 178 179void 180cpu_reboot(int howto, char *bootstr) 181{ 182 static int waittime = -1; 183 184 if (cold) { 185 howto |= RB_HALT; 186 goto haltsys; 187 } 188 189#ifdef KLOADER 190 if ((howto & RB_HALT) == 0) { 191 if ((howto & RB_STRING) && (bootstr != NULL)) { 192 kloader_reboot_setup(bootstr); 193 } 194#ifdef KLOADER_KERNEL_PATH 195 else { 196 kloader_reboot_setup(KLOADER_KERNEL_PATH); 197 } 198#endif 199 } 200#endif 201 202 boothowto = howto; 203 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 204 waittime = 0; 205 vfs_shutdown(); 206 /* 207 * If we've been adjusting the clock, the todr 208 * will be out of synch; adjust it now. 209 */ 210 /* resettodr(); */ 211 } 212 213 /* Disable interrupts. */ 214 splhigh(); 215 216 /* Do a dump if requested. */ 217 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 218 dumpsys(); 219 220haltsys: 221 doshutdownhooks(); 222 223 pmf_system_shutdown(boothowto); 224 225 if (howto & RB_HALT) { 226 printf("\n"); 227 printf("The operating system has halted.\n"); 228 printf("Please press any key to reboot.\n\n"); 229 cngetc(); 230 } 231#ifdef KLOADER 232 else { 233 delay(1 * 1000 * 1000); 234 kloader_reboot(); 235 printf("\n"); 236 printf("Failed to load a new kernel.\n"); 237 printf("Please press any key to reboot.\n\n"); 238 cngetc(); 239 } 240#endif 241 242 printf("rebooting...\n"); 243 cpu_reset(); 244 for(;;) 245 continue; 246 /*NOTREACHED*/ 247} 248 249void 250initSH3(void *pc) /* XXX return address */ 251{ 252 extern char edata[], end[]; 253 vaddr_t kernend; 254 255 /* Clear bss */ 256 memset(edata, 0, end - edata); 257 258 /* Initilize CPU ops. */ 259#if defined(SH3) && defined(SH4) 260#error "don't define both SH3 and SH4" 261#elif defined(SH3) 262#if defined(SH7708) 263 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708); 264#elif defined(SH7708S) 265 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708S); 266#elif defined(SH7708R) 267 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7708R); 268#elif defined(SH7709) 269 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709); 270#elif defined(SH7709A) 271 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7709A); 272#elif defined(SH7706) 273 sh_cpu_init(CPU_ARCH_SH3, CPU_PRODUCT_7706); 274#else 275#error "unsupported SH3 variants" 276#endif 277#elif defined(SH4) 278#if defined(SH7750) 279 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750); 280#elif defined(SH7750S) 281 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750S); 282#elif defined(SH7750R) 283 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7750R); 284#elif defined(SH7751) 285 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751); 286#elif defined(SH7751R) 287 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751R); 288#else 289#error "unsupported SH4 variants" 290#endif 291#else 292#error "define SH3 or SH4" 293#endif 294 /* Console */ 295 consinit(); 296 297#ifdef KLOADER 298 /* copy boot parameter for kloader */ 299 kloader_bootinfo_set(&kbootinfo, 0, NULL, NULL, true); 300#endif 301 302 /* Load memory to UVM */ 303 kernend = atop(round_page(SH3_P1SEG_TO_PHYS(end))); 304 physmem = atop(IOM_RAM_SIZE); 305 uvm_page_physload( 306 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 307 kernend, atop(IOM_RAM_BEGIN + IOM_RAM_SIZE), 308 VM_FREELIST_DEFAULT); 309 310 /* Initialize proc0 u-area */ 311 sh_proc0_init(); 312 313 /* Initialize pmap and start to address translation */ 314 pmap_bootstrap(); 315 316 /* 317 * XXX We can't return here, because we change stack pointer. 318 * So jump to return address directly. 319 */ 320 __asm volatile ( 321 "jmp @%0;" 322 "mov %1, r15" 323 :: "r"(pc),"r"(lwp0.l_md.md_pcb->pcb_sf.sf_r7_bank)); 324} 325 326/* 327 * consinit: 328 * initialize the system console. 329 * XXX - shouldn't deal with this initted thing, but then, 330 * it shouldn't be called from init386 either. 331 */ 332void 333consinit(void) 334{ 335 static int initted; 336 337 if (initted) 338 return; 339 initted = 1; 340 341 cninit(); 342} 343 344#if !defined(DONT_INIT_BSC) 345/* 346 * InitializeBsc 347 * : BSC(Bus State Controller) 348 */ 349void InitializeBsc(void); 350 351void 352InitializeBsc(void) 353{ 354 355 /* 356 * Drive RAS,CAS in stand by mode and bus release mode 357 * Area0 = Normal memory, Area5,6=Normal(no burst) 358 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory 359 * Area4 = Normal Memory 360 * Area6 = Normal memory 361 */ 362#if defined(SH3) 363 _reg_write_2(SH3_BCR1, BSC_BCR1_VAL); 364#elif defined(SH4) 365 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL); 366#endif 367 368 /* 369 * Bus Width 370 * Area4: Bus width = 16bit 371 * Area6,5 = 16bit 372 * Area1 = 8bit 373 * Area2,3: Bus width = 32bit 374 */ 375 _reg_write_2(SH_(BCR2), BSC_BCR2_VAL); 376 377 /* 378 * Idle cycle number in transition area and read to write 379 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3 380 * Area1 = 3, Area0 = 3 381 */ 382#if defined(SH3) 383 _reg_write_2(SH3_WCR1, BSC_WCR1_VAL); 384#elif defined(SH4) 385 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL); 386#endif 387 388 /* 389 * Wait cycle 390 * Area 6 = 6 391 * Area 5 = 2 392 * Area 4 = 10 393 * Area 3 = 3 394 * Area 2,1 = 3 395 * Area 0 = 6 396 */ 397#if defined(SH3) 398 _reg_write_2(SH3_WCR2, BSC_WCR2_VAL); 399#elif defined(SH4) 400 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL); 401#endif 402 403#if defined(SH4) && defined(BSC_WCR3_VAL) 404 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL); 405#endif 406 407 /* 408 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle, 409 * write pre-charge=1cycle 410 * CAS before RAS refresh RAS assert time = 3 cycle 411 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON 412 * CAS before RAS refresh ON, EDO DRAM 413 */ 414#if defined(SH3) 415 _reg_write_2(SH3_MCR, BSC_MCR_VAL); 416#elif defined(SH4) 417 _reg_write_4(SH4_MCR, BSC_MCR_VAL); 418#endif 419 420#if defined(BSC_SDMR2_VAL) 421 _reg_write_1(BSC_SDMR2_VAL, 0); 422#endif 423 424#if defined(BSC_SDMR3_VAL) 425#if !(defined(COMPUTEXEVB) && defined(SH7709A)) 426 _reg_write_1(BSC_SDMR3_VAL, 0); 427#else 428 _reg_write_2(0x1a000000, 0); /* ADDSET */ 429 _reg_write_1(BSC_SDMR3_VAL, 0); 430 _reg_write_2(0x18000000, 0); /* ADDRST */ 431#endif /* !(COMPUTEXEVB && SH7709A) */ 432#endif /* BSC_SDMR3_VAL */ 433 434 /* 435 * PCMCIA Control Register 436 * OE/WE assert delay 3.5 cycle 437 * OE/WE negate-address delay 3.5 cycle 438 */ 439#ifdef BSC_PCR_VAL 440 _reg_write_2(SH_(PCR), BSC_PCR_VAL); 441#endif 442 443 /* 444 * Refresh Timer Control/Status Register 445 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt 446 * Count Limit = 1024 447 * In following statement, the reason why high byte = 0xa5(a4 in RFCR) 448 * is the rule of SH3 in writing these register. 449 */ 450 _reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL); 451 452 /* 453 * Refresh Timer Counter 454 * Initialize to 0 455 */ 456#ifdef BSC_RTCNT_VAL 457 _reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL); 458#endif 459 460 /* set Refresh Time Constant Register */ 461 _reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL); 462 463 /* init Refresh Count Register */ 464#ifdef BSC_RFCR_VAL 465 _reg_write_2(SH_(RFCR), BSC_RFCR_VAL); 466#endif 467 468 /* 469 * Clock Pulse Generator 470 */ 471 /* Set Clock mode (make internal clock double speed) */ 472 _reg_write_2(SH_(FRQCR), FRQCR_VAL); 473 474 /* 475 * Cache 476 */ 477#ifndef CACHE_DISABLE 478 /* Cache ON */ 479 _reg_write_4(SH_(CCR), 0x1); 480#endif 481} 482#endif /* !DONT_INIT_BSC */ 483 484 485 /* XXX This value depends on physical available memory */ 486#define OSIMAGE_BUF_ADDR (IOM_RAM_BEGIN + 0x00400000) 487 488void 489LoadAndReset(const char *osimage) 490{ 491 void *buf_addr; 492 u_long size; 493 const u_long *src; 494 u_long *dest; 495 u_long csum = 0; 496 u_long csum2 = 0; 497 u_long size2; 498 499 printf("LoadAndReset: copy start\n"); 500 buf_addr = (void *)OSIMAGE_BUF_ADDR; 501 502 size = *(const u_long *)osimage; 503 src = (const u_long *)osimage; 504 dest = buf_addr; 505 506 size = (size + sizeof(u_long) * 2 + 3) >> 2; 507 size2 = size; 508 509 while (size--) { 510 csum += *src; 511 *dest++ = *src++; 512 } 513 514 dest = buf_addr; 515 while (size2--) 516 csum2 += *dest++; 517 518 printf("LoadAndReset: copy end[%lx,%lx]\n", csum, csum2); 519 printf("start XLoadAndReset\n"); 520 521 /* mask all externel interrupt (XXX) */ 522 523 XLoadAndReset(buf_addr); 524} 525 526void 527intc_intr(int ssr, int spc, int ssp) 528{ 529 struct intc_intrhand *ih; 530 struct clockframe cf; 531 int s, evtcode; 532 533 switch (cpu_product) { 534 case CPU_PRODUCT_7708: 535 case CPU_PRODUCT_7708S: 536 case CPU_PRODUCT_7708R: 537 evtcode = _reg_read_4(SH3_INTEVT); 538 break; 539 case CPU_PRODUCT_7709: 540 case CPU_PRODUCT_7709A: 541 case CPU_PRODUCT_7706: 542 evtcode = _reg_read_4(SH7709_INTEVT2); 543 break; 544 case CPU_PRODUCT_7750: 545 case CPU_PRODUCT_7750S: 546 case CPU_PRODUCT_7750R: 547 case CPU_PRODUCT_7751: 548 case CPU_PRODUCT_7751R: 549 evtcode = _reg_read_4(SH4_INTEVT); 550 break; 551 default: 552#ifdef DIAGNOSTIC 553 panic("intr_intc: cpu_product %d unhandled!", cpu_product); 554#endif 555 return; 556 } 557 558 ih = EVTCODE_IH(evtcode); 559 KDASSERT(ih->ih_func); 560 /* 561 * On entry, all interrrupts are disabled, 562 * and exception is enabled for P3 access. (kernel stack is P3, 563 * SH3 may or may not cause TLB miss when access stack.) 564 * Enable higher level interrupt here. 565 */ 566 s = _cpu_intr_resume(ih->ih_level); 567 568 switch (evtcode) { 569 default: 570 (*ih->ih_func)(ih->ih_arg); 571 break; 572 case SH_INTEVT_TMU0_TUNI0: 573 cf.spc = spc; 574 cf.ssr = ssr; 575 cf.ssp = ssp; 576 (*ih->ih_func)(&cf); 577 break; 578 case SH_INTEVT_NMI: 579 printf("NMI ignored.\n"); 580 break; 581 } 582} 583