zs.c revision 1.2
1 /* $NetBSD: zs.c,v 1.2 2006/11/03 03:04:53 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.2 2006/11/03 03:04:53 tsutsui Exp $"); 48 49 #include "opt_ddb.h" 50 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/tty.h> 54 #include <sys/systm.h> 55 56 #include <machine/z8530var.h> 57 #include <dev/ic/z8530reg.h> 58 59 #include "ioconf.h" 60 61 /* console status for consinit() */ 62 static struct zs_chanstate zs_conscs_store; 63 struct zs_chanstate *zs_conscs = &zs_conscs_store; 64 void *zs_consaddr; 65 66 /* 67 * Some warts needed by z8530tty.c - 68 * The default parity REALLY needs to be the same as the PROM uses, 69 * or you can not see messages done with printf during boot-up... 70 */ 71 int zs_def_cflag = (CREAD | CS8 | HUPCL); 72 73 int 74 zs_print(void *aux, const char *name) 75 { 76 struct zsc_attach_args *args = aux; 77 78 if (name != NULL) 79 aprint_normal("%s: ", name); 80 81 if (args->channel != -1) 82 aprint_normal(" channel %d", args->channel); 83 84 return UNCONF; 85 } 86 87 int 88 zshard(void *arg) 89 { 90 struct zsc_softc *zsc; 91 int rval; 92 93 zsc = arg; 94 rval = zsc_intr_hard(zsc); 95 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq) 96 softintr_schedule(zsc->zsc_si); 97 98 return rval; 99 } 100 101 /* 102 * Compute the current baud rate given a ZS channel. 103 */ 104 int 105 zs_get_speed(struct zs_chanstate *cs) 106 { 107 int tconst; 108 109 tconst = zs_read_reg(cs, 12); 110 tconst |= zs_read_reg(cs, 13) << 8; 111 return TCONST_TO_BPS(cs->cs_brg_clk, tconst); 112 } 113 114 /* 115 * MD functions for setting the baud rate and control modes. 116 */ 117 int 118 zs_set_speed(struct zs_chanstate *cs, int bps) 119 { 120 int tconst, real_bps; 121 122 if (bps == 0) 123 return 0; 124 125 #ifdef DIAGNOSTIC 126 if (cs->cs_brg_clk == 0) 127 panic("zs_set_speed"); 128 #endif 129 130 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 131 if (tconst < 0) 132 return EINVAL; 133 134 /* Convert back to make sure we can do it. */ 135 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 136 137 /* XXX - Allow some tolerance here? */ 138 if (real_bps != bps) 139 return EINVAL; 140 141 cs->cs_preg[12] = tconst; 142 cs->cs_preg[13] = tconst >> 8; 143 144 /* Caller will stuff the pending registers. */ 145 return 0; 146 } 147 148 int 149 zs_set_modes(struct zs_chanstate *cs, int cflag) 150 { 151 int s; 152 153 /* 154 * Output hardware flow control on the chip is horrendous: 155 * if carrier detect drops, the receiver is disabled, and if 156 * CTS drops, the transmitter is stoped IN MID CHARACTER! 157 * Therefore, NEVER set the HFC bit, and instead use the 158 * status interrupt to detect CTS changes. 159 */ 160 s = splserial(); 161 cs->cs_rr0_pps = 0; 162 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 163 cs->cs_rr0_dcd = 0; 164 if ((cflag & MDMBUF) == 0) 165 cs->cs_rr0_pps = ZSRR0_DCD; 166 } else 167 cs->cs_rr0_dcd = ZSRR0_DCD; 168 if ((cflag & CRTSCTS) != 0) { 169 cs->cs_wr5_dtr = ZSWR5_DTR; 170 cs->cs_wr5_rts = ZSWR5_RTS; 171 cs->cs_rr0_cts = ZSRR0_CTS; 172 } else if ((cflag & MDMBUF) != 0) { 173 cs->cs_wr5_dtr = 0; 174 cs->cs_wr5_rts = ZSWR5_DTR; 175 cs->cs_rr0_cts = ZSRR0_DCD; 176 } else { 177 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 178 cs->cs_wr5_rts = 0; 179 cs->cs_rr0_cts = 0; 180 } 181 splx(s); 182 183 /* Caller will stuff the pending registers. */ 184 return 0; 185 } 186 187 /* 188 * Read or write the chip with suitable delays. 189 */ 190 uint8_t 191 zs_read_reg(struct zs_chanstate *cs, uint8_t reg) 192 { 193 uint8_t val; 194 195 *cs->cs_reg_csr = reg; 196 197 val = *cs->cs_reg_csr; 198 199 return val; 200 } 201 202 void 203 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val) 204 { 205 206 *cs->cs_reg_csr = reg; 207 208 *cs->cs_reg_csr = val; 209 210 } 211 212 uint8_t 213 zs_read_csr(struct zs_chanstate *cs) 214 { 215 uint8_t val; 216 217 val = *cs->cs_reg_csr; 218 219 return val; 220 } 221 222 void 223 zs_write_csr(struct zs_chanstate *cs, uint8_t val) 224 { 225 226 *cs->cs_reg_csr = val; 227 228 } 229 230 uint8_t 231 zs_read_data(struct zs_chanstate *cs) 232 { 233 uint8_t val; 234 235 val = *cs->cs_reg_data; 236 237 return val; 238 } 239 240 void 241 zs_write_data(struct zs_chanstate *cs, uint8_t val) 242 { 243 244 *cs->cs_reg_data = val; 245 } 246 247 void 248 zs_abort(struct zs_chanstate *cs) 249 { 250 251 #ifdef DDB 252 Debugger(); 253 #endif 254 } 255 256 /* 257 * Polled input char. 258 */ 259 int 260 zs_getc(void *arg) 261 { 262 struct zs_chanstate *cs = arg; 263 int s, c, rr0; 264 265 s = splhigh(); 266 /* Wait for a character to arrive. */ 267 do { 268 rr0 = *cs->cs_reg_csr; 269 ZS_DELAY(); 270 } while ((rr0 & ZSRR0_RX_READY) == 0); 271 272 c = *cs->cs_reg_data; 273 ZS_DELAY(); 274 splx(s); 275 276 /* 277 * This could be used by the kd driver to read scan codes, 278 * so don't translate '\r' ==> '\n' here... 279 */ 280 return c; 281 } 282 283 /* 284 * Polled output char. 285 */ 286 void 287 zs_putc(void *arg, int c) 288 { 289 struct zs_chanstate *cs = arg; 290 int s, rr0; 291 292 s = splhigh(); 293 /* Wait for transmitter to become ready. */ 294 do { 295 rr0 = *cs->cs_reg_csr; 296 ZS_DELAY(); 297 } while ((rr0 & ZSRR0_TX_READY) == 0); 298 299 *cs->cs_reg_data = c; 300 ZS_DELAY(); 301 splx(s); 302 } 303 304 int 305 zscngetc(dev_t dev) 306 { 307 308 return zs_getc((void *)zs_conscs); 309 } 310 311 void 312 zscnputc(dev_t dev, int c) 313 { 314 315 zs_putc((void *)zs_conscs, c); 316 } 317
Indexes created Sun Sep 28 07:09:56 GMT 2025