sbd_tr2.h revision 1.1
1 /* $NetBSD: sbd_tr2.h,v 1.1 2005/12/29 15:20:09 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _SBD_TR2_PRIVATE 40 #error "Don't inlucde this file except for TR2 implemetation" 41 #endif /* !_SBD_TR2_PRIVATE */ 42 43 #ifndef _EWS4800MIPS_SBD_TR2_H_ 44 #define _EWS4800MIPS_SBD_TR2_H_ 45 /* 46 * EWS4800/350 (TR2) specific system board definition 47 */ 48 49 /* ROM */ 50 #define TR2_ROM_FONT_ADDR 0xbfc0ec00 51 #define TR2_ROM_FONT_SIZE ((0x7f - 0x20) * 24 * sizeof(int16_t)) 52 53 #define TR2_ROM_KEYMAP_NORMAL ((uint8_t *)0xbfc12d6c) 54 #define TR2_ROM_KEYMAP_SHIFTED ((uint8_t *)0xbfc12dec) 55 #define TR2_ROM_KEYMAP_CONTROL ((uint8_t *)0xbfc12e6c) 56 #define TR2_ROM_KEYMAP_CAPSLOCK ((uint8_t *)0xbfc12eec) 57 #define TR2_ROM_KBD_TYPE 0xbfc0fe04 /* [d0 00 00 01] used by kbmskbreset. */ 58 59 #define TR2_ROM_PUTC ((void (*)(int, int, int))0xbfc04f28) 60 #define TR2_ROM_GETC ((int (*)(void))0xbfc11fa0) 61 62 /* System board I/O devices */ 63 #define TR2_PICNIC_ADDR 0xbb000000 64 #define TR2_KBMS_ADDR 0xbb010000 65 #define TR2_SIO_ADDR 0xbb011000 66 #define TR2_NVSRAM_ADDR 0xbb020000 67 #define TR2_NVSRAM_SIZE 0x00004000 68 #define TR2_FDC_ADDR 0xbb030000 69 #define TR2_LPT_ADDR 0xbb040000 70 #define TR2_SCSI_ADDR 0xbb050000 71 #define TR2_ETHER_ADDR 0xbb060000 72 #define TR2_MEMC_ADDR 0xbfa00000 73 #define TR2_NABI_ADDR 0xbfb00000 74 #define TR2_GAFB_ADDR 0xf0000000 75 #define TR2_GAFB_SIZE 0x08000000 76 #define TR2_GACTRL_ADDR 0xf5f00000 77 #define TR2_GACTRL_SIZE 0x1000 78 79 #define SOFTRESET_REG ((volatile uint32_t *)0xbfb00000) 80 #define POWEROFF_REG ((volatile uint8_t *)0xbb004000) 81 #define UPS_STATUS_REG ((volatile uint8_t *)0xbb004008) /* mask 0xffffffbb, 0x4 */ 82 83 #define LED_TF_REG ((volatile uint8_t *)0xbb006000) /* 0/1 (Red)*/ 84 #define TF_ERROR_CODE ((volatile uint8_t *)0xbb006004) /* 1-255 */ 85 86 #define BUZZER_REG ((volatile uint8_t *)0xbb007000) 87 88 /* NABI */ 89 #define NABI0_CTRL_REG ((volatile uint32_t *)0xbfb00000) 90 #define NABI1_CTRL_REG ((volatile uint32_t *)0xbfb00004) 91 #define NABI2_CTRL_REG ((volatile uint32_t *)0xbfb00008) 92 #define NABI0_INTR_REG ((volatile uint32_t *)0xbfb00010) 93 #define NABI1_INTR_REG ((volatile uint32_t *)0xbfb00018) /* VME */ 94 #define NABI2_INTR_REG ((volatile uint32_t *)0xbfb0001c) 95 96 /* 97 * PICNIC (interrupt controller) 98 */ 99 #define PICNIC_INT0_STATUS_REG ((volatile uint8_t *)0xbb000000) 100 #define PICNIC_INT2_STATUS_REG ((volatile uint8_t *)0xbb000004) 101 #define PICNIC_INT4_STATUS_REG ((volatile uint8_t *)0xbb000008) 102 #define PICNIC_INT5_STATUS_REG ((volatile uint8_t *)0xbb000010) 103 #define PICNIC_NMI_REG ((volatile uint8_t *)0xbb000014) 104 105 #define PICNIC_INT0_MASK_REG ((volatile uint8_t *)0xbb001000) 106 #define PICNIC_INT2_MASK_REG ((volatile uint8_t *)0xbb001004) 107 #define PICNIC_INT4_MASK_REG ((volatile uint8_t *)0xbb001008) 108 #define PICNIC_INT5_MASK_REG ((volatile uint8_t *)0xbb001010) 109 /* Interrupt source */ 110 #define PICNIC_INT_FDDLPT 0x80 111 #define PICNIC_INT_ETHER 0x40 112 #define PICNIC_INT_SCSI 0x20 113 #define PICNIC_INT_SERIAL 0x04 114 #define PICNIC_INT_KBMS 0x01 115 #define PICNIC_INT_CLOCK 0x01 116 /* 117 * 76543210 118 * ||| | +-- keyboard, mouse 119 * ||| +-----serial 120 * ||+--------SCSI 121 * |+---------ether 122 * +----------FDC, printer 123 *0xbb00 UX IPL mips int 124 * 1000 0x80 0x00 7 INT0 125 * 1004 0x60 0x00 65 INT2 126 * 1008 0x05 0x00 2 0 INT4 127 * 1010 0x01 0x01 0 Clock INT5 128 */ 129 130 /* SIO0 Z85C30 */ 131 #define KBD_STATUS ((volatile uint8_t *)0xbb010000) 132 #define KBD_DATA ((volatile uint8_t *)0xbb010004) 133 #define MOUSE_STATUS ((volatile uint8_t *)0xbb010008) 134 #define MOUSE_DATA ((volatile uint8_t *)0xbb01000c) 135 /* SIO1 Z85C30 */ 136 #define SIOA_STATUS ((volatile uint8_t *)0xbb011008) 137 #define SIOA_RDATA ((volatile uint8_t *)0xbb01100c) 138 #define SIOB_STATUS ((volatile uint8_t *)0xbb011000) 139 #define SIOB_RDATA ((volatile uint8_t *)0xbb011004) 140 141 /* ETHER i82589 */ 142 /* read operation invokes channel attention. */ 143 #define ETHER_SETADDR_REG ((volatile uint32_t *)0xbb060000) 144 145 /* DCC (DMA controler. Parallel port and FDD use this.) */ 146 struct DCC { 147 uint32_t addr; /* DMA address */ 148 uint32_t cnt; /* transfer count */ 149 uint32_t ctrl; /* DMA status/command */ 150 uint32_t drm; 151 } __attribute__((__packed__)); 152 153 /* FDD uPD72065 (80track ready) */ 154 #define FDC_DMA ((volatile struct DCC *)0xbb030000) 155 #define FDC_STATUS ((volatile uint8_t *)0xbb030010) 156 #define FDC_DATA ((volatile uint8_t *)0xbb030014) 157 158 /* LPT */ 159 #define LPT_DMA (((volatile struct DCC *)0xbb040000) 160 #define LPT_COUNT ((volatile uint8_t *)0xbb040010) 161 #define LPT_STRR ((volatile uint8_t *)0xbb040011) 162 163 /* NVSRAM MK48T08B-15 (word aligned byte access) */ 164 /* 0, 4, 8, c */ 165 #define NVSRAM_SIGNATURE 0xbb020000 166 /* 10, 14 18 1c */ 167 #define NVSRAM_MACHINEID 0xbb020010 168 #define NVSRAM_ETHERADDR ((uint8_t *)0xbb021008) 169 /* 2000, 2004, 2008, 200c */ 170 #define NVSRAM_CDUMP_ADDR ((uint8_t *)0xbb022000) 171 #define NVSRAM_DUMPDEV_1XXX 0xbb022020 172 #define NVSRAM_DUMPDEV_2XXX 0xbb022040 173 /* 2050, 2054, 2058, 205c */ 174 #define NVSRAM_TF_SCRATCH_ADDR 0xbb022050 175 #if 0 176 /* kbd */ 177 #define NVSRAM_KBD??? 0xbb0220a0 /* 0x90 */ 178 #endif 179 #define NVSRAM_TF_TESTDATA1 0xbb023000 180 #define NVSRAM_TF_TESTDATA2 0xbb023004 181 #define NVSRAM_KEYMAP ((uint8_t *)0xbb023014) /* scratch */ 182 #define NVSRAM_TF_PROGRESS ((uint8_t *)0xbb02301c) 183 #define NVSRAM_BEV_ROM 32 /* Exception from ROM routine */ 184 185 #define NVSRAM_KBDCONNECT ((uint8_t *)0xbb023010) 186 #define HAS_KBD() (*NVSRAM_KBDCONNECT != 255) 187 #define NVSRAM_CONSTYPE ((uint8_t *)0xbb023020) 188 #define IS_FBCONS() (*NVSRAM_CONSTYPE == 0) 189 #define NVSRAM_GA 0xbb023008 190 #define HAS_GA 0 191 #define NVSRAM_TF_RESULT_HI 0xbb023024 192 #define NVSRAM_TF_RESULT_LO 0xbb023028 193 #define NVSRAM_IPLMODE ((uint8_t *)0xbb02302c) 194 /* 195 * 0: Normal mode 196 * 1: ERROR continue mode 197 * 2: Details mode 198 * 3: LOOP mode 199 */ 200 #define NVSRAM_BOOTDEV ((uint8_t *)0xbb023030) 201 #define NVSRAM_BOOTUNIT ((uint8_t *)0xbb023034) 202 203 /* V1 is memory area information */ 204 #define NVSRAM_1STBOOT_ARG_V1_3 ((uint8_t *)0xbb023048) /* 24-31 */ 205 #define NVSRAM_1STBOOT_ARG_V1_2 ((uint8_t *)0xbb02304c) /* 16-23 */ 206 #define NVSRAM_1STBOOT_ARG_V1_1 ((uint8_t *)0xbb023050) /* 8 -15 */ 207 #define NVSRAM_1STBOOT_ARG_V1_0 ((uint8_t *)0xbb023054) /* 0 - 7 */ 208 #define NVSRAM_1STBOOT_ARG_V0 ((uint8_t *)0xbb023058) 209 210 #define NVSRAM_SIMM_3_2 ((uint8_t *)0xbb023050) 211 #define NVSRAM_SIMM_1_0 ((uint8_t *)0xbb023054) 212 #define SIMM_16M 0x1 213 #define SIMM_32M 0x2 214 215 #define NVSRAM_RTCADDR ((uint8_t *)0xbb027fe0) 216 217 /* Graphic adapter */ 218 #include <machine/gareg.h> 219 220 /* 221 * VME (350/380) 222 */ 223 #define VME_ADDR 0xf8000000 224 #define VME_32_ADDR 0xf8000000 225 #define VME_32_SIZE 0x07000000 226 #define VME_BUFFER_ADDR 0xff000000 227 #define VME_BUFFER_SIZE 0x00800000 228 #define VME_24_ADDR 0xff800000 229 #define VME_24_SIZE 0x007f0000 230 #define VME_SHORTIO_ADDR 0xffff0000 231 #define VME_SHORTIO_SIZE 0x00010000 232 233 #endif /* !_EWS4800MIPS_SBD_TR2_H_ */ 234
Indexes created Tue Sep 30 11:09:46 GMT 2025