zs_sbdio.c revision 1.8
1 /* $NetBSD: zs_sbdio.c,v 1.8 2008/03/29 08:14:41 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: zs_sbdio.c,v 1.8 2008/03/29 08:14:41 tsutsui Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/tty.h> 53 #include <sys/conf.h> 54 #include <sys/intr.h> 55 56 #include <dev/cons.h> 57 #include <dev/ic/z8530reg.h> 58 59 #include <machine/sbdiovar.h> 60 #include <machine/z8530var.h> 61 62 #define ZS_DEFSPEED 9600 63 #define PCLK (9600 * 512) /* 4.915200MHz */ 64 65 /* The layout of this is hardware-dependent (padding, order). */ 66 struct zschan { 67 volatile uint8_t zc_csr; /* ctrl, status, and indirect access */ 68 uint8_t padding1[3]; 69 volatile uint8_t zc_data; /* data */ 70 uint8_t padding2[3]; 71 } __attribute__((__packed__)); 72 73 struct zsdevice { 74 /* Yes, they are backwards. */ 75 struct zschan zs_chan_b; 76 struct zschan zs_chan_a; 77 } __attribute__((__packed__)); 78 79 static uint8_t zs_init_reg[16] = { 80 0, /* 0: CMD (reset, etc.) */ 81 0, /* 1: No interrupts yet. */ 82 0, /* 2: IVECT EWS-UX don't set this. */ 83 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 84 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 85 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 86 0, /* 6: TXSYNC/SYNCLO */ 87 0, /* 7: RXSYNC/SYNCHI */ 88 0, /* 8: alias for data port */ 89 ZSWR9_MASTER_IE, 90 0, /* 10: Misc. TX/RX control bits */ 91 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 92 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */ 93 0, /*13: BAUDHI (default=9600) */ 94 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 95 ZSWR15_BREAK_IE, 96 }; 97 98 static int zs_sbdio_match(device_t, cfdata_t, void *); 99 static void zs_sbdio_attach(device_t, device_t, void *); 100 101 CFATTACH_DECL(zsc_sbdio, sizeof(struct zsc_softc), 102 zs_sbdio_match, zs_sbdio_attach, NULL, NULL); 103 104 int 105 zs_sbdio_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct sbdio_attach_args *sa = aux; 108 109 return strcmp(sa->sa_name, "zsc") ? 0 : 1; 110 } 111 112 void 113 zs_sbdio_attach(device_t parent, device_t self, void *aux) 114 { 115 struct zsc_softc *zsc = (void *)self; 116 struct sbdio_attach_args *sa = aux; 117 struct zsc_attach_args zsc_args; 118 struct zschan *zc; 119 struct zs_chanstate *cs; 120 struct zsdevice *zs_addr; 121 int s, zs_unit, channel; 122 123 aprint_normal("\n"); 124 125 zs_unit = device_unit(self); 126 zs_addr = (void *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1); 127 zsc->zsc_flags = sa->sa_flags; 128 129 /* 130 * Initialize software state for each channel. 131 */ 132 for (channel = 0; channel < 2; channel++) { 133 zsc_args.channel = channel; 134 zsc_args.hwflags = 0; 135 cs = &zsc->zsc_cs_store[channel]; 136 zsc->zsc_cs[channel] = cs; 137 138 cs->cs_channel = channel; 139 cs->cs_private = NULL; 140 cs->cs_ops = &zsops_null; 141 142 if (channel == 0) 143 zc = &zs_addr->zs_chan_a; 144 else 145 zc = &zs_addr->zs_chan_b; 146 147 if (zc == zs_consaddr) { 148 memcpy(cs, zs_conscs, sizeof(struct zs_chanstate)); 149 zs_conscs = cs; 150 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 151 } else { 152 cs->cs_reg_csr = &zc->zc_csr; 153 cs->cs_reg_data = &zc->zc_data; 154 memcpy(cs->cs_creg, zs_init_reg, 16); 155 memcpy(cs->cs_preg, zs_init_reg, 16); 156 cs->cs_defspeed = ZS_DEFSPEED; 157 zsc_args.hwflags = 0; 158 } 159 160 zs_lock_init(cs); 161 cs->cs_brg_clk = PCLK / 16; 162 cs->cs_defcflag = zs_def_cflag; 163 164 /* Make these correspond to cs_defcflag (-crtscts) */ 165 cs->cs_rr0_dcd = ZSRR0_DCD; 166 cs->cs_rr0_cts = 0; 167 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 168 cs->cs_wr5_rts = 0; 169 170 /* 171 * Clear the master interrupt enable. 172 * The INTENA is common to both channels, 173 * so just do it on the A channel. 174 */ 175 if (channel == 0) { 176 zs_write_reg(cs, 9, 0); 177 } 178 179 /* 180 * Look for a child driver for this channel. 181 * The child attach will setup the hardware. 182 */ 183 if (!config_found(self, (void *)&zsc_args, zs_print)) { 184 /* No sub-driver. Just reset it. */ 185 uint8_t reset = (channel == 0) ? 186 ZSWR9_A_RESET : ZSWR9_B_RESET; 187 s = splhigh(); 188 zs_write_reg(cs, 9, reset); 189 splx(s); 190 } 191 } 192 193 zsc->zsc_si = softint_establish(SOFTINT_SERIAL, 194 (void (*)(void *))zsc_intr_soft, zsc); 195 intr_establish(sa->sa_irq, zshard, zsc); 196 197 /* 198 * Set the master interrupt enable and interrupt vector. 199 * (common to both channels, do it on A) 200 */ 201 cs = zsc->zsc_cs[0]; 202 s = splhigh(); 203 /* interrupt vector */ 204 zs_write_reg(cs, 2, zs_init_reg[2]); 205 /* master interrupt control (enable) */ 206 zs_write_reg(cs, 9, zs_init_reg[9]); 207 splx(s); 208 } 209 210 /* 211 * console stuff 212 */ 213 214 static void zs_sbdio_cnprobe(struct consdev *); 215 static void zs_sbdio_cninit(struct consdev *); 216 217 struct consdev consdev_zs_sbdio = { 218 zs_sbdio_cnprobe, 219 zs_sbdio_cninit, 220 zscngetc, 221 zscnputc, 222 nullcnpollc, 223 NULL, 224 NULL, 225 NULL, 226 NODEV, 227 CN_DEAD 228 }; 229 230 static void 231 zs_sbdio_cnprobe(struct consdev *cn) 232 { 233 234 /* not used */ 235 } 236 237 static void 238 zs_sbdio_cninit(struct consdev *cn) 239 { 240 struct zs_chanstate *cs; 241 struct zschan *zc; 242 243 zc = zs_consaddr; 244 cs = zs_conscs; 245 246 /* Setup temporary chanstate. */ 247 cs->cs_reg_csr = &zc->zc_csr; 248 cs->cs_reg_data = &zc->zc_data; 249 250 /* Initialize the pending registers. */ 251 memcpy(cs->cs_preg, zs_init_reg, 16); 252 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 253 254 cs->cs_brg_clk = PCLK / 16; 255 cs->cs_defspeed = ZS_DEFSPEED; 256 zs_set_speed(cs, ZS_DEFSPEED); 257 258 /* Clear the master interrupt enable. */ 259 zs_write_reg(cs, 9, 0); 260 261 /* Reset the whole SCC chip. */ 262 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 263 264 /* Copy "pending" to "current" and H/W */ 265 zs_loadchannelregs(cs); 266 } 267
Indexes created Thu Oct 02 14:10:14 GMT 2025