dcm.c revision 1.47.8.2 1 1.47.8.2 nathanw /* $NetBSD: dcm.c,v 1.47.8.2 2002/01/08 00:24:32 nathanw Exp $ */
2 1.47.8.2 nathanw
3 1.47.8.2 nathanw /*-
4 1.47.8.2 nathanw * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
5 1.47.8.2 nathanw * All rights reserved.
6 1.47.8.2 nathanw *
7 1.47.8.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.47.8.2 nathanw * by Jason R. Thorpe.
9 1.47.8.2 nathanw *
10 1.47.8.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.47.8.2 nathanw * modification, are permitted provided that the following conditions
12 1.47.8.2 nathanw * are met:
13 1.47.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.47.8.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.47.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.47.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.47.8.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.47.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.47.8.2 nathanw * must display the following acknowledgement:
20 1.47.8.2 nathanw * This product includes software developed by the NetBSD
21 1.47.8.2 nathanw * Foundation, Inc. and its contributors.
22 1.47.8.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.47.8.2 nathanw * contributors may be used to endorse or promote products derived
24 1.47.8.2 nathanw * from this software without specific prior written permission.
25 1.47.8.2 nathanw *
26 1.47.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.47.8.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.47.8.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.47.8.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.47.8.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.47.8.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.47.8.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.47.8.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.47.8.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.47.8.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.47.8.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.47.8.2 nathanw */
38 1.47.8.2 nathanw
39 1.47.8.2 nathanw /*
40 1.47.8.2 nathanw * Copyright (c) 1988 University of Utah.
41 1.47.8.2 nathanw * Copyright (c) 1982, 1986, 1990, 1993
42 1.47.8.2 nathanw * The Regents of the University of California. All rights reserved.
43 1.47.8.2 nathanw *
44 1.47.8.2 nathanw * This code is derived from software contributed to Berkeley by
45 1.47.8.2 nathanw * the Systems Programming Group of the University of Utah Computer
46 1.47.8.2 nathanw * Science Department.
47 1.47.8.2 nathanw *
48 1.47.8.2 nathanw * Redistribution and use in source and binary forms, with or without
49 1.47.8.2 nathanw * modification, are permitted provided that the following conditions
50 1.47.8.2 nathanw * are met:
51 1.47.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
52 1.47.8.2 nathanw * notice, this list of conditions and the following disclaimer.
53 1.47.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
54 1.47.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
55 1.47.8.2 nathanw * documentation and/or other materials provided with the distribution.
56 1.47.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
57 1.47.8.2 nathanw * must display the following acknowledgement:
58 1.47.8.2 nathanw * This product includes software developed by the University of
59 1.47.8.2 nathanw * California, Berkeley and its contributors.
60 1.47.8.2 nathanw * 4. Neither the name of the University nor the names of its contributors
61 1.47.8.2 nathanw * may be used to endorse or promote products derived from this software
62 1.47.8.2 nathanw * without specific prior written permission.
63 1.47.8.2 nathanw *
64 1.47.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
65 1.47.8.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 1.47.8.2 nathanw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 1.47.8.2 nathanw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
68 1.47.8.2 nathanw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 1.47.8.2 nathanw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 1.47.8.2 nathanw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 1.47.8.2 nathanw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 1.47.8.2 nathanw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 1.47.8.2 nathanw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 1.47.8.2 nathanw * SUCH DAMAGE.
75 1.47.8.2 nathanw *
76 1.47.8.2 nathanw * from Utah: $Hdr: dcm.c 1.29 92/01/21$
77 1.47.8.2 nathanw *
78 1.47.8.2 nathanw * @(#)dcm.c 8.4 (Berkeley) 1/12/94
79 1.47.8.2 nathanw */
80 1.47.8.2 nathanw
81 1.47.8.2 nathanw /*
82 1.47.8.2 nathanw * TODO:
83 1.47.8.2 nathanw * Timeouts
84 1.47.8.2 nathanw * Test console support.
85 1.47.8.2 nathanw */
86 1.47.8.2 nathanw
87 1.47.8.2 nathanw /*
88 1.47.8.2 nathanw * 98642/MUX
89 1.47.8.2 nathanw */
90 1.47.8.2 nathanw
91 1.47.8.2 nathanw #include "opt_kgdb.h"
92 1.47.8.2 nathanw
93 1.47.8.2 nathanw #include <sys/param.h>
94 1.47.8.2 nathanw #include <sys/systm.h>
95 1.47.8.2 nathanw #include <sys/ioctl.h>
96 1.47.8.2 nathanw #include <sys/proc.h>
97 1.47.8.2 nathanw #include <sys/tty.h>
98 1.47.8.2 nathanw #include <sys/conf.h>
99 1.47.8.2 nathanw #include <sys/file.h>
100 1.47.8.2 nathanw #include <sys/uio.h>
101 1.47.8.2 nathanw #include <sys/kernel.h>
102 1.47.8.2 nathanw #include <sys/syslog.h>
103 1.47.8.2 nathanw #include <sys/time.h>
104 1.47.8.2 nathanw #include <sys/device.h>
105 1.47.8.2 nathanw
106 1.47.8.2 nathanw #include <machine/autoconf.h>
107 1.47.8.2 nathanw #include <machine/cpu.h>
108 1.47.8.2 nathanw #include <machine/intr.h>
109 1.47.8.2 nathanw
110 1.47.8.2 nathanw #include <dev/cons.h>
111 1.47.8.2 nathanw
112 1.47.8.2 nathanw #include <hp300/dev/dioreg.h>
113 1.47.8.2 nathanw #include <hp300/dev/diovar.h>
114 1.47.8.2 nathanw #include <hp300/dev/diodevs.h>
115 1.47.8.2 nathanw #include <hp300/dev/dcmreg.h>
116 1.47.8.2 nathanw
117 1.47.8.2 nathanw #ifndef DEFAULT_BAUD_RATE
118 1.47.8.2 nathanw #define DEFAULT_BAUD_RATE 9600
119 1.47.8.2 nathanw #endif
120 1.47.8.2 nathanw
121 1.47.8.2 nathanw struct speedtab dcmspeedtab[] = {
122 1.47.8.2 nathanw { 0, BR_0 },
123 1.47.8.2 nathanw { 50, BR_50 },
124 1.47.8.2 nathanw { 75, BR_75 },
125 1.47.8.2 nathanw { 110, BR_110 },
126 1.47.8.2 nathanw { 134, BR_134 },
127 1.47.8.2 nathanw { 150, BR_150 },
128 1.47.8.2 nathanw { 300, BR_300 },
129 1.47.8.2 nathanw { 600, BR_600 },
130 1.47.8.2 nathanw { 1200, BR_1200 },
131 1.47.8.2 nathanw { 1800, BR_1800 },
132 1.47.8.2 nathanw { 2400, BR_2400 },
133 1.47.8.2 nathanw { 4800, BR_4800 },
134 1.47.8.2 nathanw { 9600, BR_9600 },
135 1.47.8.2 nathanw { 19200, BR_19200 },
136 1.47.8.2 nathanw { 38400, BR_38400 },
137 1.47.8.2 nathanw { -1, -1 },
138 1.47.8.2 nathanw };
139 1.47.8.2 nathanw
140 1.47.8.2 nathanw /* u-sec per character based on baudrate (assumes 1 start/8 data/1 stop bit) */
141 1.47.8.2 nathanw #define DCM_USPERCH(s) (10000000 / (s))
142 1.47.8.2 nathanw
143 1.47.8.2 nathanw /*
144 1.47.8.2 nathanw * Per board interrupt scheme. 16.7ms is the polling interrupt rate
145 1.47.8.2 nathanw * (16.7ms is about 550 baud, 38.4k is 72 chars in 16.7ms).
146 1.47.8.2 nathanw */
147 1.47.8.2 nathanw #define DIS_TIMER 0
148 1.47.8.2 nathanw #define DIS_PERCHAR 1
149 1.47.8.2 nathanw #define DIS_RESET 2
150 1.47.8.2 nathanw
151 1.47.8.2 nathanw int dcmistype = -1; /* -1 == dynamic, 0 == timer, 1 == perchar */
152 1.47.8.2 nathanw int dcminterval = 5; /* interval (secs) between checks */
153 1.47.8.2 nathanw struct dcmischeme {
154 1.47.8.2 nathanw int dis_perchar; /* non-zero if interrupting per char */
155 1.47.8.2 nathanw long dis_time; /* last time examined */
156 1.47.8.2 nathanw int dis_intr; /* recv interrupts during last interval */
157 1.47.8.2 nathanw int dis_char; /* characters read during last interval */
158 1.47.8.2 nathanw };
159 1.47.8.2 nathanw
160 1.47.8.2 nathanw #ifdef KGDB
161 1.47.8.2 nathanw /*
162 1.47.8.2 nathanw * Kernel GDB support
163 1.47.8.2 nathanw */
164 1.47.8.2 nathanw #include <machine/remote-sl.h>
165 1.47.8.2 nathanw
166 1.47.8.2 nathanw extern dev_t kgdb_dev;
167 1.47.8.2 nathanw extern int kgdb_rate;
168 1.47.8.2 nathanw extern int kgdb_debug_init;
169 1.47.8.2 nathanw #endif
170 1.47.8.2 nathanw
171 1.47.8.2 nathanw /* #define DCMSTATS */
172 1.47.8.2 nathanw
173 1.47.8.2 nathanw #ifdef DEBUG
174 1.47.8.2 nathanw int dcmdebug = 0x0;
175 1.47.8.2 nathanw #define DDB_SIOERR 0x01
176 1.47.8.2 nathanw #define DDB_PARAM 0x02
177 1.47.8.2 nathanw #define DDB_INPUT 0x04
178 1.47.8.2 nathanw #define DDB_OUTPUT 0x08
179 1.47.8.2 nathanw #define DDB_INTR 0x10
180 1.47.8.2 nathanw #define DDB_IOCTL 0x20
181 1.47.8.2 nathanw #define DDB_INTSCHM 0x40
182 1.47.8.2 nathanw #define DDB_MODEM 0x80
183 1.47.8.2 nathanw #define DDB_OPENCLOSE 0x100
184 1.47.8.2 nathanw #endif
185 1.47.8.2 nathanw
186 1.47.8.2 nathanw #ifdef DCMSTATS
187 1.47.8.2 nathanw #define DCMRBSIZE 94
188 1.47.8.2 nathanw #define DCMXBSIZE 24
189 1.47.8.2 nathanw
190 1.47.8.2 nathanw struct dcmstats {
191 1.47.8.2 nathanw long xints; /* # of xmit ints */
192 1.47.8.2 nathanw long xchars; /* # of xmit chars */
193 1.47.8.2 nathanw long xempty; /* times outq is empty in dcmstart */
194 1.47.8.2 nathanw long xrestarts; /* times completed while xmitting */
195 1.47.8.2 nathanw long rints; /* # of recv ints */
196 1.47.8.2 nathanw long rchars; /* # of recv chars */
197 1.47.8.2 nathanw long xsilo[DCMXBSIZE+2]; /* times this many chars xmit on one int */
198 1.47.8.2 nathanw long rsilo[DCMRBSIZE+2]; /* times this many chars read on one int */
199 1.47.8.2 nathanw };
200 1.47.8.2 nathanw #endif
201 1.47.8.2 nathanw
202 1.47.8.2 nathanw #define DCMUNIT(x) (minor(x) & 0x7ffff)
203 1.47.8.2 nathanw #define DCMDIALOUT(x) (minor(x) & 0x80000)
204 1.47.8.2 nathanw #define DCMBOARD(x) (((x) >> 2) & 0x3f)
205 1.47.8.2 nathanw #define DCMPORT(x) ((x) & 3)
206 1.47.8.2 nathanw
207 1.47.8.2 nathanw /*
208 1.47.8.2 nathanw * Conversion from "HP DCE" to almost-normal DCE: on the 638 8-port mux,
209 1.47.8.2 nathanw * the distribution panel uses "HP DCE" conventions. If requested via
210 1.47.8.2 nathanw * the device flags, we swap the inputs to something closer to normal DCE,
211 1.47.8.2 nathanw * allowing a straight-through cable to a DTE or a reversed cable
212 1.47.8.2 nathanw * to a DCE (reversing 2-3, 4-5, 8-20 and leaving 6 unconnected;
213 1.47.8.2 nathanw * this gets "DCD" on pin 20 and "CTS" on 4, but doesn't connect
214 1.47.8.2 nathanw * DSR or make RTS work, though). The following gives the full
215 1.47.8.2 nathanw * details of a cable from this mux panel to a modem:
216 1.47.8.2 nathanw *
217 1.47.8.2 nathanw * HP modem
218 1.47.8.2 nathanw * name pin pin name
219 1.47.8.2 nathanw * HP inputs:
220 1.47.8.2 nathanw * "Rx" 2 3 Tx
221 1.47.8.2 nathanw * CTS 4 5 CTS (only needed for CCTS_OFLOW)
222 1.47.8.2 nathanw * DCD 20 8 DCD
223 1.47.8.2 nathanw * "DSR" 9 6 DSR (unneeded)
224 1.47.8.2 nathanw * RI 22 22 RI (unneeded)
225 1.47.8.2 nathanw *
226 1.47.8.2 nathanw * HP outputs:
227 1.47.8.2 nathanw * "Tx" 3 2 Rx
228 1.47.8.2 nathanw * "DTR" 6 not connected
229 1.47.8.2 nathanw * "RTS" 8 20 DTR
230 1.47.8.2 nathanw * "SR" 23 4 RTS (often not needed)
231 1.47.8.2 nathanw */
232 1.47.8.2 nathanw #define hp2dce_in(ibits) (iconv[(ibits) & 0xf])
233 1.47.8.2 nathanw static char iconv[16] = {
234 1.47.8.2 nathanw 0, MI_DM, MI_CTS, MI_CTS|MI_DM,
235 1.47.8.2 nathanw MI_CD, MI_CD|MI_DM, MI_CD|MI_CTS, MI_CD|MI_CTS|MI_DM,
236 1.47.8.2 nathanw MI_RI, MI_RI|MI_DM, MI_RI|MI_CTS, MI_RI|MI_CTS|MI_DM,
237 1.47.8.2 nathanw MI_RI|MI_CD, MI_RI|MI_CD|MI_DM, MI_RI|MI_CD|MI_CTS,
238 1.47.8.2 nathanw MI_RI|MI_CD|MI_CTS|MI_DM
239 1.47.8.2 nathanw };
240 1.47.8.2 nathanw
241 1.47.8.2 nathanw /*
242 1.47.8.2 nathanw * Note that 8-port boards appear as 2 4-port boards at consecutive
243 1.47.8.2 nathanw * select codes.
244 1.47.8.2 nathanw */
245 1.47.8.2 nathanw #define NDCMPORT 4
246 1.47.8.2 nathanw
247 1.47.8.2 nathanw struct dcm_softc {
248 1.47.8.2 nathanw struct device sc_dev; /* generic device glue */
249 1.47.8.2 nathanw struct dcmdevice *sc_dcm; /* pointer to hardware */
250 1.47.8.2 nathanw struct tty *sc_tty[NDCMPORT]; /* our tty instances */
251 1.47.8.2 nathanw struct modemreg *sc_modem[NDCMPORT]; /* modem control */
252 1.47.8.2 nathanw char sc_mcndlast[NDCMPORT]; /* XXX last modem status for port */
253 1.47.8.2 nathanw short sc_softCAR; /* mask of ports with soft-carrier */
254 1.47.8.2 nathanw struct dcmischeme sc_scheme; /* interrupt scheme for board */
255 1.47.8.2 nathanw
256 1.47.8.2 nathanw /*
257 1.47.8.2 nathanw * Mask of soft-carrier bits in config flags.
258 1.47.8.2 nathanw */
259 1.47.8.2 nathanw #define DCM_SOFTCAR 0x0000000f
260 1.47.8.2 nathanw
261 1.47.8.2 nathanw int sc_flags; /* misc. configuration info */
262 1.47.8.2 nathanw
263 1.47.8.2 nathanw /*
264 1.47.8.2 nathanw * Bits for sc_flags
265 1.47.8.2 nathanw */
266 1.47.8.2 nathanw #define DCM_ACTIVE 0x00000001 /* indicates board is alive */
267 1.47.8.2 nathanw #define DCM_ISCONSOLE 0x00000002 /* indicates board is console */
268 1.47.8.2 nathanw #define DCM_STDDCE 0x00000010 /* re-map DCE to standard */
269 1.47.8.2 nathanw #define DCM_FLAGMASK (DCM_STDDCE) /* mask of valid bits in config flags */
270 1.47.8.2 nathanw
271 1.47.8.2 nathanw #ifdef DCMSTATS
272 1.47.8.2 nathanw struct dcmstats sc_stats; /* metrics gathering */
273 1.47.8.2 nathanw #endif
274 1.47.8.2 nathanw };
275 1.47.8.2 nathanw
276 1.47.8.2 nathanw cdev_decl(dcm);
277 1.47.8.2 nathanw
278 1.47.8.2 nathanw int dcmintr __P((void *));
279 1.47.8.2 nathanw void dcmpint __P((struct dcm_softc *, int, int));
280 1.47.8.2 nathanw void dcmrint __P((struct dcm_softc *));
281 1.47.8.2 nathanw void dcmreadbuf __P((struct dcm_softc *, int));
282 1.47.8.2 nathanw void dcmxint __P((struct dcm_softc *, int));
283 1.47.8.2 nathanw void dcmmint __P((struct dcm_softc *, int, int));
284 1.47.8.2 nathanw
285 1.47.8.2 nathanw int dcmparam __P((struct tty *, struct termios *));
286 1.47.8.2 nathanw void dcmstart __P((struct tty *));
287 1.47.8.2 nathanw void dcmstop __P((struct tty *, int));
288 1.47.8.2 nathanw int dcmmctl __P((dev_t, int, int));
289 1.47.8.2 nathanw void dcmsetischeme __P((int, int));
290 1.47.8.2 nathanw void dcminit __P((struct dcmdevice *, int, int));
291 1.47.8.2 nathanw
292 1.47.8.2 nathanw int dcmselftest __P((struct dcm_softc *));
293 1.47.8.2 nathanw
294 1.47.8.2 nathanw int dcmcnattach __P((bus_space_tag_t, bus_addr_t, int));
295 1.47.8.2 nathanw int dcmcngetc __P((dev_t));
296 1.47.8.2 nathanw void dcmcnputc __P((dev_t, int));
297 1.47.8.2 nathanw
298 1.47.8.2 nathanw int dcmmatch __P((struct device *, struct cfdata *, void *));
299 1.47.8.2 nathanw void dcmattach __P((struct device *, struct device *, void *));
300 1.47.8.2 nathanw
301 1.47.8.2 nathanw struct cfattach dcm_ca = {
302 1.47.8.2 nathanw sizeof(struct dcm_softc), dcmmatch, dcmattach
303 1.47.8.2 nathanw };
304 1.47.8.2 nathanw
305 1.47.8.2 nathanw /*
306 1.47.8.2 nathanw * Stuff for DCM console support. This could probably be done a little
307 1.47.8.2 nathanw * better.
308 1.47.8.2 nathanw */
309 1.47.8.2 nathanw static struct dcmdevice *dcm_cn = NULL; /* pointer to hardware */
310 1.47.8.2 nathanw static int dcmconsinit; /* has been initialized */
311 1.47.8.2 nathanw /* static int dcm_lastcnpri = CN_DEAD; */ /* XXX last priority */
312 1.47.8.2 nathanw
313 1.47.8.2 nathanw static struct consdev dcm_cons = {
314 1.47.8.2 nathanw NULL, NULL, dcmcngetc, dcmcnputc, nullcnpollc, NULL, NODEV, CN_REMOTE
315 1.47.8.2 nathanw };
316 1.47.8.2 nathanw int dcmconscode;
317 1.47.8.2 nathanw int dcmdefaultrate = DEFAULT_BAUD_RATE;
318 1.47.8.2 nathanw int dcmconbrdbusy = 0;
319 1.47.8.2 nathanw int dcmmajor;
320 1.47.8.2 nathanw
321 1.47.8.2 nathanw extern struct cfdriver dcm_cd;
322 1.47.8.2 nathanw
323 1.47.8.2 nathanw int
324 1.47.8.2 nathanw dcmmatch(parent, match, aux)
325 1.47.8.2 nathanw struct device *parent;
326 1.47.8.2 nathanw struct cfdata *match;
327 1.47.8.2 nathanw void *aux;
328 1.47.8.2 nathanw {
329 1.47.8.2 nathanw struct dio_attach_args *da = aux;
330 1.47.8.2 nathanw
331 1.47.8.2 nathanw switch (da->da_id) {
332 1.47.8.2 nathanw case DIO_DEVICE_ID_DCM:
333 1.47.8.2 nathanw case DIO_DEVICE_ID_DCMREM:
334 1.47.8.2 nathanw return (1);
335 1.47.8.2 nathanw }
336 1.47.8.2 nathanw
337 1.47.8.2 nathanw return (0);
338 1.47.8.2 nathanw }
339 1.47.8.2 nathanw
340 1.47.8.2 nathanw void
341 1.47.8.2 nathanw dcmattach(parent, self, aux)
342 1.47.8.2 nathanw struct device *parent, *self;
343 1.47.8.2 nathanw void *aux;
344 1.47.8.2 nathanw {
345 1.47.8.2 nathanw struct dcm_softc *sc = (struct dcm_softc *)self;
346 1.47.8.2 nathanw struct dio_attach_args *da = aux;
347 1.47.8.2 nathanw struct dcmdevice *dcm;
348 1.47.8.2 nathanw int brd = self->dv_unit;
349 1.47.8.2 nathanw int scode = da->da_scode;
350 1.47.8.2 nathanw int i, mbits, code, ipl;
351 1.47.8.2 nathanw
352 1.47.8.2 nathanw sc->sc_flags = 0;
353 1.47.8.2 nathanw
354 1.47.8.2 nathanw if (scode == dcmconscode) {
355 1.47.8.2 nathanw dcm = dcm_cn;
356 1.47.8.2 nathanw sc->sc_flags |= DCM_ISCONSOLE;
357 1.47.8.2 nathanw
358 1.47.8.2 nathanw /*
359 1.47.8.2 nathanw * We didn't know which unit this would be during
360 1.47.8.2 nathanw * the console probe, so we have to fixup cn_dev here.
361 1.47.8.2 nathanw * Note that we always assume port 1 on the board.
362 1.47.8.2 nathanw */
363 1.47.8.2 nathanw cn_tab->cn_dev = makedev(dcmmajor, (brd << 2) | DCMCONSPORT);
364 1.47.8.2 nathanw } else {
365 1.47.8.2 nathanw dcm = (struct dcmdevice *)iomap(dio_scodetopa(da->da_scode),
366 1.47.8.2 nathanw da->da_size);
367 1.47.8.2 nathanw if (dcm == NULL) {
368 1.47.8.2 nathanw printf("\n%s: can't map registers\n",
369 1.47.8.2 nathanw sc->sc_dev.dv_xname);
370 1.47.8.2 nathanw return;
371 1.47.8.2 nathanw }
372 1.47.8.2 nathanw }
373 1.47.8.2 nathanw
374 1.47.8.2 nathanw sc->sc_dcm = dcm;
375 1.47.8.2 nathanw
376 1.47.8.2 nathanw ipl = DIO_IPL(dcm);
377 1.47.8.2 nathanw printf(" ipl %d", ipl);
378 1.47.8.2 nathanw
379 1.47.8.2 nathanw /*
380 1.47.8.2 nathanw * XXX someone _should_ fix this; the self test screws
381 1.47.8.2 nathanw * autoconfig messages.
382 1.47.8.2 nathanw */
383 1.47.8.2 nathanw if ((sc->sc_flags & DCM_ISCONSOLE) && dcmselftest(sc)) {
384 1.47.8.2 nathanw printf("\n%s: self-test failed\n", sc->sc_dev.dv_xname);
385 1.47.8.2 nathanw return;
386 1.47.8.2 nathanw }
387 1.47.8.2 nathanw
388 1.47.8.2 nathanw /* Extract configuration info from flags. */
389 1.47.8.2 nathanw sc->sc_softCAR = self->dv_cfdata->cf_flags & DCM_SOFTCAR;
390 1.47.8.2 nathanw sc->sc_flags |= self->dv_cfdata->cf_flags & DCM_FLAGMASK;
391 1.47.8.2 nathanw
392 1.47.8.2 nathanw /* Mark our unit as configured. */
393 1.47.8.2 nathanw sc->sc_flags |= DCM_ACTIVE;
394 1.47.8.2 nathanw
395 1.47.8.2 nathanw /* Establish the interrupt handler. */
396 1.47.8.2 nathanw (void) dio_intr_establish(dcmintr, sc, ipl, IPL_TTY);
397 1.47.8.2 nathanw
398 1.47.8.2 nathanw if (dcmistype == DIS_TIMER)
399 1.47.8.2 nathanw dcmsetischeme(brd, DIS_RESET|DIS_TIMER);
400 1.47.8.2 nathanw else
401 1.47.8.2 nathanw dcmsetischeme(brd, DIS_RESET|DIS_PERCHAR);
402 1.47.8.2 nathanw
403 1.47.8.2 nathanw /* load pointers to modem control */
404 1.47.8.2 nathanw sc->sc_modem[0] = &dcm->dcm_modem0;
405 1.47.8.2 nathanw sc->sc_modem[1] = &dcm->dcm_modem1;
406 1.47.8.2 nathanw sc->sc_modem[2] = &dcm->dcm_modem2;
407 1.47.8.2 nathanw sc->sc_modem[3] = &dcm->dcm_modem3;
408 1.47.8.2 nathanw
409 1.47.8.2 nathanw /* set DCD (modem) and CTS (flow control) on all ports */
410 1.47.8.2 nathanw if (sc->sc_flags & DCM_STDDCE)
411 1.47.8.2 nathanw mbits = hp2dce_in(MI_CD|MI_CTS);
412 1.47.8.2 nathanw else
413 1.47.8.2 nathanw mbits = MI_CD|MI_CTS;
414 1.47.8.2 nathanw
415 1.47.8.2 nathanw for (i = 0; i < NDCMPORT; i++)
416 1.47.8.2 nathanw sc->sc_modem[i]->mdmmsk = mbits;
417 1.47.8.2 nathanw
418 1.47.8.2 nathanw /*
419 1.47.8.2 nathanw * Get current state of mdmin register on all ports, so that
420 1.47.8.2 nathanw * deltas will work properly.
421 1.47.8.2 nathanw */
422 1.47.8.2 nathanw for (i = 0; i < NDCMPORT; i++) {
423 1.47.8.2 nathanw code = sc->sc_modem[i]->mdmin;
424 1.47.8.2 nathanw if (sc->sc_flags & DCM_STDDCE)
425 1.47.8.2 nathanw code = hp2dce_in(code);
426 1.47.8.2 nathanw sc->sc_mcndlast[i] = code;
427 1.47.8.2 nathanw }
428 1.47.8.2 nathanw
429 1.47.8.2 nathanw dcm->dcm_ic = IC_IE; /* turn all interrupts on */
430 1.47.8.2 nathanw
431 1.47.8.2 nathanw /*
432 1.47.8.2 nathanw * Need to reset baud rate, etc. of next print so reset dcmconsinit.
433 1.47.8.2 nathanw * Also make sure console is always "hardwired"
434 1.47.8.2 nathanw */
435 1.47.8.2 nathanw if (sc->sc_flags & DCM_ISCONSOLE) {
436 1.47.8.2 nathanw dcmconsinit = 0;
437 1.47.8.2 nathanw sc->sc_softCAR |= (1 << DCMCONSPORT);
438 1.47.8.2 nathanw printf(": console on port %d\n", DCMCONSPORT);
439 1.47.8.2 nathanw } else
440 1.47.8.2 nathanw printf("\n");
441 1.47.8.2 nathanw
442 1.47.8.2 nathanw #ifdef KGDB
443 1.47.8.2 nathanw if (major(kgdb_dev) == dcmmajor &&
444 1.47.8.2 nathanw DCMBOARD(DCMUNIT(kgdb_dev)) == brd) {
445 1.47.8.2 nathanw if (dcmconsole == DCMUNIT(kgdb_dev)) /* XXX fixme */
446 1.47.8.2 nathanw kgdb_dev = NODEV; /* can't debug over console port */
447 1.47.8.2 nathanw #ifndef KGDB_CHEAT
448 1.47.8.2 nathanw /*
449 1.47.8.2 nathanw * The following could potentially be replaced
450 1.47.8.2 nathanw * by the corresponding code in dcmcnprobe.
451 1.47.8.2 nathanw */
452 1.47.8.2 nathanw else {
453 1.47.8.2 nathanw dcminit(dcm, DCMPORT(DCMUNIT(kgdb_dev)),
454 1.47.8.2 nathanw kgdb_rate);
455 1.47.8.2 nathanw if (kgdb_debug_init) {
456 1.47.8.2 nathanw printf("%s port %d: ", sc->sc_dev.dv_xname,
457 1.47.8.2 nathanw DCMPORT(DCMUNIT(kgdb_dev)));
458 1.47.8.2 nathanw kgdb_connect(1);
459 1.47.8.2 nathanw } else
460 1.47.8.2 nathanw printf("%s port %d: kgdb enabled\n",
461 1.47.8.2 nathanw sc->sc_dev.dv_xname,
462 1.47.8.2 nathanw DCMPORT(DCMUNIT(kgdb_dev)));
463 1.47.8.2 nathanw }
464 1.47.8.2 nathanw /* end could be replaced */
465 1.47.8.2 nathanw #endif /* KGDB_CHEAT */
466 1.47.8.2 nathanw }
467 1.47.8.2 nathanw #endif /* KGDB */
468 1.47.8.2 nathanw }
469 1.47.8.2 nathanw
470 1.47.8.2 nathanw /* ARGSUSED */
471 1.47.8.2 nathanw int
472 1.47.8.2 nathanw dcmopen(dev, flag, mode, p)
473 1.47.8.2 nathanw dev_t dev;
474 1.47.8.2 nathanw int flag, mode;
475 1.47.8.2 nathanw struct proc *p;
476 1.47.8.2 nathanw {
477 1.47.8.2 nathanw struct dcm_softc *sc;
478 1.47.8.2 nathanw struct tty *tp;
479 1.47.8.2 nathanw int unit, brd, port;
480 1.47.8.2 nathanw int error = 0, mbits, s;
481 1.47.8.2 nathanw
482 1.47.8.2 nathanw unit = DCMUNIT(dev);
483 1.47.8.2 nathanw brd = DCMBOARD(unit);
484 1.47.8.2 nathanw port = DCMPORT(unit);
485 1.47.8.2 nathanw
486 1.47.8.2 nathanw if (brd >= dcm_cd.cd_ndevs || port >= NDCMPORT ||
487 1.47.8.2 nathanw (sc = dcm_cd.cd_devs[brd]) == NULL)
488 1.47.8.2 nathanw return (ENXIO);
489 1.47.8.2 nathanw
490 1.47.8.2 nathanw if ((sc->sc_flags & DCM_ACTIVE) == 0)
491 1.47.8.2 nathanw return (ENXIO);
492 1.47.8.2 nathanw
493 1.47.8.2 nathanw if (sc->sc_tty[port] == NULL) {
494 1.47.8.2 nathanw tp = sc->sc_tty[port] = ttymalloc();
495 1.47.8.2 nathanw tty_attach(tp);
496 1.47.8.2 nathanw } else
497 1.47.8.2 nathanw tp = sc->sc_tty[port];
498 1.47.8.2 nathanw
499 1.47.8.2 nathanw tp->t_oproc = dcmstart;
500 1.47.8.2 nathanw tp->t_param = dcmparam;
501 1.47.8.2 nathanw tp->t_dev = dev;
502 1.47.8.2 nathanw
503 1.47.8.2 nathanw if ((tp->t_state & TS_ISOPEN) &&
504 1.47.8.2 nathanw (tp->t_state & TS_XCLUDE) &&
505 1.47.8.2 nathanw p->p_ucred->cr_uid != 0)
506 1.47.8.2 nathanw return (EBUSY);
507 1.47.8.2 nathanw
508 1.47.8.2 nathanw s = spltty();
509 1.47.8.2 nathanw
510 1.47.8.2 nathanw if ((tp->t_state & TS_ISOPEN) == 0 && tp->t_wopen == 0) {
511 1.47.8.2 nathanw /*
512 1.47.8.2 nathanw * Sanity clause: reset the card on first open.
513 1.47.8.2 nathanw * The card might be left in an inconsistent state
514 1.47.8.2 nathanw * if the card memory is read inadvertently.
515 1.47.8.2 nathanw */
516 1.47.8.2 nathanw dcminit(sc->sc_dcm, port, dcmdefaultrate);
517 1.47.8.2 nathanw
518 1.47.8.2 nathanw ttychars(tp);
519 1.47.8.2 nathanw tp->t_iflag = TTYDEF_IFLAG;
520 1.47.8.2 nathanw tp->t_oflag = TTYDEF_OFLAG;
521 1.47.8.2 nathanw tp->t_cflag = TTYDEF_CFLAG;
522 1.47.8.2 nathanw tp->t_lflag = TTYDEF_LFLAG;
523 1.47.8.2 nathanw tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
524 1.47.8.2 nathanw
525 1.47.8.2 nathanw (void) dcmparam(tp, &tp->t_termios);
526 1.47.8.2 nathanw ttsetwater(tp);
527 1.47.8.2 nathanw
528 1.47.8.2 nathanw /* Set modem control state. */
529 1.47.8.2 nathanw mbits = MO_ON;
530 1.47.8.2 nathanw if (sc->sc_flags & DCM_STDDCE)
531 1.47.8.2 nathanw mbits |= MO_SR; /* pin 23, could be used as RTS */
532 1.47.8.2 nathanw
533 1.47.8.2 nathanw (void) dcmmctl(dev, mbits, DMSET); /* enable port */
534 1.47.8.2 nathanw
535 1.47.8.2 nathanw /* Set soft-carrier if so configured. */
536 1.47.8.2 nathanw if ((sc->sc_softCAR & (1 << port)) ||
537 1.47.8.2 nathanw (dcmmctl(dev, MO_OFF, DMGET) & MI_CD))
538 1.47.8.2 nathanw tp->t_state |= TS_CARR_ON;
539 1.47.8.2 nathanw }
540 1.47.8.2 nathanw
541 1.47.8.2 nathanw splx(s);
542 1.47.8.2 nathanw
543 1.47.8.2 nathanw #ifdef DEBUG
544 1.47.8.2 nathanw if (dcmdebug & DDB_MODEM)
545 1.47.8.2 nathanw printf("%s: dcmopen port %d softcarr %c\n",
546 1.47.8.2 nathanw sc->sc_dev.dv_xname, port,
547 1.47.8.2 nathanw (tp->t_state & TS_CARR_ON) ? '1' : '0');
548 1.47.8.2 nathanw #endif
549 1.47.8.2 nathanw
550 1.47.8.2 nathanw error = ttyopen(tp, DCMDIALOUT(dev), (flag & O_NONBLOCK));
551 1.47.8.2 nathanw if (error)
552 1.47.8.2 nathanw goto bad;
553 1.47.8.2 nathanw
554 1.47.8.2 nathanw #ifdef DEBUG
555 1.47.8.2 nathanw if (dcmdebug & DDB_OPENCLOSE)
556 1.47.8.2 nathanw printf("%s port %d: dcmopen: st %x fl %x\n",
557 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, tp->t_state, tp->t_flags);
558 1.47.8.2 nathanw #endif
559 1.47.8.2 nathanw error = (*tp->t_linesw->l_open)(dev, tp);
560 1.47.8.2 nathanw
561 1.47.8.2 nathanw bad:
562 1.47.8.2 nathanw return (error);
563 1.47.8.2 nathanw }
564 1.47.8.2 nathanw
565 1.47.8.2 nathanw /*ARGSUSED*/
566 1.47.8.2 nathanw int
567 1.47.8.2 nathanw dcmclose(dev, flag, mode, p)
568 1.47.8.2 nathanw dev_t dev;
569 1.47.8.2 nathanw int flag, mode;
570 1.47.8.2 nathanw struct proc *p;
571 1.47.8.2 nathanw {
572 1.47.8.2 nathanw int s, unit, board, port;
573 1.47.8.2 nathanw struct dcm_softc *sc;
574 1.47.8.2 nathanw struct tty *tp;
575 1.47.8.2 nathanw
576 1.47.8.2 nathanw unit = DCMUNIT(dev);
577 1.47.8.2 nathanw board = DCMBOARD(unit);
578 1.47.8.2 nathanw port = DCMPORT(unit);
579 1.47.8.2 nathanw
580 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
581 1.47.8.2 nathanw tp = sc->sc_tty[port];
582 1.47.8.2 nathanw
583 1.47.8.2 nathanw (*tp->t_linesw->l_close)(tp, flag);
584 1.47.8.2 nathanw
585 1.47.8.2 nathanw s = spltty();
586 1.47.8.2 nathanw
587 1.47.8.2 nathanw if (tp->t_cflag & HUPCL || tp->t_wopen != 0 ||
588 1.47.8.2 nathanw (tp->t_state & TS_ISOPEN) == 0)
589 1.47.8.2 nathanw (void) dcmmctl(dev, MO_OFF, DMSET);
590 1.47.8.2 nathanw #ifdef DEBUG
591 1.47.8.2 nathanw if (dcmdebug & DDB_OPENCLOSE)
592 1.47.8.2 nathanw printf("%s port %d: dcmclose: st %x fl %x\n",
593 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, tp->t_state, tp->t_flags);
594 1.47.8.2 nathanw #endif
595 1.47.8.2 nathanw splx(s);
596 1.47.8.2 nathanw ttyclose(tp);
597 1.47.8.2 nathanw #if 0
598 1.47.8.2 nathanw tty_detach(tp);
599 1.47.8.2 nathanw ttyfree(tp);
600 1.47.8.2 nathanw sc->sc_tty[port] == NULL;
601 1.47.8.2 nathanw #endif
602 1.47.8.2 nathanw return (0);
603 1.47.8.2 nathanw }
604 1.47.8.2 nathanw
605 1.47.8.2 nathanw int
606 1.47.8.2 nathanw dcmread(dev, uio, flag)
607 1.47.8.2 nathanw dev_t dev;
608 1.47.8.2 nathanw struct uio *uio;
609 1.47.8.2 nathanw int flag;
610 1.47.8.2 nathanw {
611 1.47.8.2 nathanw int unit, board, port;
612 1.47.8.2 nathanw struct dcm_softc *sc;
613 1.47.8.2 nathanw struct tty *tp;
614 1.47.8.2 nathanw
615 1.47.8.2 nathanw unit = DCMUNIT(dev);
616 1.47.8.2 nathanw board = DCMBOARD(unit);
617 1.47.8.2 nathanw port = DCMPORT(unit);
618 1.47.8.2 nathanw
619 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
620 1.47.8.2 nathanw tp = sc->sc_tty[port];
621 1.47.8.2 nathanw
622 1.47.8.2 nathanw return ((*tp->t_linesw->l_read)(tp, uio, flag));
623 1.47.8.2 nathanw }
624 1.47.8.2 nathanw
625 1.47.8.2 nathanw int
626 1.47.8.2 nathanw dcmwrite(dev, uio, flag)
627 1.47.8.2 nathanw dev_t dev;
628 1.47.8.2 nathanw struct uio *uio;
629 1.47.8.2 nathanw int flag;
630 1.47.8.2 nathanw {
631 1.47.8.2 nathanw int unit, board, port;
632 1.47.8.2 nathanw struct dcm_softc *sc;
633 1.47.8.2 nathanw struct tty *tp;
634 1.47.8.2 nathanw
635 1.47.8.2 nathanw unit = DCMUNIT(dev);
636 1.47.8.2 nathanw board = DCMBOARD(unit);
637 1.47.8.2 nathanw port = DCMPORT(unit);
638 1.47.8.2 nathanw
639 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
640 1.47.8.2 nathanw tp = sc->sc_tty[port];
641 1.47.8.2 nathanw
642 1.47.8.2 nathanw return ((*tp->t_linesw->l_write)(tp, uio, flag));
643 1.47.8.2 nathanw }
644 1.47.8.2 nathanw
645 1.47.8.2 nathanw int
646 1.47.8.2 nathanw dcmpoll(dev, events, p)
647 1.47.8.2 nathanw dev_t dev;
648 1.47.8.2 nathanw int events;
649 1.47.8.2 nathanw struct proc *p;
650 1.47.8.2 nathanw {
651 1.47.8.2 nathanw int unit, board, port;
652 1.47.8.2 nathanw struct dcm_softc *sc;
653 1.47.8.2 nathanw struct tty *tp;
654 1.47.8.2 nathanw
655 1.47.8.2 nathanw unit = DCMUNIT(dev);
656 1.47.8.2 nathanw board = DCMBOARD(unit);
657 1.47.8.2 nathanw port = DCMPORT(unit);
658 1.47.8.2 nathanw
659 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
660 1.47.8.2 nathanw tp = sc->sc_tty[port];
661 1.47.8.2 nathanw
662 1.47.8.2 nathanw return ((*tp->t_linesw->l_poll)(tp, events, p));
663 1.47.8.2 nathanw }
664 1.47.8.2 nathanw
665 1.47.8.2 nathanw struct tty *
666 1.47.8.2 nathanw dcmtty(dev)
667 1.47.8.2 nathanw dev_t dev;
668 1.47.8.2 nathanw {
669 1.47.8.2 nathanw int unit, board, port;
670 1.47.8.2 nathanw struct dcm_softc *sc;
671 1.47.8.2 nathanw
672 1.47.8.2 nathanw unit = DCMUNIT(dev);
673 1.47.8.2 nathanw board = DCMBOARD(unit);
674 1.47.8.2 nathanw port = DCMPORT(unit);
675 1.47.8.2 nathanw
676 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
677 1.47.8.2 nathanw
678 1.47.8.2 nathanw return (sc->sc_tty[port]);
679 1.47.8.2 nathanw }
680 1.47.8.2 nathanw
681 1.47.8.2 nathanw int
682 1.47.8.2 nathanw dcmintr(arg)
683 1.47.8.2 nathanw void *arg;
684 1.47.8.2 nathanw {
685 1.47.8.2 nathanw struct dcm_softc *sc = arg;
686 1.47.8.2 nathanw struct dcmdevice *dcm = sc->sc_dcm;
687 1.47.8.2 nathanw struct dcmischeme *dis = &sc->sc_scheme;
688 1.47.8.2 nathanw int brd = sc->sc_dev.dv_unit;
689 1.47.8.2 nathanw int code, i;
690 1.47.8.2 nathanw int pcnd[4], mcode, mcnd[4];
691 1.47.8.2 nathanw
692 1.47.8.2 nathanw /*
693 1.47.8.2 nathanw * Do all guarded accesses right off to minimize
694 1.47.8.2 nathanw * block out of hardware.
695 1.47.8.2 nathanw */
696 1.47.8.2 nathanw SEM_LOCK(dcm);
697 1.47.8.2 nathanw if ((dcm->dcm_ic & IC_IR) == 0) {
698 1.47.8.2 nathanw SEM_UNLOCK(dcm);
699 1.47.8.2 nathanw return (0);
700 1.47.8.2 nathanw }
701 1.47.8.2 nathanw for (i = 0; i < 4; i++) {
702 1.47.8.2 nathanw pcnd[i] = dcm->dcm_icrtab[i].dcm_data;
703 1.47.8.2 nathanw dcm->dcm_icrtab[i].dcm_data = 0;
704 1.47.8.2 nathanw code = sc->sc_modem[i]->mdmin;
705 1.47.8.2 nathanw if (sc->sc_flags & DCM_STDDCE)
706 1.47.8.2 nathanw code = hp2dce_in(code);
707 1.47.8.2 nathanw mcnd[i] = code;
708 1.47.8.2 nathanw }
709 1.47.8.2 nathanw code = dcm->dcm_iir & IIR_MASK;
710 1.47.8.2 nathanw dcm->dcm_iir = 0; /* XXX doc claims read clears interrupt?! */
711 1.47.8.2 nathanw mcode = dcm->dcm_modemintr;
712 1.47.8.2 nathanw dcm->dcm_modemintr = 0;
713 1.47.8.2 nathanw SEM_UNLOCK(dcm);
714 1.47.8.2 nathanw
715 1.47.8.2 nathanw #ifdef DEBUG
716 1.47.8.2 nathanw if (dcmdebug & DDB_INTR) {
717 1.47.8.2 nathanw printf("%s: dcmintr: iir %x pc %x/%x/%x/%x ",
718 1.47.8.2 nathanw sc->sc_dev.dv_xname, code, pcnd[0], pcnd[1],
719 1.47.8.2 nathanw pcnd[2], pcnd[3]);
720 1.47.8.2 nathanw printf("miir %x mc %x/%x/%x/%x\n",
721 1.47.8.2 nathanw mcode, mcnd[0], mcnd[1], mcnd[2], mcnd[3]);
722 1.47.8.2 nathanw }
723 1.47.8.2 nathanw #endif
724 1.47.8.2 nathanw if (code & IIR_TIMEO)
725 1.47.8.2 nathanw dcmrint(sc);
726 1.47.8.2 nathanw if (code & IIR_PORT0)
727 1.47.8.2 nathanw dcmpint(sc, 0, pcnd[0]);
728 1.47.8.2 nathanw if (code & IIR_PORT1)
729 1.47.8.2 nathanw dcmpint(sc, 1, pcnd[1]);
730 1.47.8.2 nathanw if (code & IIR_PORT2)
731 1.47.8.2 nathanw dcmpint(sc, 2, pcnd[2]);
732 1.47.8.2 nathanw if (code & IIR_PORT3)
733 1.47.8.2 nathanw dcmpint(sc, 3, pcnd[3]);
734 1.47.8.2 nathanw if (code & IIR_MODM) {
735 1.47.8.2 nathanw if (mcode == 0 || mcode & 0x1) /* mcode==0 -> 98642 board */
736 1.47.8.2 nathanw dcmmint(sc, 0, mcnd[0]);
737 1.47.8.2 nathanw if (mcode & 0x2)
738 1.47.8.2 nathanw dcmmint(sc, 1, mcnd[1]);
739 1.47.8.2 nathanw if (mcode & 0x4)
740 1.47.8.2 nathanw dcmmint(sc, 2, mcnd[2]);
741 1.47.8.2 nathanw if (mcode & 0x8)
742 1.47.8.2 nathanw dcmmint(sc, 3, mcnd[3]);
743 1.47.8.2 nathanw }
744 1.47.8.2 nathanw
745 1.47.8.2 nathanw /*
746 1.47.8.2 nathanw * Chalk up a receiver interrupt if the timer running or one of
747 1.47.8.2 nathanw * the ports reports a special character interrupt.
748 1.47.8.2 nathanw */
749 1.47.8.2 nathanw if ((code & IIR_TIMEO) ||
750 1.47.8.2 nathanw ((pcnd[0]|pcnd[1]|pcnd[2]|pcnd[3]) & IT_SPEC))
751 1.47.8.2 nathanw dis->dis_intr++;
752 1.47.8.2 nathanw /*
753 1.47.8.2 nathanw * See if it is time to check/change the interrupt rate.
754 1.47.8.2 nathanw */
755 1.47.8.2 nathanw if (dcmistype < 0 &&
756 1.47.8.2 nathanw (i = time.tv_sec - dis->dis_time) >= dcminterval) {
757 1.47.8.2 nathanw /*
758 1.47.8.2 nathanw * If currently per-character and averaged over 70 interrupts
759 1.47.8.2 nathanw * per-second (66 is threshold of 600 baud) in last interval,
760 1.47.8.2 nathanw * switch to timer mode.
761 1.47.8.2 nathanw *
762 1.47.8.2 nathanw * XXX decay counts ala load average to avoid spikes?
763 1.47.8.2 nathanw */
764 1.47.8.2 nathanw if (dis->dis_perchar && dis->dis_intr > 70 * i)
765 1.47.8.2 nathanw dcmsetischeme(brd, DIS_TIMER);
766 1.47.8.2 nathanw /*
767 1.47.8.2 nathanw * If currently using timer and had more interrupts than
768 1.47.8.2 nathanw * received characters in the last interval, switch back
769 1.47.8.2 nathanw * to per-character. Note that after changing to per-char
770 1.47.8.2 nathanw * we must process any characters already in the queue
771 1.47.8.2 nathanw * since they may have arrived before the bitmap was setup.
772 1.47.8.2 nathanw *
773 1.47.8.2 nathanw * XXX decay counts?
774 1.47.8.2 nathanw */
775 1.47.8.2 nathanw else if (!dis->dis_perchar && dis->dis_intr > dis->dis_char) {
776 1.47.8.2 nathanw dcmsetischeme(brd, DIS_PERCHAR);
777 1.47.8.2 nathanw dcmrint(sc);
778 1.47.8.2 nathanw }
779 1.47.8.2 nathanw dis->dis_intr = dis->dis_char = 0;
780 1.47.8.2 nathanw dis->dis_time = time.tv_sec;
781 1.47.8.2 nathanw }
782 1.47.8.2 nathanw return (1);
783 1.47.8.2 nathanw }
784 1.47.8.2 nathanw
785 1.47.8.2 nathanw /*
786 1.47.8.2 nathanw * Port interrupt. Can be two things:
787 1.47.8.2 nathanw * First, it might be a special character (exception interrupt);
788 1.47.8.2 nathanw * Second, it may be a buffer empty (transmit interrupt);
789 1.47.8.2 nathanw */
790 1.47.8.2 nathanw void
791 1.47.8.2 nathanw dcmpint(sc, port, code)
792 1.47.8.2 nathanw struct dcm_softc *sc;
793 1.47.8.2 nathanw int port, code;
794 1.47.8.2 nathanw {
795 1.47.8.2 nathanw
796 1.47.8.2 nathanw if (code & IT_SPEC)
797 1.47.8.2 nathanw dcmreadbuf(sc, port);
798 1.47.8.2 nathanw if (code & IT_TX)
799 1.47.8.2 nathanw dcmxint(sc, port);
800 1.47.8.2 nathanw }
801 1.47.8.2 nathanw
802 1.47.8.2 nathanw void
803 1.47.8.2 nathanw dcmrint(sc)
804 1.47.8.2 nathanw struct dcm_softc *sc;
805 1.47.8.2 nathanw {
806 1.47.8.2 nathanw int port;
807 1.47.8.2 nathanw
808 1.47.8.2 nathanw for (port = 0; port < NDCMPORT; port++)
809 1.47.8.2 nathanw dcmreadbuf(sc, port);
810 1.47.8.2 nathanw }
811 1.47.8.2 nathanw
812 1.47.8.2 nathanw void
813 1.47.8.2 nathanw dcmreadbuf(sc, port)
814 1.47.8.2 nathanw struct dcm_softc *sc;
815 1.47.8.2 nathanw int port;
816 1.47.8.2 nathanw {
817 1.47.8.2 nathanw struct dcmdevice *dcm = sc->sc_dcm;
818 1.47.8.2 nathanw struct dcmpreg *pp = dcm_preg(dcm, port);
819 1.47.8.2 nathanw struct dcmrfifo *fifo;
820 1.47.8.2 nathanw struct tty *tp;
821 1.47.8.2 nathanw int c, stat;
822 1.47.8.2 nathanw u_int head;
823 1.47.8.2 nathanw int nch = 0;
824 1.47.8.2 nathanw #ifdef DCMSTATS
825 1.47.8.2 nathanw struct dcmstats *dsp = &sc->sc_stats;
826 1.47.8.2 nathanw
827 1.47.8.2 nathanw dsp->rints++;
828 1.47.8.2 nathanw #endif
829 1.47.8.2 nathanw tp = sc->sc_tty[port];
830 1.47.8.2 nathanw if (tp == NULL)
831 1.47.8.2 nathanw return;
832 1.47.8.2 nathanw
833 1.47.8.2 nathanw if ((tp->t_state & TS_ISOPEN) == 0) {
834 1.47.8.2 nathanw #ifdef KGDB
835 1.47.8.2 nathanw if ((makedev(dcmmajor, minor(tp->t_dev)) == kgdb_dev) &&
836 1.47.8.2 nathanw (head = pp->r_head & RX_MASK) != (pp->r_tail & RX_MASK) &&
837 1.47.8.2 nathanw dcm->dcm_rfifos[3-port][head>>1].data_char == FRAME_START) {
838 1.47.8.2 nathanw pp->r_head = (head + 2) & RX_MASK;
839 1.47.8.2 nathanw kgdb_connect(0); /* trap into kgdb */
840 1.47.8.2 nathanw return;
841 1.47.8.2 nathanw }
842 1.47.8.2 nathanw #endif /* KGDB */
843 1.47.8.2 nathanw pp->r_head = pp->r_tail & RX_MASK;
844 1.47.8.2 nathanw return;
845 1.47.8.2 nathanw }
846 1.47.8.2 nathanw
847 1.47.8.2 nathanw head = pp->r_head & RX_MASK;
848 1.47.8.2 nathanw fifo = &dcm->dcm_rfifos[3-port][head>>1];
849 1.47.8.2 nathanw /*
850 1.47.8.2 nathanw * XXX upper bound on how many chars we will take in one swallow?
851 1.47.8.2 nathanw */
852 1.47.8.2 nathanw while (head != (pp->r_tail & RX_MASK)) {
853 1.47.8.2 nathanw /*
854 1.47.8.2 nathanw * Get character/status and update head pointer as fast
855 1.47.8.2 nathanw * as possible to make room for more characters.
856 1.47.8.2 nathanw */
857 1.47.8.2 nathanw c = fifo->data_char;
858 1.47.8.2 nathanw stat = fifo->data_stat;
859 1.47.8.2 nathanw head = (head + 2) & RX_MASK;
860 1.47.8.2 nathanw pp->r_head = head;
861 1.47.8.2 nathanw fifo = head ? fifo+1 : &dcm->dcm_rfifos[3-port][0];
862 1.47.8.2 nathanw nch++;
863 1.47.8.2 nathanw
864 1.47.8.2 nathanw #ifdef DEBUG
865 1.47.8.2 nathanw if (dcmdebug & DDB_INPUT)
866 1.47.8.2 nathanw printf("%s port %d: dcmreadbuf: c%x('%c') s%x f%x h%x t%x\n",
867 1.47.8.2 nathanw sc->sc_dev.dv_xname, port,
868 1.47.8.2 nathanw c&0xFF, c, stat&0xFF,
869 1.47.8.2 nathanw tp->t_flags, head, pp->r_tail);
870 1.47.8.2 nathanw #endif
871 1.47.8.2 nathanw /*
872 1.47.8.2 nathanw * Check for and handle errors
873 1.47.8.2 nathanw */
874 1.47.8.2 nathanw if (stat & RD_MASK) {
875 1.47.8.2 nathanw #ifdef DEBUG
876 1.47.8.2 nathanw if (dcmdebug & (DDB_INPUT|DDB_SIOERR))
877 1.47.8.2 nathanw printf("%s port %d: dcmreadbuf: err: c%x('%c') s%x\n",
878 1.47.8.2 nathanw sc->sc_dev.dv_xname, port,
879 1.47.8.2 nathanw stat, c&0xFF, c);
880 1.47.8.2 nathanw #endif
881 1.47.8.2 nathanw if (stat & (RD_BD | RD_FE))
882 1.47.8.2 nathanw c |= TTY_FE;
883 1.47.8.2 nathanw else if (stat & RD_PE)
884 1.47.8.2 nathanw c |= TTY_PE;
885 1.47.8.2 nathanw else if (stat & RD_OVF)
886 1.47.8.2 nathanw log(LOG_WARNING,
887 1.47.8.2 nathanw "%s port %d: silo overflow\n",
888 1.47.8.2 nathanw sc->sc_dev.dv_xname, port);
889 1.47.8.2 nathanw else if (stat & RD_OE)
890 1.47.8.2 nathanw log(LOG_WARNING,
891 1.47.8.2 nathanw "%s port %d: uart overflow\n",
892 1.47.8.2 nathanw sc->sc_dev.dv_xname, port);
893 1.47.8.2 nathanw }
894 1.47.8.2 nathanw (*tp->t_linesw->l_rint)(c, tp);
895 1.47.8.2 nathanw }
896 1.47.8.2 nathanw sc->sc_scheme.dis_char += nch;
897 1.47.8.2 nathanw
898 1.47.8.2 nathanw #ifdef DCMSTATS
899 1.47.8.2 nathanw dsp->rchars += nch;
900 1.47.8.2 nathanw if (nch <= DCMRBSIZE)
901 1.47.8.2 nathanw dsp->rsilo[nch]++;
902 1.47.8.2 nathanw else
903 1.47.8.2 nathanw dsp->rsilo[DCMRBSIZE+1]++;
904 1.47.8.2 nathanw #endif
905 1.47.8.2 nathanw }
906 1.47.8.2 nathanw
907 1.47.8.2 nathanw void
908 1.47.8.2 nathanw dcmxint(sc, port)
909 1.47.8.2 nathanw struct dcm_softc *sc;
910 1.47.8.2 nathanw int port;
911 1.47.8.2 nathanw {
912 1.47.8.2 nathanw struct tty *tp;
913 1.47.8.2 nathanw
914 1.47.8.2 nathanw tp = sc->sc_tty[port];
915 1.47.8.2 nathanw if (tp == NULL || (tp->t_state & TS_ISOPEN) == 0)
916 1.47.8.2 nathanw return;
917 1.47.8.2 nathanw
918 1.47.8.2 nathanw tp->t_state &= ~TS_BUSY;
919 1.47.8.2 nathanw if (tp->t_state & TS_FLUSH)
920 1.47.8.2 nathanw tp->t_state &= ~TS_FLUSH;
921 1.47.8.2 nathanw (*tp->t_linesw->l_start)(tp);
922 1.47.8.2 nathanw }
923 1.47.8.2 nathanw
924 1.47.8.2 nathanw void
925 1.47.8.2 nathanw dcmmint(sc, port, mcnd)
926 1.47.8.2 nathanw struct dcm_softc *sc;
927 1.47.8.2 nathanw int port, mcnd;
928 1.47.8.2 nathanw {
929 1.47.8.2 nathanw int delta;
930 1.47.8.2 nathanw struct tty *tp;
931 1.47.8.2 nathanw struct dcmdevice *dcm = sc->sc_dcm;
932 1.47.8.2 nathanw
933 1.47.8.2 nathanw tp = sc->sc_tty[port];
934 1.47.8.2 nathanw if (tp == NULL || (tp->t_state & TS_ISOPEN) == 0)
935 1.47.8.2 nathanw return;
936 1.47.8.2 nathanw
937 1.47.8.2 nathanw #ifdef DEBUG
938 1.47.8.2 nathanw if (dcmdebug & DDB_MODEM)
939 1.47.8.2 nathanw printf("%s port %d: dcmmint: mcnd %x mcndlast %x\n",
940 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, mcnd, sc->sc_mcndlast[port]);
941 1.47.8.2 nathanw #endif
942 1.47.8.2 nathanw delta = mcnd ^ sc->sc_mcndlast[port];
943 1.47.8.2 nathanw sc->sc_mcndlast[port] = mcnd;
944 1.47.8.2 nathanw if ((delta & MI_CTS) && (tp->t_state & TS_ISOPEN) &&
945 1.47.8.2 nathanw (tp->t_flags & CCTS_OFLOW)) {
946 1.47.8.2 nathanw if (mcnd & MI_CTS) {
947 1.47.8.2 nathanw tp->t_state &= ~TS_TTSTOP;
948 1.47.8.2 nathanw ttstart(tp);
949 1.47.8.2 nathanw } else
950 1.47.8.2 nathanw tp->t_state |= TS_TTSTOP; /* inline dcmstop */
951 1.47.8.2 nathanw }
952 1.47.8.2 nathanw if (delta & MI_CD) {
953 1.47.8.2 nathanw if (mcnd & MI_CD)
954 1.47.8.2 nathanw (void)(*tp->t_linesw->l_modem)(tp, 1);
955 1.47.8.2 nathanw else if ((sc->sc_softCAR & (1 << port)) == 0 &&
956 1.47.8.2 nathanw (*tp->t_linesw->l_modem)(tp, 0) == 0) {
957 1.47.8.2 nathanw sc->sc_modem[port]->mdmout = MO_OFF;
958 1.47.8.2 nathanw SEM_LOCK(dcm);
959 1.47.8.2 nathanw dcm->dcm_modemchng |= (1 << port);
960 1.47.8.2 nathanw dcm->dcm_cr |= CR_MODM;
961 1.47.8.2 nathanw SEM_UNLOCK(dcm);
962 1.47.8.2 nathanw DELAY(10); /* time to change lines */
963 1.47.8.2 nathanw }
964 1.47.8.2 nathanw }
965 1.47.8.2 nathanw }
966 1.47.8.2 nathanw
967 1.47.8.2 nathanw int
968 1.47.8.2 nathanw dcmioctl(dev, cmd, data, flag, p)
969 1.47.8.2 nathanw dev_t dev;
970 1.47.8.2 nathanw u_long cmd;
971 1.47.8.2 nathanw caddr_t data;
972 1.47.8.2 nathanw int flag;
973 1.47.8.2 nathanw struct proc *p;
974 1.47.8.2 nathanw {
975 1.47.8.2 nathanw struct dcm_softc *sc;
976 1.47.8.2 nathanw struct tty *tp;
977 1.47.8.2 nathanw struct dcmdevice *dcm;
978 1.47.8.2 nathanw int board, port, unit = DCMUNIT(dev);
979 1.47.8.2 nathanw int error, s;
980 1.47.8.2 nathanw
981 1.47.8.2 nathanw port = DCMPORT(unit);
982 1.47.8.2 nathanw board = DCMBOARD(unit);
983 1.47.8.2 nathanw
984 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
985 1.47.8.2 nathanw dcm = sc->sc_dcm;
986 1.47.8.2 nathanw tp = sc->sc_tty[port];
987 1.47.8.2 nathanw
988 1.47.8.2 nathanw #ifdef DEBUG
989 1.47.8.2 nathanw if (dcmdebug & DDB_IOCTL)
990 1.47.8.2 nathanw printf("%s port %d: dcmioctl: cmd %lx data %x flag %x\n",
991 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, cmd, *data, flag);
992 1.47.8.2 nathanw #endif
993 1.47.8.2 nathanw error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
994 1.47.8.2 nathanw if (error >= 0)
995 1.47.8.2 nathanw return (error);
996 1.47.8.2 nathanw error = ttioctl(tp, cmd, data, flag, p);
997 1.47.8.2 nathanw if (error >= 0)
998 1.47.8.2 nathanw return (error);
999 1.47.8.2 nathanw
1000 1.47.8.2 nathanw switch (cmd) {
1001 1.47.8.2 nathanw case TIOCSBRK:
1002 1.47.8.2 nathanw /*
1003 1.47.8.2 nathanw * Wait for transmitter buffer to empty
1004 1.47.8.2 nathanw */
1005 1.47.8.2 nathanw s = spltty();
1006 1.47.8.2 nathanw while (dcm->dcm_thead[port].ptr != dcm->dcm_ttail[port].ptr)
1007 1.47.8.2 nathanw DELAY(DCM_USPERCH(tp->t_ospeed));
1008 1.47.8.2 nathanw SEM_LOCK(dcm);
1009 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_BRK;
1010 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port); /* start break */
1011 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1012 1.47.8.2 nathanw splx(s);
1013 1.47.8.2 nathanw break;
1014 1.47.8.2 nathanw
1015 1.47.8.2 nathanw case TIOCCBRK:
1016 1.47.8.2 nathanw SEM_LOCK(dcm);
1017 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_BRK;
1018 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port); /* end break */
1019 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1020 1.47.8.2 nathanw break;
1021 1.47.8.2 nathanw
1022 1.47.8.2 nathanw case TIOCSDTR:
1023 1.47.8.2 nathanw (void) dcmmctl(dev, MO_ON, DMBIS);
1024 1.47.8.2 nathanw break;
1025 1.47.8.2 nathanw
1026 1.47.8.2 nathanw case TIOCCDTR:
1027 1.47.8.2 nathanw (void) dcmmctl(dev, MO_ON, DMBIC);
1028 1.47.8.2 nathanw break;
1029 1.47.8.2 nathanw
1030 1.47.8.2 nathanw case TIOCMSET:
1031 1.47.8.2 nathanw (void) dcmmctl(dev, *(int *)data, DMSET);
1032 1.47.8.2 nathanw break;
1033 1.47.8.2 nathanw
1034 1.47.8.2 nathanw case TIOCMBIS:
1035 1.47.8.2 nathanw (void) dcmmctl(dev, *(int *)data, DMBIS);
1036 1.47.8.2 nathanw break;
1037 1.47.8.2 nathanw
1038 1.47.8.2 nathanw case TIOCMBIC:
1039 1.47.8.2 nathanw (void) dcmmctl(dev, *(int *)data, DMBIC);
1040 1.47.8.2 nathanw break;
1041 1.47.8.2 nathanw
1042 1.47.8.2 nathanw case TIOCMGET:
1043 1.47.8.2 nathanw *(int *)data = dcmmctl(dev, 0, DMGET);
1044 1.47.8.2 nathanw break;
1045 1.47.8.2 nathanw
1046 1.47.8.2 nathanw case TIOCGFLAGS: {
1047 1.47.8.2 nathanw int bits = 0;
1048 1.47.8.2 nathanw
1049 1.47.8.2 nathanw if ((sc->sc_softCAR & (1 << port)))
1050 1.47.8.2 nathanw bits |= TIOCFLAG_SOFTCAR;
1051 1.47.8.2 nathanw
1052 1.47.8.2 nathanw if (tp->t_cflag & CLOCAL)
1053 1.47.8.2 nathanw bits |= TIOCFLAG_CLOCAL;
1054 1.47.8.2 nathanw
1055 1.47.8.2 nathanw *(int *)data = bits;
1056 1.47.8.2 nathanw break;
1057 1.47.8.2 nathanw }
1058 1.47.8.2 nathanw
1059 1.47.8.2 nathanw case TIOCSFLAGS: {
1060 1.47.8.2 nathanw int userbits;
1061 1.47.8.2 nathanw
1062 1.47.8.2 nathanw error = suser(p->p_ucred, &p->p_acflag);
1063 1.47.8.2 nathanw if (error)
1064 1.47.8.2 nathanw return (EPERM);
1065 1.47.8.2 nathanw
1066 1.47.8.2 nathanw userbits = *(int *)data;
1067 1.47.8.2 nathanw
1068 1.47.8.2 nathanw if ((userbits & TIOCFLAG_SOFTCAR) ||
1069 1.47.8.2 nathanw ((sc->sc_flags & DCM_ISCONSOLE) &&
1070 1.47.8.2 nathanw (port == DCMCONSPORT)))
1071 1.47.8.2 nathanw sc->sc_softCAR |= (1 << port);
1072 1.47.8.2 nathanw
1073 1.47.8.2 nathanw if (userbits & TIOCFLAG_CLOCAL)
1074 1.47.8.2 nathanw tp->t_cflag |= CLOCAL;
1075 1.47.8.2 nathanw
1076 1.47.8.2 nathanw break;
1077 1.47.8.2 nathanw }
1078 1.47.8.2 nathanw
1079 1.47.8.2 nathanw default:
1080 1.47.8.2 nathanw return (ENOTTY);
1081 1.47.8.2 nathanw }
1082 1.47.8.2 nathanw return (0);
1083 1.47.8.2 nathanw }
1084 1.47.8.2 nathanw
1085 1.47.8.2 nathanw int
1086 1.47.8.2 nathanw dcmparam(tp, t)
1087 1.47.8.2 nathanw struct tty *tp;
1088 1.47.8.2 nathanw struct termios *t;
1089 1.47.8.2 nathanw {
1090 1.47.8.2 nathanw struct dcm_softc *sc;
1091 1.47.8.2 nathanw struct dcmdevice *dcm;
1092 1.47.8.2 nathanw int unit, board, port, mode, cflag = t->c_cflag;
1093 1.47.8.2 nathanw int ospeed = ttspeedtab(t->c_ospeed, dcmspeedtab);
1094 1.47.8.2 nathanw
1095 1.47.8.2 nathanw unit = DCMUNIT(tp->t_dev);
1096 1.47.8.2 nathanw board = DCMBOARD(unit);
1097 1.47.8.2 nathanw port = DCMPORT(unit);
1098 1.47.8.2 nathanw
1099 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
1100 1.47.8.2 nathanw dcm = sc->sc_dcm;
1101 1.47.8.2 nathanw
1102 1.47.8.2 nathanw /* check requested parameters */
1103 1.47.8.2 nathanw if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
1104 1.47.8.2 nathanw return (EINVAL);
1105 1.47.8.2 nathanw /* and copy to tty */
1106 1.47.8.2 nathanw tp->t_ispeed = t->c_ispeed;
1107 1.47.8.2 nathanw tp->t_ospeed = t->c_ospeed;
1108 1.47.8.2 nathanw tp->t_cflag = cflag;
1109 1.47.8.2 nathanw if (ospeed == 0) {
1110 1.47.8.2 nathanw (void) dcmmctl(DCMUNIT(tp->t_dev), MO_OFF, DMSET);
1111 1.47.8.2 nathanw return (0);
1112 1.47.8.2 nathanw }
1113 1.47.8.2 nathanw
1114 1.47.8.2 nathanw mode = 0;
1115 1.47.8.2 nathanw switch (cflag&CSIZE) {
1116 1.47.8.2 nathanw case CS5:
1117 1.47.8.2 nathanw mode = LC_5BITS; break;
1118 1.47.8.2 nathanw case CS6:
1119 1.47.8.2 nathanw mode = LC_6BITS; break;
1120 1.47.8.2 nathanw case CS7:
1121 1.47.8.2 nathanw mode = LC_7BITS; break;
1122 1.47.8.2 nathanw case CS8:
1123 1.47.8.2 nathanw mode = LC_8BITS; break;
1124 1.47.8.2 nathanw }
1125 1.47.8.2 nathanw if (cflag&PARENB) {
1126 1.47.8.2 nathanw if (cflag&PARODD)
1127 1.47.8.2 nathanw mode |= LC_PODD;
1128 1.47.8.2 nathanw else
1129 1.47.8.2 nathanw mode |= LC_PEVEN;
1130 1.47.8.2 nathanw }
1131 1.47.8.2 nathanw if (cflag&CSTOPB)
1132 1.47.8.2 nathanw mode |= LC_2STOP;
1133 1.47.8.2 nathanw else
1134 1.47.8.2 nathanw mode |= LC_1STOP;
1135 1.47.8.2 nathanw #ifdef DEBUG
1136 1.47.8.2 nathanw if (dcmdebug & DDB_PARAM)
1137 1.47.8.2 nathanw printf("%s port %d: dcmparam: cflag %x mode %x speed %d uperch %d\n",
1138 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, cflag, mode, tp->t_ospeed,
1139 1.47.8.2 nathanw DCM_USPERCH(tp->t_ospeed));
1140 1.47.8.2 nathanw #endif
1141 1.47.8.2 nathanw
1142 1.47.8.2 nathanw /*
1143 1.47.8.2 nathanw * Wait for transmitter buffer to empty.
1144 1.47.8.2 nathanw */
1145 1.47.8.2 nathanw while (dcm->dcm_thead[port].ptr != dcm->dcm_ttail[port].ptr)
1146 1.47.8.2 nathanw DELAY(DCM_USPERCH(tp->t_ospeed));
1147 1.47.8.2 nathanw /*
1148 1.47.8.2 nathanw * Make changes known to hardware.
1149 1.47.8.2 nathanw */
1150 1.47.8.2 nathanw dcm->dcm_data[port].dcm_baud = ospeed;
1151 1.47.8.2 nathanw dcm->dcm_data[port].dcm_conf = mode;
1152 1.47.8.2 nathanw SEM_LOCK(dcm);
1153 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_CON;
1154 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port);
1155 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1156 1.47.8.2 nathanw /*
1157 1.47.8.2 nathanw * Delay for config change to take place. Weighted by baud.
1158 1.47.8.2 nathanw * XXX why do we do this?
1159 1.47.8.2 nathanw */
1160 1.47.8.2 nathanw DELAY(16 * DCM_USPERCH(tp->t_ospeed));
1161 1.47.8.2 nathanw return (0);
1162 1.47.8.2 nathanw }
1163 1.47.8.2 nathanw
1164 1.47.8.2 nathanw void
1165 1.47.8.2 nathanw dcmstart(tp)
1166 1.47.8.2 nathanw struct tty *tp;
1167 1.47.8.2 nathanw {
1168 1.47.8.2 nathanw struct dcm_softc *sc;
1169 1.47.8.2 nathanw struct dcmdevice *dcm;
1170 1.47.8.2 nathanw struct dcmpreg *pp;
1171 1.47.8.2 nathanw struct dcmtfifo *fifo;
1172 1.47.8.2 nathanw char *bp;
1173 1.47.8.2 nathanw u_int head, tail, next;
1174 1.47.8.2 nathanw int unit, board, port, nch;
1175 1.47.8.2 nathanw char buf[16];
1176 1.47.8.2 nathanw int s;
1177 1.47.8.2 nathanw #ifdef DCMSTATS
1178 1.47.8.2 nathanw struct dcmstats *dsp = &sc->sc_stats;
1179 1.47.8.2 nathanw int tch = 0;
1180 1.47.8.2 nathanw #endif
1181 1.47.8.2 nathanw
1182 1.47.8.2 nathanw unit = DCMUNIT(tp->t_dev);
1183 1.47.8.2 nathanw board = DCMBOARD(unit);
1184 1.47.8.2 nathanw port = DCMPORT(unit);
1185 1.47.8.2 nathanw
1186 1.47.8.2 nathanw sc = dcm_cd.cd_devs[board];
1187 1.47.8.2 nathanw dcm = sc->sc_dcm;
1188 1.47.8.2 nathanw
1189 1.47.8.2 nathanw s = spltty();
1190 1.47.8.2 nathanw #ifdef DCMSTATS
1191 1.47.8.2 nathanw dsp->xints++;
1192 1.47.8.2 nathanw #endif
1193 1.47.8.2 nathanw #ifdef DEBUG
1194 1.47.8.2 nathanw if (dcmdebug & DDB_OUTPUT)
1195 1.47.8.2 nathanw printf("%s port %d: dcmstart: state %x flags %x outcc %d\n",
1196 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, tp->t_state, tp->t_flags,
1197 1.47.8.2 nathanw tp->t_outq.c_cc);
1198 1.47.8.2 nathanw #endif
1199 1.47.8.2 nathanw if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
1200 1.47.8.2 nathanw goto out;
1201 1.47.8.2 nathanw if (tp->t_outq.c_cc <= tp->t_lowat) {
1202 1.47.8.2 nathanw if (tp->t_state&TS_ASLEEP) {
1203 1.47.8.2 nathanw tp->t_state &= ~TS_ASLEEP;
1204 1.47.8.2 nathanw wakeup((caddr_t)&tp->t_outq);
1205 1.47.8.2 nathanw }
1206 1.47.8.2 nathanw selwakeup(&tp->t_wsel);
1207 1.47.8.2 nathanw }
1208 1.47.8.2 nathanw if (tp->t_outq.c_cc == 0) {
1209 1.47.8.2 nathanw #ifdef DCMSTATS
1210 1.47.8.2 nathanw dsp->xempty++;
1211 1.47.8.2 nathanw #endif
1212 1.47.8.2 nathanw goto out;
1213 1.47.8.2 nathanw }
1214 1.47.8.2 nathanw
1215 1.47.8.2 nathanw pp = dcm_preg(dcm, port);
1216 1.47.8.2 nathanw tail = pp->t_tail & TX_MASK;
1217 1.47.8.2 nathanw next = (tail + 1) & TX_MASK;
1218 1.47.8.2 nathanw head = pp->t_head & TX_MASK;
1219 1.47.8.2 nathanw if (head == next)
1220 1.47.8.2 nathanw goto out;
1221 1.47.8.2 nathanw fifo = &dcm->dcm_tfifos[3-port][tail];
1222 1.47.8.2 nathanw again:
1223 1.47.8.2 nathanw nch = q_to_b(&tp->t_outq, buf, (head - next) & TX_MASK);
1224 1.47.8.2 nathanw #ifdef DCMSTATS
1225 1.47.8.2 nathanw tch += nch;
1226 1.47.8.2 nathanw #endif
1227 1.47.8.2 nathanw #ifdef DEBUG
1228 1.47.8.2 nathanw if (dcmdebug & DDB_OUTPUT)
1229 1.47.8.2 nathanw printf("\thead %x tail %x nch %d\n", head, tail, nch);
1230 1.47.8.2 nathanw #endif
1231 1.47.8.2 nathanw /*
1232 1.47.8.2 nathanw * Loop transmitting all the characters we can.
1233 1.47.8.2 nathanw */
1234 1.47.8.2 nathanw for (bp = buf; --nch >= 0; bp++) {
1235 1.47.8.2 nathanw fifo->data_char = *bp;
1236 1.47.8.2 nathanw pp->t_tail = next;
1237 1.47.8.2 nathanw /*
1238 1.47.8.2 nathanw * If this is the first character,
1239 1.47.8.2 nathanw * get the hardware moving right now.
1240 1.47.8.2 nathanw */
1241 1.47.8.2 nathanw if (bp == buf) {
1242 1.47.8.2 nathanw tp->t_state |= TS_BUSY;
1243 1.47.8.2 nathanw SEM_LOCK(dcm);
1244 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_TX;
1245 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port);
1246 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1247 1.47.8.2 nathanw }
1248 1.47.8.2 nathanw tail = next;
1249 1.47.8.2 nathanw fifo = tail ? fifo+1 : &dcm->dcm_tfifos[3-port][0];
1250 1.47.8.2 nathanw next = (next + 1) & TX_MASK;
1251 1.47.8.2 nathanw }
1252 1.47.8.2 nathanw /*
1253 1.47.8.2 nathanw * Head changed while we were loading the buffer,
1254 1.47.8.2 nathanw * go back and load some more if we can.
1255 1.47.8.2 nathanw */
1256 1.47.8.2 nathanw if (tp->t_outq.c_cc && head != (pp->t_head & TX_MASK)) {
1257 1.47.8.2 nathanw #ifdef DCMSTATS
1258 1.47.8.2 nathanw dsp->xrestarts++;
1259 1.47.8.2 nathanw #endif
1260 1.47.8.2 nathanw head = pp->t_head & TX_MASK;
1261 1.47.8.2 nathanw goto again;
1262 1.47.8.2 nathanw }
1263 1.47.8.2 nathanw
1264 1.47.8.2 nathanw /*
1265 1.47.8.2 nathanw * Kick it one last time in case it finished while we were
1266 1.47.8.2 nathanw * loading the last bunch.
1267 1.47.8.2 nathanw */
1268 1.47.8.2 nathanw if (bp > &buf[1]) {
1269 1.47.8.2 nathanw tp->t_state |= TS_BUSY;
1270 1.47.8.2 nathanw SEM_LOCK(dcm);
1271 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_TX;
1272 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port);
1273 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1274 1.47.8.2 nathanw }
1275 1.47.8.2 nathanw #ifdef DEBUG
1276 1.47.8.2 nathanw if (dcmdebug & DDB_INTR)
1277 1.47.8.2 nathanw printf("%s port %d: dcmstart: head %x tail %x outqcc %d\n",
1278 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, head, tail, tp->t_outq.c_cc);
1279 1.47.8.2 nathanw #endif
1280 1.47.8.2 nathanw out:
1281 1.47.8.2 nathanw #ifdef DCMSTATS
1282 1.47.8.2 nathanw dsp->xchars += tch;
1283 1.47.8.2 nathanw if (tch <= DCMXBSIZE)
1284 1.47.8.2 nathanw dsp->xsilo[tch]++;
1285 1.47.8.2 nathanw else
1286 1.47.8.2 nathanw dsp->xsilo[DCMXBSIZE+1]++;
1287 1.47.8.2 nathanw #endif
1288 1.47.8.2 nathanw splx(s);
1289 1.47.8.2 nathanw }
1290 1.47.8.2 nathanw
1291 1.47.8.2 nathanw /*
1292 1.47.8.2 nathanw * Stop output on a line.
1293 1.47.8.2 nathanw */
1294 1.47.8.2 nathanw void
1295 1.47.8.2 nathanw dcmstop(tp, flag)
1296 1.47.8.2 nathanw struct tty *tp;
1297 1.47.8.2 nathanw int flag;
1298 1.47.8.2 nathanw {
1299 1.47.8.2 nathanw int s;
1300 1.47.8.2 nathanw
1301 1.47.8.2 nathanw s = spltty();
1302 1.47.8.2 nathanw if (tp->t_state & TS_BUSY) {
1303 1.47.8.2 nathanw /* XXX is there some way to safely stop transmission? */
1304 1.47.8.2 nathanw if ((tp->t_state&TS_TTSTOP) == 0)
1305 1.47.8.2 nathanw tp->t_state |= TS_FLUSH;
1306 1.47.8.2 nathanw }
1307 1.47.8.2 nathanw splx(s);
1308 1.47.8.2 nathanw }
1309 1.47.8.2 nathanw
1310 1.47.8.2 nathanw /*
1311 1.47.8.2 nathanw * Modem control
1312 1.47.8.2 nathanw */
1313 1.47.8.2 nathanw int
1314 1.47.8.2 nathanw dcmmctl(dev, bits, how)
1315 1.47.8.2 nathanw dev_t dev;
1316 1.47.8.2 nathanw int bits, how;
1317 1.47.8.2 nathanw {
1318 1.47.8.2 nathanw struct dcm_softc *sc;
1319 1.47.8.2 nathanw struct dcmdevice *dcm;
1320 1.47.8.2 nathanw int s, unit, brd, port, hit = 0;
1321 1.47.8.2 nathanw
1322 1.47.8.2 nathanw unit = DCMUNIT(dev);
1323 1.47.8.2 nathanw brd = DCMBOARD(unit);
1324 1.47.8.2 nathanw port = DCMPORT(unit);
1325 1.47.8.2 nathanw
1326 1.47.8.2 nathanw sc = dcm_cd.cd_devs[brd];
1327 1.47.8.2 nathanw dcm = sc->sc_dcm;
1328 1.47.8.2 nathanw
1329 1.47.8.2 nathanw #ifdef DEBUG
1330 1.47.8.2 nathanw if (dcmdebug & DDB_MODEM)
1331 1.47.8.2 nathanw printf("%s port %d: dcmmctl: bits 0x%x how %x\n",
1332 1.47.8.2 nathanw sc->sc_dev.dv_xname, port, bits, how);
1333 1.47.8.2 nathanw #endif
1334 1.47.8.2 nathanw
1335 1.47.8.2 nathanw s = spltty();
1336 1.47.8.2 nathanw
1337 1.47.8.2 nathanw switch (how) {
1338 1.47.8.2 nathanw case DMSET:
1339 1.47.8.2 nathanw sc->sc_modem[port]->mdmout = bits;
1340 1.47.8.2 nathanw hit++;
1341 1.47.8.2 nathanw break;
1342 1.47.8.2 nathanw
1343 1.47.8.2 nathanw case DMBIS:
1344 1.47.8.2 nathanw sc->sc_modem[port]->mdmout |= bits;
1345 1.47.8.2 nathanw hit++;
1346 1.47.8.2 nathanw break;
1347 1.47.8.2 nathanw
1348 1.47.8.2 nathanw case DMBIC:
1349 1.47.8.2 nathanw sc->sc_modem[port]->mdmout &= ~bits;
1350 1.47.8.2 nathanw hit++;
1351 1.47.8.2 nathanw break;
1352 1.47.8.2 nathanw
1353 1.47.8.2 nathanw case DMGET:
1354 1.47.8.2 nathanw bits = sc->sc_modem[port]->mdmin;
1355 1.47.8.2 nathanw if (sc->sc_flags & DCM_STDDCE)
1356 1.47.8.2 nathanw bits = hp2dce_in(bits);
1357 1.47.8.2 nathanw break;
1358 1.47.8.2 nathanw }
1359 1.47.8.2 nathanw if (hit) {
1360 1.47.8.2 nathanw SEM_LOCK(dcm);
1361 1.47.8.2 nathanw dcm->dcm_modemchng |= 1<<(unit & 3);
1362 1.47.8.2 nathanw dcm->dcm_cr |= CR_MODM;
1363 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1364 1.47.8.2 nathanw DELAY(10); /* delay until done */
1365 1.47.8.2 nathanw (void) splx(s);
1366 1.47.8.2 nathanw }
1367 1.47.8.2 nathanw return (bits);
1368 1.47.8.2 nathanw }
1369 1.47.8.2 nathanw
1370 1.47.8.2 nathanw /*
1371 1.47.8.2 nathanw * Set board to either interrupt per-character or at a fixed interval.
1372 1.47.8.2 nathanw */
1373 1.47.8.2 nathanw void
1374 1.47.8.2 nathanw dcmsetischeme(brd, flags)
1375 1.47.8.2 nathanw int brd, flags;
1376 1.47.8.2 nathanw {
1377 1.47.8.2 nathanw struct dcm_softc *sc = dcm_cd.cd_devs[brd];
1378 1.47.8.2 nathanw struct dcmdevice *dcm = sc->sc_dcm;
1379 1.47.8.2 nathanw struct dcmischeme *dis = &sc->sc_scheme;
1380 1.47.8.2 nathanw int i;
1381 1.47.8.2 nathanw u_char mask;
1382 1.47.8.2 nathanw int perchar = flags & DIS_PERCHAR;
1383 1.47.8.2 nathanw
1384 1.47.8.2 nathanw #ifdef DEBUG
1385 1.47.8.2 nathanw if (dcmdebug & DDB_INTSCHM)
1386 1.47.8.2 nathanw printf("%s: dcmsetischeme(%d): cur %d, ints %d, chars %d\n",
1387 1.47.8.2 nathanw sc->sc_dev.dv_xname, perchar, dis->dis_perchar,
1388 1.47.8.2 nathanw dis->dis_intr, dis->dis_char);
1389 1.47.8.2 nathanw if ((flags & DIS_RESET) == 0 && perchar == dis->dis_perchar) {
1390 1.47.8.2 nathanw printf("%s: dcmsetischeme: redundent request %d\n",
1391 1.47.8.2 nathanw sc->sc_dev.dv_xname, perchar);
1392 1.47.8.2 nathanw return;
1393 1.47.8.2 nathanw }
1394 1.47.8.2 nathanw #endif
1395 1.47.8.2 nathanw /*
1396 1.47.8.2 nathanw * If perchar is non-zero, we enable interrupts on all characters
1397 1.47.8.2 nathanw * otherwise we disable perchar interrupts and use periodic
1398 1.47.8.2 nathanw * polling interrupts.
1399 1.47.8.2 nathanw */
1400 1.47.8.2 nathanw dis->dis_perchar = perchar;
1401 1.47.8.2 nathanw mask = perchar ? 0xf : 0x0;
1402 1.47.8.2 nathanw for (i = 0; i < 256; i++)
1403 1.47.8.2 nathanw dcm->dcm_bmap[i].data_data = mask;
1404 1.47.8.2 nathanw /*
1405 1.47.8.2 nathanw * Don't slow down tandem mode, interrupt on flow control
1406 1.47.8.2 nathanw * chars for any port on the board.
1407 1.47.8.2 nathanw */
1408 1.47.8.2 nathanw if (!perchar) {
1409 1.47.8.2 nathanw struct tty *tp;
1410 1.47.8.2 nathanw int c;
1411 1.47.8.2 nathanw
1412 1.47.8.2 nathanw for (i = 0; i < NDCMPORT; i++) {
1413 1.47.8.2 nathanw tp = sc->sc_tty[i];
1414 1.47.8.2 nathanw
1415 1.47.8.2 nathanw if ((c = tp->t_cc[VSTART]) != _POSIX_VDISABLE)
1416 1.47.8.2 nathanw dcm->dcm_bmap[c].data_data |= (1 << i);
1417 1.47.8.2 nathanw if ((c = tp->t_cc[VSTOP]) != _POSIX_VDISABLE)
1418 1.47.8.2 nathanw dcm->dcm_bmap[c].data_data |= (1 << i);
1419 1.47.8.2 nathanw }
1420 1.47.8.2 nathanw }
1421 1.47.8.2 nathanw /*
1422 1.47.8.2 nathanw * Board starts with timer disabled so if first call is to
1423 1.47.8.2 nathanw * set perchar mode then we don't want to toggle the timer.
1424 1.47.8.2 nathanw */
1425 1.47.8.2 nathanw if (flags == (DIS_RESET|DIS_PERCHAR))
1426 1.47.8.2 nathanw return;
1427 1.47.8.2 nathanw /*
1428 1.47.8.2 nathanw * Toggle card 16.7ms interrupts (we first make sure that card
1429 1.47.8.2 nathanw * has cleared the bit so it will see the toggle).
1430 1.47.8.2 nathanw */
1431 1.47.8.2 nathanw while (dcm->dcm_cr & CR_TIMER)
1432 1.47.8.2 nathanw ;
1433 1.47.8.2 nathanw SEM_LOCK(dcm);
1434 1.47.8.2 nathanw dcm->dcm_cr |= CR_TIMER;
1435 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1436 1.47.8.2 nathanw }
1437 1.47.8.2 nathanw
1438 1.47.8.2 nathanw void
1439 1.47.8.2 nathanw dcminit(dcm, port, rate)
1440 1.47.8.2 nathanw struct dcmdevice *dcm;
1441 1.47.8.2 nathanw int port, rate;
1442 1.47.8.2 nathanw {
1443 1.47.8.2 nathanw int s, mode;
1444 1.47.8.2 nathanw
1445 1.47.8.2 nathanw mode = LC_8BITS | LC_1STOP;
1446 1.47.8.2 nathanw
1447 1.47.8.2 nathanw s = splhigh();
1448 1.47.8.2 nathanw
1449 1.47.8.2 nathanw /*
1450 1.47.8.2 nathanw * Wait for transmitter buffer to empty.
1451 1.47.8.2 nathanw */
1452 1.47.8.2 nathanw while (dcm->dcm_thead[port].ptr != dcm->dcm_ttail[port].ptr)
1453 1.47.8.2 nathanw DELAY(DCM_USPERCH(rate));
1454 1.47.8.2 nathanw
1455 1.47.8.2 nathanw /*
1456 1.47.8.2 nathanw * Make changes known to hardware.
1457 1.47.8.2 nathanw */
1458 1.47.8.2 nathanw dcm->dcm_data[port].dcm_baud = ttspeedtab(rate, dcmspeedtab);
1459 1.47.8.2 nathanw dcm->dcm_data[port].dcm_conf = mode;
1460 1.47.8.2 nathanw SEM_LOCK(dcm);
1461 1.47.8.2 nathanw dcm->dcm_cmdtab[port].dcm_data |= CT_CON;
1462 1.47.8.2 nathanw dcm->dcm_cr |= (1 << port);
1463 1.47.8.2 nathanw SEM_UNLOCK(dcm);
1464 1.47.8.2 nathanw
1465 1.47.8.2 nathanw /*
1466 1.47.8.2 nathanw * Delay for config change to take place. Weighted by baud.
1467 1.47.8.2 nathanw * XXX why do we do this?
1468 1.47.8.2 nathanw */
1469 1.47.8.2 nathanw DELAY(16 * DCM_USPERCH(rate));
1470 1.47.8.2 nathanw splx(s);
1471 1.47.8.2 nathanw }
1472 1.47.8.2 nathanw
1473 1.47.8.2 nathanw /*
1474 1.47.8.2 nathanw * Empirically derived self-test magic
1475 1.47.8.2 nathanw */
1476 1.47.8.2 nathanw int
1477 1.47.8.2 nathanw dcmselftest(sc)
1478 1.47.8.2 nathanw struct dcm_softc *sc;
1479 1.47.8.2 nathanw {
1480 1.47.8.2 nathanw struct dcmdevice *dcm = sc->sc_dcm;
1481 1.47.8.2 nathanw int timo = 0;
1482 1.47.8.2 nathanw int s, rv;
1483 1.47.8.2 nathanw
1484 1.47.8.2 nathanw rv = 1;
1485 1.47.8.2 nathanw
1486 1.47.8.2 nathanw s = splhigh();
1487 1.47.8.2 nathanw dcm->dcm_rsid = DCMRS;
1488 1.47.8.2 nathanw DELAY(50000); /* 5000 is not long enough */
1489 1.47.8.2 nathanw dcm->dcm_rsid = 0;
1490 1.47.8.2 nathanw dcm->dcm_ic = IC_IE;
1491 1.47.8.2 nathanw dcm->dcm_cr = CR_SELFT;
1492 1.47.8.2 nathanw while ((dcm->dcm_ic & IC_IR) == 0) {
1493 1.47.8.2 nathanw if (++timo == 20000)
1494 1.47.8.2 nathanw goto out;
1495 1.47.8.2 nathanw DELAY(1);
1496 1.47.8.2 nathanw }
1497 1.47.8.2 nathanw DELAY(50000); /* XXX why is this needed ???? */
1498 1.47.8.2 nathanw while ((dcm->dcm_iir & IIR_SELFT) == 0) {
1499 1.47.8.2 nathanw if (++timo == 400000)
1500 1.47.8.2 nathanw goto out;
1501 1.47.8.2 nathanw DELAY(1);
1502 1.47.8.2 nathanw }
1503 1.47.8.2 nathanw DELAY(50000); /* XXX why is this needed ???? */
1504 1.47.8.2 nathanw if (dcm->dcm_stcon != ST_OK) {
1505 1.47.8.2 nathanw #if 0
1506 1.47.8.2 nathanw if (hd->hp_args->hw_sc != conscode)
1507 1.47.8.2 nathanw printf("dcm%d: self test failed: %x\n",
1508 1.47.8.2 nathanw brd, dcm->dcm_stcon);
1509 1.47.8.2 nathanw #endif
1510 1.47.8.2 nathanw goto out;
1511 1.47.8.2 nathanw }
1512 1.47.8.2 nathanw dcm->dcm_ic = IC_ID;
1513 1.47.8.2 nathanw rv = 0;
1514 1.47.8.2 nathanw
1515 1.47.8.2 nathanw out:
1516 1.47.8.2 nathanw splx(s);
1517 1.47.8.2 nathanw return (rv);
1518 1.47.8.2 nathanw }
1519 1.47.8.2 nathanw
1520 1.47.8.2 nathanw /*
1521 1.47.8.2 nathanw * Following are all routines needed for DCM to act as console
1522 1.47.8.2 nathanw */
1523 1.47.8.2 nathanw
1524 1.47.8.2 nathanw int
1525 1.47.8.2 nathanw dcmcnattach(bus_space_tag_t bst, bus_addr_t addr, int scode)
1526 1.47.8.2 nathanw {
1527 1.47.8.2 nathanw bus_space_handle_t bsh;
1528 1.47.8.2 nathanw caddr_t va;
1529 1.47.8.2 nathanw struct dcmdevice *dcm;
1530 1.47.8.2 nathanw
1531 1.47.8.2 nathanw if (bus_space_map(bst, addr, DIOCSIZE, 0, &bsh))
1532 1.47.8.2 nathanw return (1);
1533 1.47.8.2 nathanw
1534 1.47.8.2 nathanw va = bus_space_vaddr(bst, bsh);
1535 1.47.8.2 nathanw dcm = (struct dcmdevice *)va;
1536 1.47.8.2 nathanw
1537 1.47.8.2 nathanw switch (dcm->dcm_rsid) {
1538 1.47.8.2 nathanw #ifdef CONSCODE
1539 1.47.8.2 nathanw case DCMID:
1540 1.47.8.2 nathanw #endif
1541 1.47.8.2 nathanw case DCMID|DCMCON:
1542 1.47.8.2 nathanw break;
1543 1.47.8.2 nathanw default:
1544 1.47.8.2 nathanw goto error;
1545 1.47.8.2 nathanw }
1546 1.47.8.2 nathanw
1547 1.47.8.2 nathanw dcminit(dcm, DCMCONSPORT, dcmdefaultrate);
1548 1.47.8.2 nathanw dcmconsinit = 1;
1549 1.47.8.2 nathanw dcmconscode = scode;
1550 1.47.8.2 nathanw dcm_cn = dcm;
1551 1.47.8.2 nathanw
1552 1.47.8.2 nathanw /* locate the major number */
1553 1.47.8.2 nathanw for (dcmmajor = 0; dcmmajor < nchrdev; dcmmajor++)
1554 1.47.8.2 nathanw if (cdevsw[dcmmajor].d_open == dcmopen)
1555 1.47.8.2 nathanw break;
1556 1.47.8.2 nathanw
1557 1.47.8.2 nathanw /* initialize required fields */
1558 1.47.8.2 nathanw cn_tab = &dcm_cons;
1559 1.47.8.2 nathanw cn_tab->cn_dev = makedev(dcmmajor, 0);
1560 1.47.8.2 nathanw
1561 1.47.8.2 nathanw #ifdef KGDB_CHEAT
1562 1.47.8.2 nathanw /* XXX this needs to be fixed. */
1563 1.47.8.2 nathanw /*
1564 1.47.8.2 nathanw * This doesn't currently work, at least not with ite consoles;
1565 1.47.8.2 nathanw * the console hasn't been initialized yet.
1566 1.47.8.2 nathanw */
1567 1.47.8.2 nathanw if (major(kgdb_dev) == dcmmajor &&
1568 1.47.8.2 nathanw DCMBOARD(DCMUNIT(kgdb_dev)) == DCMBOARD(unit)) {
1569 1.47.8.2 nathanw dcminit(dcm_cn, DCMPORT(DCMUNIT(kgdb_dev)), kgdb_rate);
1570 1.47.8.2 nathanw if (kgdb_debug_init) {
1571 1.47.8.2 nathanw /*
1572 1.47.8.2 nathanw * We assume that console is ready for us...
1573 1.47.8.2 nathanw * this assumes that a dca or ite console
1574 1.47.8.2 nathanw * has been selected already and will init
1575 1.47.8.2 nathanw * on the first putc.
1576 1.47.8.2 nathanw */
1577 1.47.8.2 nathanw printf("dcm%d: ", DCMUNIT(kgdb_dev));
1578 1.47.8.2 nathanw kgdb_connect(1);
1579 1.47.8.2 nathanw }
1580 1.47.8.2 nathanw }
1581 1.47.8.2 nathanw #endif
1582 1.47.8.2 nathanw
1583 1.47.8.2 nathanw
1584 1.47.8.2 nathanw return (0);
1585 1.47.8.2 nathanw
1586 1.47.8.2 nathanw error:
1587 1.47.8.2 nathanw bus_space_unmap(bst, bsh, DIOCSIZE);
1588 1.47.8.2 nathanw return (1);
1589 1.47.8.2 nathanw }
1590 1.47.8.2 nathanw
1591 1.47.8.2 nathanw /* ARGSUSED */
1592 1.47.8.2 nathanw int
1593 1.47.8.2 nathanw dcmcngetc(dev)
1594 1.47.8.2 nathanw dev_t dev;
1595 1.47.8.2 nathanw {
1596 1.47.8.2 nathanw struct dcmrfifo *fifo;
1597 1.47.8.2 nathanw struct dcmpreg *pp;
1598 1.47.8.2 nathanw u_int head;
1599 1.47.8.2 nathanw int s, c, stat;
1600 1.47.8.2 nathanw
1601 1.47.8.2 nathanw pp = dcm_preg(dcm_cn, DCMCONSPORT);
1602 1.47.8.2 nathanw
1603 1.47.8.2 nathanw s = splhigh();
1604 1.47.8.2 nathanw head = pp->r_head & RX_MASK;
1605 1.47.8.2 nathanw fifo = &dcm_cn->dcm_rfifos[3-DCMCONSPORT][head>>1];
1606 1.47.8.2 nathanw while (head == (pp->r_tail & RX_MASK))
1607 1.47.8.2 nathanw ;
1608 1.47.8.2 nathanw /*
1609 1.47.8.2 nathanw * If board interrupts are enabled, just let our received char
1610 1.47.8.2 nathanw * interrupt through in case some other port on the board was
1611 1.47.8.2 nathanw * busy. Otherwise we must clear the interrupt.
1612 1.47.8.2 nathanw */
1613 1.47.8.2 nathanw SEM_LOCK(dcm_cn);
1614 1.47.8.2 nathanw if ((dcm_cn->dcm_ic & IC_IE) == 0)
1615 1.47.8.2 nathanw stat = dcm_cn->dcm_iir;
1616 1.47.8.2 nathanw SEM_UNLOCK(dcm_cn);
1617 1.47.8.2 nathanw c = fifo->data_char;
1618 1.47.8.2 nathanw stat = fifo->data_stat;
1619 1.47.8.2 nathanw pp->r_head = (head + 2) & RX_MASK;
1620 1.47.8.2 nathanw splx(s);
1621 1.47.8.2 nathanw return (c);
1622 1.47.8.2 nathanw }
1623 1.47.8.2 nathanw
1624 1.47.8.2 nathanw /*
1625 1.47.8.2 nathanw * Console kernel output character routine.
1626 1.47.8.2 nathanw */
1627 1.47.8.2 nathanw /* ARGSUSED */
1628 1.47.8.2 nathanw void
1629 1.47.8.2 nathanw dcmcnputc(dev, c)
1630 1.47.8.2 nathanw dev_t dev;
1631 1.47.8.2 nathanw int c;
1632 1.47.8.2 nathanw {
1633 1.47.8.2 nathanw struct dcmpreg *pp;
1634 1.47.8.2 nathanw unsigned tail;
1635 1.47.8.2 nathanw int s, stat;
1636 1.47.8.2 nathanw
1637 1.47.8.2 nathanw pp = dcm_preg(dcm_cn, DCMCONSPORT);
1638 1.47.8.2 nathanw
1639 1.47.8.2 nathanw s = splhigh();
1640 1.47.8.2 nathanw #ifdef KGDB
1641 1.47.8.2 nathanw if (dev != kgdb_dev)
1642 1.47.8.2 nathanw #endif
1643 1.47.8.2 nathanw if (dcmconsinit == 0) {
1644 1.47.8.2 nathanw dcminit(dcm_cn, DCMCONSPORT, dcmdefaultrate);
1645 1.47.8.2 nathanw dcmconsinit = 1;
1646 1.47.8.2 nathanw }
1647 1.47.8.2 nathanw tail = pp->t_tail & TX_MASK;
1648 1.47.8.2 nathanw while (tail != (pp->t_head & TX_MASK))
1649 1.47.8.2 nathanw ;
1650 1.47.8.2 nathanw dcm_cn->dcm_tfifos[3-DCMCONSPORT][tail].data_char = c;
1651 1.47.8.2 nathanw pp->t_tail = tail = (tail + 1) & TX_MASK;
1652 1.47.8.2 nathanw SEM_LOCK(dcm_cn);
1653 1.47.8.2 nathanw dcm_cn->dcm_cmdtab[DCMCONSPORT].dcm_data |= CT_TX;
1654 1.47.8.2 nathanw dcm_cn->dcm_cr |= (1 << DCMCONSPORT);
1655 1.47.8.2 nathanw SEM_UNLOCK(dcm_cn);
1656 1.47.8.2 nathanw while (tail != (pp->t_head & TX_MASK))
1657 1.47.8.2 nathanw ;
1658 1.47.8.2 nathanw /*
1659 1.47.8.2 nathanw * If board interrupts are enabled, just let our completion
1660 1.47.8.2 nathanw * interrupt through in case some other port on the board
1661 1.47.8.2 nathanw * was busy. Otherwise we must clear the interrupt.
1662 1.47.8.2 nathanw */
1663 1.47.8.2 nathanw if ((dcm_cn->dcm_ic & IC_IE) == 0) {
1664 1.47.8.2 nathanw SEM_LOCK(dcm_cn);
1665 1.47.8.2 nathanw stat = dcm_cn->dcm_iir;
1666 1.47.8.2 nathanw SEM_UNLOCK(dcm_cn);
1667 1.47.8.2 nathanw }
1668 1.47.8.2 nathanw splx(s);
1669 1.47.8.2 nathanw }
1670