Home | History | Annotate | Line # | Download | only in dev
dcmreg.h revision 1.5
      1 /*	$NetBSD: dcmreg.h,v 1.5 1996/02/24 00:55:05 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1988 University of Utah.
      5  * Copyright (c) 1982, 1986, 1990, 1993
      6  *	The Regents of the University of California.  All rights reserved.
      7  *
      8  * This code is derived from software contributed to Berkeley by
      9  * the Systems Programming Group of the University of Utah Computer
     10  * Science Department.
     11  *
     12  * Redistribution and use in source and binary forms, with or without
     13  * modification, are permitted provided that the following conditions
     14  * are met:
     15  * 1. Redistributions of source code must retain the above copyright
     16  *    notice, this list of conditions and the following disclaimer.
     17  * 2. Redistributions in binary form must reproduce the above copyright
     18  *    notice, this list of conditions and the following disclaimer in the
     19  *    documentation and/or other materials provided with the distribution.
     20  * 3. All advertising materials mentioning features or use of this software
     21  *    must display the following acknowledgement:
     22  *	This product includes software developed by the University of
     23  *	California, Berkeley and its contributors.
     24  * 4. Neither the name of the University nor the names of its contributors
     25  *    may be used to endorse or promote products derived from this software
     26  *    without specific prior written permission.
     27  *
     28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38  * SUCH DAMAGE.
     39  *
     40  * from: Utah $Hdr: dcmreg.h 1.7 92/01/21$
     41  *
     42  *	@(#)dcmreg.h	8.1 (Berkeley) 6/10/93
     43  */
     44 
     45 #include <hp300/dev/iotypes.h>		/* XXX */
     46 
     47 struct dcmdevice {	   /* host address, only odd bytes addressed */
     48 	u_char	dcm_pad0;
     49 	vu_char	dcm_rsid;		/* Reset / ID			0001 */
     50 	u_char	dcm_pad1;
     51 	vu_char	dcm_ic;			/* Interrupt control register	0003 */
     52 	u_char	dcm_pad2;
     53 	vu_char	dcm_sem;		/* Semaphore register		0005 */
     54 	u_char  dcm_pad3[0x7ffa];	/* Unaddressable	0006-7fff */
     55 	u_char	dcm_pad4;
     56 	vu_char	dcm_iir;		/* Interrupt ident register	8001 */
     57 	u_char	dcm_pad5;
     58 	vu_char	dcm_cr;			/* Command register		8003 */
     59 	u_char  dcm_pad6[0x3fc];	/* Card scratch		8004-83ff */
     60 	struct	dcmrfifo {
     61 		u_char	ptr_pad1;
     62 		vu_char	data_char;
     63 		u_char	ptr_pad2;
     64 		vu_char	data_stat;
     65 	} dcm_rfifos[4][0x80];		/* Receive queues		8400 */
     66 	struct  {
     67 		u_char	ptr_pad1;
     68 		vu_char	data_data;
     69 	} dcm_bmap[0x100];		/* Bitmap table			8c00 */
     70 	struct  {
     71 		u_char	ptr_pad;
     72 		vu_char	ptr;
     73 	} dcm_rhead[4];			/* Fifo head - receive		8e00 */
     74 	struct  {
     75 		u_char  ptr_pad;
     76 		vu_char  ptr;
     77 	} dcm_rtail[4];			/* Fifo tail - receive		8e08 */
     78 	struct  {
     79 		u_char	ptr_pad;
     80 		vu_char	ptr;
     81 	} dcm_thead[4];			/* Fifo head - transmit		8e10 */
     82 	struct  {
     83 		u_char	ptr_pad;
     84 		vu_char	ptr;
     85 	} dcm_ttail[4];			/* Fifo tail - transmit		8e18 */
     86 	struct  {
     87 		u_char	pad1;
     88 		vu_char	dcm_conf;
     89 		u_char	pad2;
     90 		vu_char	dcm_baud;
     91 	} dcm_data[4];			/* Configuration registers	8e20 */
     92 	struct	modemreg {
     93 		u_char	pad0;
     94 		vu_char mdmin;		/* Modem in			8e31 */
     95 		u_char  pad1;
     96 		vu_char mdmout;		/* Modem out			8e33 */
     97 		u_char  pad2;
     98 		vu_char mdmmsk;		/* Modem mask			8e35 */
     99 	} dcm_modem0;
    100 	struct  {
    101 		u_char pad1;
    102 		vu_char dcm_data;
    103 	} dcm_cmdtab[4];		/* Command tables		8e36 */
    104 	struct  {
    105 		u_char pad1;
    106 		vu_char dcm_data;
    107 	} dcm_icrtab[4];		/* Interrupt data		8e3e */
    108 	u_char  dcm_pad10;
    109 	vu_char dcm_stcon;		/* Self test condition		8e47 */
    110 	struct modemreg dcm_modem1;	/* 638 Modem port1		8e48 */
    111 	struct modemreg dcm_modem2;	/* 638 Modem port2		8e4e */
    112 	struct modemreg dcm_modem3;	/* 638 Modem port3		8e54 */
    113 	u_char	dcm_pad11;
    114 	vu_char	dcm_modemchng;		/* 638 Modem change mask	8e5b */
    115 	u_char	dcm_pad12;
    116 	vu_char	dcm_modemintr;		/* 638 Modem interrupt mask	8e5d */
    117 	u_char  dcm_pad13[0x82];	/* Undef Shared Ram	8e5e-8edf */
    118 	struct	dcmtfifo {
    119 	    u_char  ptr_pad1;
    120 	    vu_char  data_char;
    121 	} dcm_tfifos[4][0x10];		/* Transmit queues		8ee0 */
    122 };
    123 
    124 /*
    125  * Overlay structure for port specific queue "registers".
    126  * Starts at offset 0x8E00+(port*2).
    127  */
    128 struct	dcmpreg {
    129 	u_char		pad0;		/* +00 */
    130 	vu_char	r_head;			/* +01 */
    131 	u_char		pad1[7];	/* +02 */
    132 	vu_char	r_tail;			/* +09 */
    133 	u_char		pad2[7];	/* +0A */
    134 	vu_char	t_head;			/* +11 */
    135 	u_char		pad3[7];	/* +12 */
    136 	vu_char	t_tail;			/* +19 */
    137 };
    138 #define	dcm_preg(d, p)	((struct dcmpreg *)((u_int)(d)+0x8e00+(p)*2))
    139 
    140 /* interface reset/id */
    141 #define DCMCON          0x80	/* REMOTE/LOCAL switch, read */
    142 #define	DCMID		0x5	/* hardwired card id, read */
    143 #define	DCMRS		0x80	/* software reset, write */
    144 
    145 /* interrupt control */
    146 #define	DCMIPL(x)	((((x) >> 4) & 3) + 3)	/* interupt level, read */
    147 #define	IC_IR		0x40	/* interupt request, read */
    148 #define	IC_IE		0x80	/* interupt enable, write */
    149 #define	IC_ID		0x00	/* interupt disable, write */
    150 
    151 
    152 /* Semaphore control */
    153 #define	SEM_BSY		0x80	/* read */
    154 #define SEM_CLR         0xFF	/* write */
    155 #define SEM_LOCK(dcm)	while ((dcm)->dcm_sem & SEM_BSY)
    156 #define SEM_UNLOCK(dcm)	(dcm)->dcm_sem = SEM_CLR
    157 
    158 /* command register */
    159 #define	CR_PORT0	0x1
    160 #define	CR_PORT1	0x2
    161 #define	CR_PORT2	0x4
    162 #define	CR_PORT3	0x8
    163 #define	CR_MODM		0x10	/* change modem output lines */
    164 #define	CR_TIMER	0x20	/* 16ms interrupt timer toggle */
    165 #define	CR_SELFT	0x40	/* run self test */
    166 #define CR_MASK		0x7f
    167 
    168 /* interrupt ident register */
    169 #define	IIR_PORT0	0x1
    170 #define	IIR_PORT1	0x2
    171 #define	IIR_PORT2	0x4
    172 #define	IIR_PORT3	0x8
    173 #define	IIR_SELFT	0x10	/* self test completed */
    174 #define	IIR_MODM	0x20	/* change in modem input lines */
    175 #define	IIR_TIMEO	0x40	/* Time out */
    176 #define IIR_MASK	0x7f
    177 
    178 /* self test cond reg */
    179 #define ST_OK           0xe0
    180 
    181 /* Line configuration register */
    182 #define	LC_PNO		0x00
    183 #define	LC_PODD		0x01
    184 #define	LC_PEVEN	0x02
    185 #define	LC_PMSK		0x03
    186 
    187 #define	LC_1STOP	0x00
    188 #define	LC_1HSTOP	0x04
    189 #define	LC_2STOP	0x08
    190 #define	LC_STOPMSK	0x0b
    191 
    192 #define	LC_8BITS	0x30
    193 #define	LC_7BITS	0x20
    194 #define	LC_6BITS	0x10
    195 #define	LC_5BITS	0x00
    196 #define	LC_BITMSK	0x30
    197 
    198 /* baud reg */
    199 #define BR_0		0x00
    200 #define BR_50		0x01
    201 #define BR_75		0x02
    202 #define BR_110		0x03
    203 #define BR_134  	0x04
    204 #define BR_150		0x05
    205 #define BR_300		0x06
    206 #define BR_600		0x07
    207 #define BR_900		0x08
    208 #define BR_1200		0x09
    209 #define BR_1800		0x0a
    210 #define BR_2400		0x0b
    211 #define BR_3600		0x0c
    212 #define BR_4800		0x0d
    213 #define BR_7200		0x0e
    214 #define BR_9600		0x0f
    215 #define BR_19200	0x10
    216 #define BR_38400	0x11
    217 
    218 /* modem input register */
    219 #define	MI_CTS		0x08
    220 #define	MI_DM		0x04
    221 #define	MI_CD		0x02
    222 #define	MI_RI		0x01
    223 
    224 /* modem output register */
    225 #define	MO_SR		0x04
    226 #define	MO_DTR		0x02
    227 #define	MO_RTS		0x01
    228 #define	MO_ON		((MO_DTR) | (MO_RTS))
    229 #define	MO_OFF		0x00
    230 
    231 /* cmd-tab values, write */
    232 #define CT_CON		0x1	/* configuration change */
    233 #define CT_TX		0x2	/* transmit buffer not empty */
    234 #define CT_BRK		0x4	/* toggle BREAK */
    235 
    236 /* icr-tab values, read */
    237 #define IT_TX		0x1	/* transmit buffer empty */
    238 #define IT_SPEC		0x2	/* special character received */
    239 
    240 /* data errors */
    241 #define RD_OVF		0x08
    242 #define RD_BD		0x10
    243 #define RD_PE		0x20
    244 #define RD_OE		0x40
    245 #define RD_FE		0x80
    246 #define RD_MASK		0xf8
    247 
    248 /* Transmit/Receive masks */
    249 #define TX_MASK		0x0f
    250 #define RX_MASK		0xff
    251 
    252 /*
    253  * DCM console caveat: only port 1 is affected by the remote switch, and
    254  * thus the only supported console port on a given DCM card.
    255  */
    256 #define DCMCONSPORT	1
    257