dmareg.h revision 1.13 1 1.13 agc /* $NetBSD: dmareg.h,v 1.13 2003/08/07 16:27:28 agc Exp $ */
2 1.4 cgd
3 1.1 cgd /*
4 1.3 mycroft * Copyright (c) 1982, 1990, 1993
5 1.3 mycroft * The Regents of the University of California. All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Redistribution and use in source and binary forms, with or without
8 1.1 cgd * modification, are permitted provided that the following conditions
9 1.1 cgd * are met:
10 1.1 cgd * 1. Redistributions of source code must retain the above copyright
11 1.1 cgd * notice, this list of conditions and the following disclaimer.
12 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 cgd * notice, this list of conditions and the following disclaimer in the
14 1.1 cgd * documentation and/or other materials provided with the distribution.
15 1.13 agc * 3. Neither the name of the University nor the names of its contributors
16 1.1 cgd * may be used to endorse or promote products derived from this software
17 1.1 cgd * without specific prior written permission.
18 1.1 cgd *
19 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 1.1 cgd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 cgd * SUCH DAMAGE.
30 1.1 cgd *
31 1.4 cgd * @(#)dmareg.h 8.1 (Berkeley) 6/10/93
32 1.1 cgd */
33 1.1 cgd
34 1.3 mycroft #include <hp300/dev/iotypes.h> /* XXX */
35 1.11 thorpej #include <machine/hp300spu.h>
36 1.3 mycroft
37 1.1 cgd /*
38 1.1 cgd * Hardware layout for the 98620[ABC]:
39 1.1 cgd * 98620A (old 320s?): byte/word DMA in up to 64K chunks
40 1.1 cgd * 98620B (320s only): 98620A with programmable IPL
41 1.1 cgd * 98620C (all others): byte/word/longword DMA in up to 4Gb chunks
42 1.1 cgd */
43 1.1 cgd
44 1.1 cgd struct dmaBdevice {
45 1.1 cgd v_char *dmaB_addr;
46 1.1 cgd vu_short dmaB_count;
47 1.1 cgd vu_short dmaB_cmd;
48 1.1 cgd #define dmaB_stat dmaB_cmd
49 1.1 cgd };
50 1.1 cgd
51 1.1 cgd struct dmadevice {
52 1.1 cgd v_char *dma_addr;
53 1.1 cgd vu_int dma_count;
54 1.1 cgd vu_short dma_cmd;
55 1.1 cgd vu_short dma_stat;
56 1.1 cgd };
57 1.1 cgd
58 1.1 cgd struct dmareg {
59 1.1 cgd struct dmaBdevice dma_Bchan0;
60 1.1 cgd struct dmaBdevice dma_Bchan1;
61 1.1 cgd /* the rest are 98620C specific */
62 1.1 cgd v_char dma_id[4];
63 1.1 cgd vu_char dma_cr;
64 1.1 cgd char dma_pad1[0xEB];
65 1.1 cgd struct dmadevice dma_chan0;
66 1.1 cgd char dma_pad2[0xF4];
67 1.1 cgd struct dmadevice dma_chan1;
68 1.1 cgd };
69 1.1 cgd
70 1.6 thorpej /* The hp300 has 2 DMA channels. */
71 1.6 thorpej #define NDMACHAN 2
72 1.1 cgd
73 1.1 cgd /* addresses */
74 1.1 cgd #define DMA_BASE IIOV(0x500000)
75 1.1 cgd
76 1.1 cgd /* command bits */
77 1.1 cgd #define DMA_ENAB 0x0001
78 1.1 cgd #define DMA_WORD 0x0002
79 1.1 cgd #define DMA_WRT 0x0004
80 1.1 cgd #define DMA_PRI 0x0008
81 1.1 cgd #define DMA_IPL(x) (((x) - 3) << 4)
82 1.1 cgd #define DMA_LWORD 0x0100
83 1.1 cgd #define DMA_START 0x8000
84 1.1 cgd
85 1.1 cgd /* status bits */
86 1.1 cgd #define DMA_ARMED 0x01
87 1.1 cgd #define DMA_INTR 0x02
88 1.1 cgd #define DMA_ACC 0x04
89 1.1 cgd #define DMA_HALT 0x08
90 1.1 cgd #define DMA_BERR 0x10
91 1.1 cgd #define DMA_ALIGN 0x20
92 1.1 cgd #define DMA_WRAP 0x40
93 1.1 cgd
94 1.5 jtc #ifdef _KERNEL
95 1.1 cgd /*
96 1.1 cgd * Macros to attempt to hide the HW differences between the 98620B DMA
97 1.1 cgd * board and the 1TQ4-0401 DMA chip (68020C "board"). The latter
98 1.1 cgd * includes emulation registers for the former but you need to access
99 1.1 cgd * the "native-mode" registers directly in order to do 32-bit DMA.
100 1.1 cgd *
101 1.1 cgd * DMA_CLEAR: Clear interrupt on DMA board. We just use the
102 1.1 cgd * emulation registers on the 98620C as that is easiest.
103 1.1 cgd * DMA_STAT: Read status register. Again, we always read the
104 1.1 cgd * emulation register. Someday we might want to
105 1.1 cgd * look at the 98620C status to get the extended bits.
106 1.1 cgd * DMA_ARM: Load address, count and kick-off DMA.
107 1.1 cgd */
108 1.10 scottr #define DMA_CLEAR(dc) do { \
109 1.10 scottr v_int dmaclr; \
110 1.10 scottr dmaclr = (int)dc->dm_Bhwaddr->dmaB_addr; \
111 1.10 scottr } while (0);
112 1.6 thorpej #define DMA_STAT(dc) dc->dm_Bhwaddr->dmaB_stat
113 1.1 cgd
114 1.1 cgd #if defined(HP320)
115 1.12 thorpej #define DMA_ARM(sc, dc) \
116 1.12 thorpej if (sc->sc_type == DMA_B) { \
117 1.9 scottr struct dmaBdevice *dma = dc->dm_Bhwaddr; \
118 1.8 thorpej dma->dmaB_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
119 1.8 thorpej dma->dmaB_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
120 1.6 thorpej dma->dmaB_cmd = dc->dm_cmd; \
121 1.1 cgd } else { \
122 1.9 scottr struct dmadevice *dma = dc->dm_hwaddr; \
123 1.8 thorpej dma->dma_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
124 1.8 thorpej dma->dma_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
125 1.6 thorpej dma->dma_cmd = dc->dm_cmd; \
126 1.1 cgd }
127 1.1 cgd #else
128 1.12 thorpej #define DMA_ARM(sc, dc) \
129 1.1 cgd { \
130 1.9 scottr struct dmadevice *dma = dc->dm_hwaddr; \
131 1.8 thorpej dma->dma_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
132 1.8 thorpej dma->dma_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
133 1.6 thorpej dma->dma_cmd = dc->dm_cmd; \
134 1.1 cgd }
135 1.1 cgd #endif
136 1.1 cgd #endif
137