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if_lereg.h revision 1.1
      1  1.1  cgd /*
      2  1.1  cgd  * Copyright (c) 1982, 1990 The Regents of the University of California.
      3  1.1  cgd  * All rights reserved.
      4  1.1  cgd  *
      5  1.1  cgd  * Redistribution and use in source and binary forms, with or without
      6  1.1  cgd  * modification, are permitted provided that the following conditions
      7  1.1  cgd  * are met:
      8  1.1  cgd  * 1. Redistributions of source code must retain the above copyright
      9  1.1  cgd  *    notice, this list of conditions and the following disclaimer.
     10  1.1  cgd  * 2. Redistributions in binary form must reproduce the above copyright
     11  1.1  cgd  *    notice, this list of conditions and the following disclaimer in the
     12  1.1  cgd  *    documentation and/or other materials provided with the distribution.
     13  1.1  cgd  * 3. All advertising materials mentioning features or use of this software
     14  1.1  cgd  *    must display the following acknowledgement:
     15  1.1  cgd  *	This product includes software developed by the University of
     16  1.1  cgd  *	California, Berkeley and its contributors.
     17  1.1  cgd  * 4. Neither the name of the University nor the names of its contributors
     18  1.1  cgd  *    may be used to endorse or promote products derived from this software
     19  1.1  cgd  *    without specific prior written permission.
     20  1.1  cgd  *
     21  1.1  cgd  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     22  1.1  cgd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     23  1.1  cgd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     24  1.1  cgd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     25  1.1  cgd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     26  1.1  cgd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     27  1.1  cgd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     28  1.1  cgd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     29  1.1  cgd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     30  1.1  cgd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     31  1.1  cgd  * SUCH DAMAGE.
     32  1.1  cgd  *
     33  1.1  cgd  *	@(#)if_lereg.h	7.1 (Berkeley) 5/8/90
     34  1.1  cgd  */
     35  1.1  cgd 
     36  1.1  cgd #define	LEID		21
     37  1.1  cgd 
     38  1.1  cgd #define	LEMTU		1518
     39  1.1  cgd #define	LEMINSIZE	60	/* should be 64 if mode DTCR is set */
     40  1.1  cgd #define	LERBUF		8
     41  1.1  cgd #define	LERBUFLOG2	3
     42  1.1  cgd #define	LE_RLEN		(LERBUFLOG2 << 13)
     43  1.1  cgd #define	LETBUF		1
     44  1.1  cgd #define	LETBUFLOG2	0
     45  1.1  cgd #define	LE_TLEN		(LETBUFLOG2 << 13)
     46  1.1  cgd 
     47  1.1  cgd #define vu_char		volatile u_char
     48  1.1  cgd 
     49  1.1  cgd /*
     50  1.1  cgd  * LANCE registers.
     51  1.1  cgd  */
     52  1.1  cgd struct lereg0 {
     53  1.1  cgd 	u_char	ler0_pad0;
     54  1.1  cgd 	vu_char	ler0_id;	/* ID */
     55  1.1  cgd 	u_char	ler0_pad1;
     56  1.1  cgd 	vu_char	ler0_status;	/* interrupt enable/status */
     57  1.1  cgd };
     58  1.1  cgd 
     59  1.1  cgd struct lereg1 {
     60  1.1  cgd 	u_short	ler1_rdp;	/* data port */
     61  1.1  cgd 	u_short	ler1_rap;	/* register select port */
     62  1.1  cgd };
     63  1.1  cgd 
     64  1.1  cgd /*
     65  1.1  cgd  * Overlayed on 16K dual-port RAM.
     66  1.1  cgd  * Current size is 13,758 bytes with 8 x 1518 receive buffers and
     67  1.1  cgd  * 1 x 1518 transmit buffer.
     68  1.1  cgd  */
     69  1.1  cgd struct lereg2 {
     70  1.1  cgd 	/* init block */
     71  1.1  cgd 	u_short	ler2_mode;		/* +0x0000 */
     72  1.1  cgd 	u_char	ler2_padr[6];		/* +0x0002 */
     73  1.1  cgd 	u_long	ler2_ladrf0;		/* +0x0008 */
     74  1.1  cgd 	u_long	ler2_ladrf1;		/* +0x000C */
     75  1.1  cgd 	u_short	ler2_rdra;		/* +0x0010 */
     76  1.1  cgd 	u_short	ler2_rlen;		/* +0x0012 */
     77  1.1  cgd 	u_short	ler2_tdra;		/* +0x0014 */
     78  1.1  cgd 	u_short	ler2_tlen;		/* +0x0016 */
     79  1.1  cgd 	/* receive message descriptors */
     80  1.1  cgd 	struct	lermd {			/* +0x0018 */
     81  1.1  cgd 		u_short	rmd0;
     82  1.1  cgd 		u_short	rmd1;
     83  1.1  cgd 		short	rmd2;
     84  1.1  cgd 		u_short	rmd3;
     85  1.1  cgd 	} ler2_rmd[LERBUF];
     86  1.1  cgd 	/* transmit message descriptors */
     87  1.1  cgd 	struct	letmd {			/* +0x0058 */
     88  1.1  cgd 		u_short	tmd0;
     89  1.1  cgd 		u_short	tmd1;
     90  1.1  cgd 		short	tmd2;
     91  1.1  cgd 		u_short	tmd3;
     92  1.1  cgd 	} ler2_tmd[LETBUF];
     93  1.1  cgd 	char	ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */
     94  1.1  cgd 	char	ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD0 */
     95  1.1  cgd };
     96  1.1  cgd 
     97  1.1  cgd /*
     98  1.1  cgd  * Control and status bits -- lereg0
     99  1.1  cgd  */
    100  1.1  cgd #define	LE_IE		0x80		/* interrupt enable */
    101  1.1  cgd #define	LE_IR		0x40		/* interrupt requested */
    102  1.1  cgd #define	LE_LOCK		0x08		/* lock status register */
    103  1.1  cgd #define	LE_ACK		0x04		/* ack of lock */
    104  1.1  cgd #define	LE_JAB		0x02		/* loss of tx clock (???) */
    105  1.1  cgd #define LE_IPL(x)	((((x) >> 4) & 0x3) + 3)
    106  1.1  cgd 
    107  1.1  cgd /*
    108  1.1  cgd  * Control and status bits -- lereg1
    109  1.1  cgd  */
    110  1.1  cgd #define	LE_CSR0		0
    111  1.1  cgd #define	LE_CSR1		1
    112  1.1  cgd #define	LE_CSR2		2
    113  1.1  cgd #define	LE_CSR3		3
    114  1.1  cgd 
    115  1.1  cgd #define	LE_SERR		0x8000
    116  1.1  cgd #define	LE_BABL		0x4000
    117  1.1  cgd #define	LE_CERR		0x2000
    118  1.1  cgd #define	LE_MISS		0x1000
    119  1.1  cgd #define	LE_MERR		0x0800
    120  1.1  cgd #define	LE_RINT		0x0400
    121  1.1  cgd #define	LE_TINT		0x0200
    122  1.1  cgd #define	LE_IDON		0x0100
    123  1.1  cgd #define	LE_INTR		0x0080
    124  1.1  cgd #define	LE_INEA		0x0040
    125  1.1  cgd #define	LE_RXON		0x0020
    126  1.1  cgd #define	LE_TXON		0x0010
    127  1.1  cgd #define	LE_TDMD		0x0008
    128  1.1  cgd #define	LE_STOP		0x0004
    129  1.1  cgd #define	LE_STRT		0x0002
    130  1.1  cgd #define	LE_INIT		0x0001
    131  1.1  cgd 
    132  1.1  cgd #define	LE_BSWP		0x4
    133  1.1  cgd #define	LE_MODE		0x0
    134  1.1  cgd 
    135  1.1  cgd /*
    136  1.1  cgd  * Control and status bits -- lereg2
    137  1.1  cgd  */
    138  1.1  cgd #define	LE_OWN		0x8000
    139  1.1  cgd #define	LE_ERR		0x4000
    140  1.1  cgd #define	LE_STP		0x0200
    141  1.1  cgd #define	LE_ENP		0x0100
    142  1.1  cgd 
    143  1.1  cgd #define	LE_FRAM		0x2000
    144  1.1  cgd #define	LE_OFLO		0x1000
    145  1.1  cgd #define	LE_CRC		0x0800
    146  1.1  cgd #define	LE_RBUFF	0x0400
    147  1.1  cgd #define	LE_MORE		0x1000
    148  1.1  cgd #define	LE_ONE		0x0800
    149  1.1  cgd #define	LE_DEF		0x0400
    150  1.1  cgd #define	LE_TBUFF	0x8000
    151  1.1  cgd #define	LE_UFLO		0x4000
    152  1.1  cgd #define	LE_LCOL		0x1000
    153  1.1  cgd #define	LE_LCAR		0x0800
    154  1.1  cgd #define	LE_RTRY		0x0400
    155