cacheops_machdep.h revision 1.1 1 1.1 chs /* $NetBSD: cacheops_machdep.h,v 1.1 2002/11/02 20:03:05 chs Exp $ */
2 1.1 chs
3 1.1 chs /*
4 1.1 chs * Copyright (c) 1994, 1995 Gordon W. Ross
5 1.1 chs * Copyright (c) 1988 University of Utah.
6 1.1 chs * Copyright (c) 1980, 1990, 1993
7 1.1 chs * The Regents of the University of California. All rights reserved.
8 1.1 chs *
9 1.1 chs * This code is derived from software contributed to Berkeley by
10 1.1 chs * the Systems Programming Group of the University of Utah Computer
11 1.1 chs * Science Department.
12 1.1 chs *
13 1.1 chs * Redistribution and use in source and binary forms, with or without
14 1.1 chs * modification, are permitted provided that the following conditions
15 1.1 chs * are met:
16 1.1 chs * 1. Redistributions of source code must retain the above copyright
17 1.1 chs * notice, this list of conditions and the following disclaimer.
18 1.1 chs * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 chs * notice, this list of conditions and the following disclaimer in the
20 1.1 chs * documentation and/or other materials provided with the distribution.
21 1.1 chs * 3. All advertising materials mentioning features or use of this software
22 1.1 chs * must display the following acknowledgement:
23 1.1 chs * This product includes software developed by the University of
24 1.1 chs * California, Berkeley and its contributors.
25 1.1 chs * 4. Neither the name of the University nor the names of its contributors
26 1.1 chs * may be used to endorse or promote products derived from this software
27 1.1 chs * without specific prior written permission.
28 1.1 chs *
29 1.1 chs * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 1.1 chs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 1.1 chs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 1.1 chs * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 1.1 chs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 1.1 chs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 1.1 chs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 1.1 chs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 1.1 chs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 1.1 chs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 1.1 chs * SUCH DAMAGE.
40 1.1 chs */
41 1.1 chs
42 1.1 chs #ifndef _HP300_CACHEOPS_MACHDEP_H_
43 1.1 chs #define _HP300_CACHEOPS_MACHDEP_H_
44 1.1 chs
45 1.1 chs extern vaddr_t MMUbase;
46 1.1 chs
47 1.1 chs int DCIA_md(void);
48 1.1 chs extern __inline int
49 1.1 chs DCIA_md(void)
50 1.1 chs {
51 1.1 chs volatile int *ip = (void *)(MMUbase + MMUCMD);
52 1.1 chs
53 1.1 chs if (ectype != EC_VIRT) {
54 1.1 chs return 0;
55 1.1 chs }
56 1.1 chs
57 1.1 chs *ip &= ~MMU_CEN;
58 1.1 chs *ip |= MMU_CEN;
59 1.1 chs return 1;
60 1.1 chs }
61 1.1 chs
62 1.1 chs int DCIS_md(void);
63 1.1 chs extern __inline int
64 1.1 chs DCIS_md(void)
65 1.1 chs {
66 1.1 chs volatile int *ip = (void *)(MMUbase + MMUSSTP);
67 1.1 chs
68 1.1 chs if (ectype != EC_VIRT) {
69 1.1 chs return 0;
70 1.1 chs }
71 1.1 chs
72 1.1 chs *ip = *ip;
73 1.1 chs return 1;
74 1.1 chs }
75 1.1 chs
76 1.1 chs int DCIU_md(void);
77 1.1 chs extern __inline int
78 1.1 chs DCIU_md(void)
79 1.1 chs {
80 1.1 chs volatile int *ip = (void *)(MMUbase + MMUUSTP);
81 1.1 chs
82 1.1 chs if (ectype != EC_VIRT) {
83 1.1 chs return 0;
84 1.1 chs }
85 1.1 chs
86 1.1 chs *ip = *ip;
87 1.1 chs return 1;
88 1.1 chs }
89 1.1 chs
90 1.1 chs int PCIA_md(void);
91 1.1 chs extern __inline int
92 1.1 chs PCIA_md(void)
93 1.1 chs {
94 1.1 chs volatile int *ip = (void *)(MMUbase + MMUCMD);
95 1.1 chs
96 1.1 chs if (ectype != EC_PHYS || cputype != CPU_68030) {
97 1.1 chs return 0;
98 1.1 chs }
99 1.1 chs
100 1.1 chs *ip &= ~MMU_CEN;
101 1.1 chs *ip |= MMU_CEN;
102 1.1 chs
103 1.1 chs /*
104 1.1 chs * only some '030 models (345/370/375/400) have external PAC,
105 1.1 chs * so we need to do the standard flushing as well.
106 1.1 chs */
107 1.1 chs
108 1.1 chs return 0;
109 1.1 chs }
110 1.1 chs
111 1.1 chs int TBIA_md(void);
112 1.1 chs extern __inline int
113 1.1 chs TBIA_md(void)
114 1.1 chs {
115 1.1 chs volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
116 1.1 chs
117 1.1 chs if (mmutype != MMU_HP) {
118 1.1 chs return 0;
119 1.1 chs }
120 1.1 chs
121 1.1 chs (void) *ip;
122 1.1 chs return 1;
123 1.1 chs }
124 1.1 chs
125 1.1 chs int TBIS_md(vaddr_t);
126 1.1 chs extern __inline int
127 1.1 chs TBIS_md(vaddr_t va)
128 1.1 chs {
129 1.1 chs vaddr_t r_va __asm("%a0") = va;
130 1.1 chs int s;
131 1.1 chs
132 1.1 chs if (mmutype != MMU_HP) {
133 1.1 chs return 0;
134 1.1 chs }
135 1.1 chs
136 1.1 chs s = splhigh();
137 1.1 chs __asm __volatile (" movc %0, %%dfc;" /* select purge space */
138 1.1 chs " movsl %3, %1@;" /* purge it */
139 1.1 chs " movc %2, %%dfc;"
140 1.1 chs : : "r" (FC_PURGE), "a" (r_va), "r" (FC_USERD),
141 1.1 chs "r" (0));
142 1.1 chs splx(s);
143 1.1 chs return 1;
144 1.1 chs }
145 1.1 chs
146 1.1 chs int TBIAS_md(void);
147 1.1 chs extern __inline int
148 1.1 chs TBIAS_md(void)
149 1.1 chs {
150 1.1 chs volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
151 1.1 chs
152 1.1 chs if (mmutype != MMU_HP) {
153 1.1 chs return 0;
154 1.1 chs }
155 1.1 chs
156 1.1 chs *ip = 0x8000;
157 1.1 chs return 1;
158 1.1 chs }
159 1.1 chs
160 1.1 chs int TBIAU_md(void);
161 1.1 chs extern __inline int
162 1.1 chs TBIAU_md(void)
163 1.1 chs {
164 1.1 chs volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
165 1.1 chs
166 1.1 chs if (mmutype != MMU_HP) {
167 1.1 chs return 0;
168 1.1 chs }
169 1.1 chs
170 1.1 chs *ip = 0;
171 1.1 chs return 1;
172 1.1 chs }
173 1.1 chs #endif /* _HP300_CACHEOPS_MACHDEP_H_ */
174