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cacheops_machdep.h revision 1.2.8.2
      1  1.2.8.1  skrll /*	$NetBSD: cacheops_machdep.h,v 1.2.8.2 2004/09/18 14:34:19 skrll Exp $	*/
      2      1.1    chs 
      3      1.1    chs /*
      4      1.1    chs  * Copyright (c) 1980, 1990, 1993
      5      1.1    chs  *	The Regents of the University of California.  All rights reserved.
      6      1.1    chs  *
      7      1.1    chs  * This code is derived from software contributed to Berkeley by
      8      1.1    chs  * the Systems Programming Group of the University of Utah Computer
      9      1.1    chs  * Science Department.
     10      1.1    chs  *
     11      1.1    chs  * Redistribution and use in source and binary forms, with or without
     12      1.1    chs  * modification, are permitted provided that the following conditions
     13      1.1    chs  * are met:
     14      1.1    chs  * 1. Redistributions of source code must retain the above copyright
     15      1.1    chs  *    notice, this list of conditions and the following disclaimer.
     16      1.1    chs  * 2. Redistributions in binary form must reproduce the above copyright
     17      1.1    chs  *    notice, this list of conditions and the following disclaimer in the
     18      1.1    chs  *    documentation and/or other materials provided with the distribution.
     19  1.2.8.1  skrll  * 3. Neither the name of the University nor the names of its contributors
     20  1.2.8.1  skrll  *    may be used to endorse or promote products derived from this software
     21  1.2.8.1  skrll  *    without specific prior written permission.
     22  1.2.8.1  skrll  *
     23  1.2.8.1  skrll  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     24  1.2.8.1  skrll  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     25  1.2.8.1  skrll  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     26  1.2.8.1  skrll  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     27  1.2.8.1  skrll  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     28  1.2.8.1  skrll  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     29  1.2.8.1  skrll  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     30  1.2.8.1  skrll  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     31  1.2.8.1  skrll  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     32  1.2.8.1  skrll  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     33  1.2.8.1  skrll  * SUCH DAMAGE.
     34  1.2.8.1  skrll  */
     35  1.2.8.1  skrll 
     36  1.2.8.1  skrll /*
     37  1.2.8.1  skrll  * Copyright (c) 1994, 1995 Gordon W. Ross
     38  1.2.8.1  skrll  * Copyright (c) 1988 University of Utah.
     39  1.2.8.1  skrll  *
     40  1.2.8.1  skrll  * This code is derived from software contributed to Berkeley by
     41  1.2.8.1  skrll  * the Systems Programming Group of the University of Utah Computer
     42  1.2.8.1  skrll  * Science Department.
     43  1.2.8.1  skrll  *
     44  1.2.8.1  skrll  * Redistribution and use in source and binary forms, with or without
     45  1.2.8.1  skrll  * modification, are permitted provided that the following conditions
     46  1.2.8.1  skrll  * are met:
     47  1.2.8.1  skrll  * 1. Redistributions of source code must retain the above copyright
     48  1.2.8.1  skrll  *    notice, this list of conditions and the following disclaimer.
     49  1.2.8.1  skrll  * 2. Redistributions in binary form must reproduce the above copyright
     50  1.2.8.1  skrll  *    notice, this list of conditions and the following disclaimer in the
     51  1.2.8.1  skrll  *    documentation and/or other materials provided with the distribution.
     52      1.1    chs  * 3. All advertising materials mentioning features or use of this software
     53      1.1    chs  *    must display the following acknowledgement:
     54      1.1    chs  *	This product includes software developed by the University of
     55      1.1    chs  *	California, Berkeley and its contributors.
     56      1.1    chs  * 4. Neither the name of the University nor the names of its contributors
     57      1.1    chs  *    may be used to endorse or promote products derived from this software
     58      1.1    chs  *    without specific prior written permission.
     59      1.1    chs  *
     60      1.1    chs  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     61      1.1    chs  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     62      1.1    chs  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     63      1.1    chs  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     64      1.1    chs  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     65      1.1    chs  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     66      1.1    chs  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     67      1.1    chs  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     68      1.1    chs  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     69      1.1    chs  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     70      1.1    chs  * SUCH DAMAGE.
     71      1.1    chs  */
     72      1.1    chs 
     73      1.1    chs #ifndef _HP300_CACHEOPS_MACHDEP_H_
     74      1.1    chs #define	_HP300_CACHEOPS_MACHDEP_H_
     75      1.1    chs 
     76      1.1    chs extern vaddr_t MMUbase;
     77      1.1    chs 
     78      1.2    chs static __inline int __attribute__((__unused__))
     79      1.1    chs DCIA_md(void)
     80      1.1    chs {
     81      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUCMD);
     82      1.1    chs 
     83      1.1    chs 	if (ectype != EC_VIRT) {
     84      1.1    chs 		return 0;
     85      1.1    chs 	}
     86      1.1    chs 
     87      1.1    chs 	*ip &= ~MMU_CEN;
     88      1.1    chs 	*ip |= MMU_CEN;
     89      1.1    chs 	return 1;
     90      1.1    chs }
     91      1.1    chs 
     92      1.2    chs static __inline int __attribute__((__unused__))
     93      1.1    chs DCIS_md(void)
     94      1.1    chs {
     95      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUSSTP);
     96      1.1    chs 
     97      1.1    chs 	if (ectype != EC_VIRT) {
     98      1.1    chs 		return 0;
     99      1.1    chs 	}
    100      1.1    chs 
    101      1.1    chs 	*ip = *ip;
    102      1.1    chs 	return 1;
    103      1.1    chs }
    104      1.1    chs 
    105      1.2    chs static __inline int __attribute__((__unused__))
    106      1.1    chs DCIU_md(void)
    107      1.1    chs {
    108      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUUSTP);
    109      1.1    chs 
    110      1.1    chs 	if (ectype != EC_VIRT) {
    111      1.1    chs 		return 0;
    112      1.1    chs 	}
    113      1.1    chs 
    114      1.1    chs 	*ip = *ip;
    115      1.1    chs 	return 1;
    116      1.1    chs }
    117      1.1    chs 
    118      1.2    chs static __inline int __attribute__((__unused__))
    119      1.1    chs PCIA_md(void)
    120      1.1    chs {
    121      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUCMD);
    122      1.1    chs 
    123      1.1    chs 	if (ectype != EC_PHYS || cputype != CPU_68030) {
    124      1.1    chs 		return 0;
    125      1.1    chs 	}
    126      1.1    chs 
    127      1.1    chs 	*ip &= ~MMU_CEN;
    128      1.1    chs 	*ip |= MMU_CEN;
    129      1.1    chs 
    130      1.1    chs 	/*
    131      1.1    chs 	 * only some '030 models (345/370/375/400) have external PAC,
    132      1.1    chs 	 * so we need to do the standard flushing as well.
    133      1.1    chs 	 */
    134      1.1    chs 
    135      1.1    chs 	return 0;
    136      1.1    chs }
    137      1.1    chs 
    138      1.2    chs static __inline int __attribute__((__unused__))
    139      1.1    chs TBIA_md(void)
    140      1.1    chs {
    141      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
    142      1.1    chs 
    143      1.1    chs 	if (mmutype != MMU_HP) {
    144      1.1    chs 		return 0;
    145      1.1    chs 	}
    146      1.1    chs 
    147      1.1    chs 	(void) *ip;
    148      1.1    chs 	return 1;
    149      1.1    chs }
    150      1.1    chs 
    151      1.2    chs static __inline int __attribute__((__unused__))
    152      1.1    chs TBIS_md(vaddr_t va)
    153      1.1    chs {
    154  1.2.8.1  skrll 	register vaddr_t r_va __asm("%a1") = va;
    155      1.1    chs 	int s;
    156      1.1    chs 
    157      1.1    chs 	if (mmutype != MMU_HP) {
    158      1.1    chs 		return 0;
    159      1.1    chs 	}
    160      1.1    chs 
    161      1.1    chs 	s = splhigh();
    162      1.1    chs 	__asm __volatile (" movc   %0, %%dfc;"	/* select purge space */
    163      1.1    chs 			  " movsl  %3, %1@;"	/* purge it */
    164      1.1    chs 			  " movc   %2, %%dfc;"
    165      1.1    chs 			  : : "r" (FC_PURGE), "a" (r_va), "r" (FC_USERD),
    166      1.1    chs 			  "r" (0));
    167      1.1    chs 	splx(s);
    168      1.1    chs 	return 1;
    169      1.1    chs }
    170      1.1    chs 
    171      1.2    chs static __inline int __attribute__((__unused__))
    172      1.1    chs TBIAS_md(void)
    173      1.1    chs {
    174      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
    175      1.1    chs 
    176      1.1    chs 	if (mmutype != MMU_HP) {
    177      1.1    chs 		return 0;
    178      1.1    chs 	}
    179      1.1    chs 
    180      1.1    chs 	*ip = 0x8000;
    181      1.1    chs 	return 1;
    182      1.1    chs }
    183      1.1    chs 
    184      1.2    chs static __inline int __attribute__((__unused__))
    185      1.1    chs TBIAU_md(void)
    186      1.1    chs {
    187      1.1    chs 	volatile int *ip = (void *)(MMUbase + MMUTBINVAL);
    188      1.1    chs 
    189      1.1    chs 	if (mmutype != MMU_HP) {
    190      1.1    chs 		return 0;
    191      1.1    chs 	}
    192      1.1    chs 
    193      1.1    chs 	*ip = 0;
    194      1.1    chs 	return 1;
    195      1.1    chs }
    196      1.1    chs #endif /* _HP300_CACHEOPS_MACHDEP_H_ */
    197