cpu.h revision 1.42 1 1.42 agc /* $NetBSD: cpu.h,v 1.42 2003/08/07 16:27:39 agc Exp $ */
2 1.9 cgd
3 1.1 cgd /*
4 1.8 mycroft * Copyright (c) 1982, 1990, 1993
5 1.8 mycroft * The Regents of the University of California. All rights reserved.
6 1.42 agc *
7 1.42 agc * This code is derived from software contributed to Berkeley by
8 1.42 agc * the Systems Programming Group of the University of Utah Computer
9 1.42 agc * Science Department.
10 1.42 agc *
11 1.42 agc * Redistribution and use in source and binary forms, with or without
12 1.42 agc * modification, are permitted provided that the following conditions
13 1.42 agc * are met:
14 1.42 agc * 1. Redistributions of source code must retain the above copyright
15 1.42 agc * notice, this list of conditions and the following disclaimer.
16 1.42 agc * 2. Redistributions in binary form must reproduce the above copyright
17 1.42 agc * notice, this list of conditions and the following disclaimer in the
18 1.42 agc * documentation and/or other materials provided with the distribution.
19 1.42 agc * 3. Neither the name of the University nor the names of its contributors
20 1.42 agc * may be used to endorse or promote products derived from this software
21 1.42 agc * without specific prior written permission.
22 1.42 agc *
23 1.42 agc * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 1.42 agc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 1.42 agc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 1.42 agc * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 1.42 agc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 1.42 agc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 1.42 agc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 1.42 agc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 1.42 agc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 1.42 agc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 1.42 agc * SUCH DAMAGE.
34 1.42 agc *
35 1.42 agc * from: Utah $Hdr: cpu.h 1.16 91/03/25$
36 1.42 agc *
37 1.42 agc * @(#)cpu.h 8.4 (Berkeley) 1/5/94
38 1.42 agc */
39 1.42 agc /*
40 1.42 agc * Copyright (c) 1988 University of Utah.
41 1.1 cgd *
42 1.1 cgd * This code is derived from software contributed to Berkeley by
43 1.1 cgd * the Systems Programming Group of the University of Utah Computer
44 1.1 cgd * Science Department.
45 1.1 cgd *
46 1.1 cgd * Redistribution and use in source and binary forms, with or without
47 1.1 cgd * modification, are permitted provided that the following conditions
48 1.1 cgd * are met:
49 1.1 cgd * 1. Redistributions of source code must retain the above copyright
50 1.1 cgd * notice, this list of conditions and the following disclaimer.
51 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
52 1.1 cgd * notice, this list of conditions and the following disclaimer in the
53 1.1 cgd * documentation and/or other materials provided with the distribution.
54 1.1 cgd * 3. All advertising materials mentioning features or use of this software
55 1.1 cgd * must display the following acknowledgement:
56 1.1 cgd * This product includes software developed by the University of
57 1.1 cgd * California, Berkeley and its contributors.
58 1.1 cgd * 4. Neither the name of the University nor the names of its contributors
59 1.1 cgd * may be used to endorse or promote products derived from this software
60 1.1 cgd * without specific prior written permission.
61 1.1 cgd *
62 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66 1.1 cgd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 1.1 cgd * SUCH DAMAGE.
73 1.1 cgd *
74 1.8 mycroft * from: Utah $Hdr: cpu.h 1.16 91/03/25$
75 1.8 mycroft *
76 1.9 cgd * @(#)cpu.h 8.4 (Berkeley) 1/5/94
77 1.1 cgd */
78 1.1 cgd
79 1.15 thorpej #ifndef _HP300_CPU_H_
80 1.15 thorpej #define _HP300_CPU_H_
81 1.15 thorpej
82 1.38 mrg #if defined(_KERNEL_OPT)
83 1.34 thorpej #include "opt_lockdebug.h"
84 1.34 thorpej #endif
85 1.34 thorpej
86 1.1 cgd /*
87 1.1 cgd * Exported definitions unique to hp300/68k cpu support.
88 1.1 cgd */
89 1.1 cgd
90 1.1 cgd /*
91 1.20 thorpej * Get common m68k CPU definitions.
92 1.20 thorpej */
93 1.20 thorpej #include <m68k/cpu.h>
94 1.39 chs #include <machine/hp300spu.h>
95 1.20 thorpej
96 1.20 thorpej /*
97 1.24 thorpej * Get interrupt glue.
98 1.24 thorpej */
99 1.24 thorpej #include <machine/intr.h>
100 1.24 thorpej
101 1.34 thorpej #include <sys/sched.h>
102 1.34 thorpej struct cpu_info {
103 1.34 thorpej struct schedstate_percpu ci_schedstate; /* scheduler state */
104 1.34 thorpej #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
105 1.34 thorpej u_long ci_spin_locks; /* # of spin locks held */
106 1.34 thorpej u_long ci_simple_locks; /* # of simple locks held */
107 1.34 thorpej #endif
108 1.34 thorpej };
109 1.34 thorpej
110 1.34 thorpej #ifdef _KERNEL
111 1.35 he extern struct cpu_info cpu_info_store;
112 1.34 thorpej
113 1.34 thorpej #define curcpu() (&cpu_info_store)
114 1.34 thorpej
115 1.24 thorpej /*
116 1.1 cgd * definitions of cpu-dependent requirements
117 1.1 cgd * referenced in generic code
118 1.1 cgd */
119 1.8 mycroft #define cpu_swapin(p) /* nothing */
120 1.8 mycroft #define cpu_wait(p) /* nothing */
121 1.13 mycroft #define cpu_swapout(p) /* nothing */
122 1.33 thorpej #define cpu_number() 0
123 1.8 mycroft
124 1.41 thorpej void cpu_proc_fork(struct proc *, struct proc *);
125 1.41 thorpej
126 1.1 cgd /*
127 1.8 mycroft * Arguments to hardclock and gatherstats encapsulate the previous
128 1.8 mycroft * machine state in an opaque clockframe. One the hp300, we use
129 1.8 mycroft * what the hardware pushes on an interrupt (frame format 0).
130 1.1 cgd */
131 1.5 mycroft struct clockframe {
132 1.8 mycroft u_short sr; /* sr at time of interrupt */
133 1.8 mycroft u_long pc; /* pc at time of interrupt */
134 1.8 mycroft u_short vo; /* vector offset (4-word frame) */
135 1.5 mycroft };
136 1.1 cgd
137 1.8 mycroft #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
138 1.8 mycroft #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
139 1.8 mycroft #define CLKF_PC(framep) ((framep)->pc)
140 1.8 mycroft #if 0
141 1.8 mycroft /* We would like to do it this way... */
142 1.8 mycroft #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
143 1.8 mycroft #else
144 1.8 mycroft /* but until we start using PSL_M, we have to do this instead */
145 1.8 mycroft #define CLKF_INTR(framep) (0) /* XXX */
146 1.8 mycroft #endif
147 1.1 cgd
148 1.1 cgd
149 1.1 cgd /*
150 1.1 cgd * Preempt the current process if in interrupt from user mode,
151 1.1 cgd * or after the current trap/syscall if in system mode.
152 1.1 cgd */
153 1.28 scottr extern int want_resched; /* resched() was called */
154 1.36 thorpej #define need_resched(ci) { want_resched++; aston(); }
155 1.1 cgd
156 1.1 cgd /*
157 1.8 mycroft * Give a profiling tick to the current process when the user profiling
158 1.8 mycroft * buffer pages are invalid. On the hp300, request an ast to send us
159 1.8 mycroft * through trap, marking the proc as needing a profiling tick.
160 1.1 cgd */
161 1.7 cgd #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
162 1.1 cgd
163 1.1 cgd /*
164 1.1 cgd * Notify the current process (p) that it has a signal pending,
165 1.1 cgd * process as soon as possible.
166 1.1 cgd */
167 1.1 cgd #define signotify(p) aston()
168 1.1 cgd
169 1.28 scottr extern int astpending; /* need to trap before returning to user mode */
170 1.1 cgd #define aston() (astpending++)
171 1.34 thorpej
172 1.34 thorpej #endif /* _KERNEL */
173 1.1 cgd
174 1.6 mycroft /*
175 1.6 mycroft * CTL_MACHDEP definitions.
176 1.6 mycroft */
177 1.6 mycroft #define CPU_CONSDEV 1 /* dev_t: console terminal device */
178 1.6 mycroft #define CPU_MAXID 2 /* number of valid machdep ids */
179 1.1 cgd
180 1.8 mycroft #define CTL_MACHDEP_NAMES { \
181 1.6 mycroft { 0, 0 }, \
182 1.6 mycroft { "console_device", CTLTYPE_STRUCT }, \
183 1.6 mycroft }
184 1.1 cgd
185 1.15 thorpej /*
186 1.25 thorpej * The rest of this should probably be moved to <machine/hp300spu.h>,
187 1.1 cgd * although some of it could probably be put into generic 68k headers.
188 1.1 cgd */
189 1.1 cgd
190 1.19 thorpej #ifdef _KERNEL
191 1.1 cgd extern char *intiobase, *intiolimit;
192 1.19 thorpej extern void (*vectab[]) __P((void));
193 1.17 thorpej
194 1.22 scottr struct frame;
195 1.22 scottr struct fpframe;
196 1.22 scottr struct pcb;
197 1.21 thorpej
198 1.21 thorpej /* locore.s functions */
199 1.22 scottr void m68881_save __P((struct fpframe *));
200 1.22 scottr void m68881_restore __P((struct fpframe *));
201 1.22 scottr int suline __P((caddr_t, caddr_t));
202 1.22 scottr void savectx __P((struct pcb *));
203 1.41 thorpej void switch_exit __P((struct lwp *));
204 1.41 thorpej void switch_lwp_exit __P((struct lwp *));
205 1.22 scottr void proc_trampoline __P((void));
206 1.22 scottr void loadustp __P((int));
207 1.22 scottr
208 1.18 scottr void doboot __P((void))
209 1.17 thorpej __attribute__((__noreturn__));
210 1.21 thorpej void ecacheon __P((void));
211 1.21 thorpej void ecacheoff __P((void));
212 1.26 thorpej
213 1.26 thorpej /* clock.c functions */
214 1.26 thorpej void hp300_calibrate_delay __P((void));
215 1.21 thorpej
216 1.21 thorpej /* machdep.c functions */
217 1.21 thorpej int badaddr __P((caddr_t));
218 1.21 thorpej int badbaddr __P((caddr_t));
219 1.22 scottr
220 1.22 scottr /* sys_machdep.c functions */
221 1.32 is int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *));
222 1.22 scottr
223 1.22 scottr /* vm_machdep.c functions */
224 1.22 scottr void physaccess __P((caddr_t, caddr_t, int, int));
225 1.22 scottr void physunaccess __P((caddr_t, int));
226 1.22 scottr int kvtop __P((caddr_t));
227 1.8 mycroft
228 1.8 mycroft /* what is this supposed to do? i.e. how is it different than startrtclock? */
229 1.8 mycroft #define enablertclock()
230 1.8 mycroft
231 1.1 cgd #endif
232 1.1 cgd
233 1.1 cgd /* physical memory sections */
234 1.1 cgd #define ROMBASE (0x00000000)
235 1.1 cgd #define INTIOBASE (0x00400000)
236 1.1 cgd #define INTIOTOP (0x00600000)
237 1.1 cgd #define EXTIOBASE (0x00600000)
238 1.1 cgd #define EXTIOTOP (0x20000000)
239 1.1 cgd #define MAXADDR (0xFFFFF000)
240 1.1 cgd
241 1.1 cgd /*
242 1.1 cgd * Internal IO space:
243 1.1 cgd *
244 1.1 cgd * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
245 1.1 cgd *
246 1.1 cgd * Internal IO space is mapped in the kernel from ``intiobase'' to
247 1.1 cgd * ``intiolimit'' (defined in locore.s). Since it is always mapped,
248 1.1 cgd * conversion between physical and kernel virtual addresses is easy.
249 1.1 cgd */
250 1.1 cgd #define ISIIOVA(va) \
251 1.1 cgd ((char *)(va) >= intiobase && (char *)(va) < intiolimit)
252 1.1 cgd #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
253 1.1 cgd #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
254 1.1 cgd #define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
255 1.1 cgd #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */
256 1.1 cgd
257 1.1 cgd /*
258 1.1 cgd * External IO space:
259 1.1 cgd *
260 1.1 cgd * DIO ranges from select codes 0-63 at physical addresses given by:
261 1.1 cgd * 0x600000 + (sc - 32) * 0x10000
262 1.1 cgd * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for
263 1.1 cgd * their control space and the remaining areas, [0x200000-0x400000) and
264 1.1 cgd * [0x800000-0x1000000), are for additional space required by a card;
265 1.1 cgd * e.g. a display framebuffer.
266 1.1 cgd *
267 1.1 cgd * DIO-II ranges from select codes 132-255 at physical addresses given by:
268 1.1 cgd * 0x1000000 + (sc - 132) * 0x400000
269 1.1 cgd * The address range of DIO-II space is thus [0x1000000-0x20000000).
270 1.1 cgd *
271 1.1 cgd * DIO/DIO-II space is too large to map in its entirety, instead devices
272 1.1 cgd * are mapped into kernel virtual address space allocated from a range
273 1.1 cgd * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''.
274 1.1 cgd */
275 1.1 cgd #define DIOBASE (0x600000)
276 1.1 cgd #define DIOTOP (0x1000000)
277 1.1 cgd #define DIOCSIZE (0x10000)
278 1.1 cgd #define DIOIIBASE (0x01000000)
279 1.1 cgd #define DIOIITOP (0x20000000)
280 1.1 cgd #define DIOIICSIZE (0x00400000)
281 1.1 cgd
282 1.1 cgd /*
283 1.1 cgd * HP MMU
284 1.1 cgd */
285 1.1 cgd #define MMUBASE IIOPOFF(0x5F4000)
286 1.1 cgd #define MMUSSTP 0x0
287 1.1 cgd #define MMUUSTP 0x4
288 1.1 cgd #define MMUTBINVAL 0x8
289 1.1 cgd #define MMUSTAT 0xC
290 1.1 cgd #define MMUCMD MMUSTAT
291 1.1 cgd
292 1.1 cgd #define MMU_UMEN 0x0001 /* enable user mapping */
293 1.1 cgd #define MMU_SMEN 0x0002 /* enable supervisor mapping */
294 1.1 cgd #define MMU_CEN 0x0004 /* enable data cache */
295 1.1 cgd #define MMU_BERR 0x0008 /* bus error */
296 1.1 cgd #define MMU_IEN 0x0020 /* enable instruction cache */
297 1.1 cgd #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */
298 1.1 cgd #define MMU_WPF 0x2000 /* write protect fault */
299 1.1 cgd #define MMU_PF 0x4000 /* page fault */
300 1.1 cgd #define MMU_PTF 0x8000 /* page table fault */
301 1.1 cgd
302 1.1 cgd #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
303 1.1 cgd #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
304 1.40 chs
305 1.40 chs #if defined(CACHE_HAVE_PAC) || defined(CACHE_HAVE_VAC)
306 1.40 chs #define M68K_CACHEOPS_MACHDEP
307 1.40 chs #endif
308 1.40 chs
309 1.40 chs #ifdef CACHE_HAVE_PAC
310 1.40 chs #define M68K_CACHEOPS_MACHDEP_PCIA
311 1.40 chs #endif
312 1.40 chs
313 1.40 chs #ifdef CACHE_HAVE_VAC
314 1.40 chs #define M68K_CACHEOPS_MACHDEP_DCIA
315 1.40 chs #define M68K_CACHEOPS_MACHDEP_DCIS
316 1.40 chs #define M68K_CACHEOPS_MACHDEP_DCIU
317 1.40 chs #define M68K_CACHEOPS_MACHDEP_TBIA
318 1.40 chs #define M68K_CACHEOPS_MACHDEP_TBIS
319 1.40 chs #define M68K_CACHEOPS_MACHDEP_TBIAS
320 1.40 chs #define M68K_CACHEOPS_MACHDEP_TBIAU
321 1.40 chs #endif
322 1.15 thorpej
323 1.15 thorpej #endif /* _HP300_CPU_H_ */
324