cpu.h revision 1.17
1 /* $NetBSD: cpu.h,v 1.17 1996/04/27 00:38:44 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 #ifndef _HP300_CPU_H_ 46 #define _HP300_CPU_H_ 47 48 /* 49 * Exported definitions unique to hp300/68k cpu support. 50 */ 51 52 /* 53 * definitions of cpu-dependent requirements 54 * referenced in generic code 55 */ 56 #define cpu_swapin(p) /* nothing */ 57 #define cpu_wait(p) /* nothing */ 58 #define cpu_swapout(p) /* nothing */ 59 60 /* 61 * Arguments to hardclock and gatherstats encapsulate the previous 62 * machine state in an opaque clockframe. One the hp300, we use 63 * what the hardware pushes on an interrupt (frame format 0). 64 */ 65 struct clockframe { 66 u_short sr; /* sr at time of interrupt */ 67 u_long pc; /* pc at time of interrupt */ 68 u_short vo; /* vector offset (4-word frame) */ 69 }; 70 71 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 72 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 73 #define CLKF_PC(framep) ((framep)->pc) 74 #if 0 75 /* We would like to do it this way... */ 76 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 77 #else 78 /* but until we start using PSL_M, we have to do this instead */ 79 #define CLKF_INTR(framep) (0) /* XXX */ 80 #endif 81 82 83 /* 84 * Preempt the current process if in interrupt from user mode, 85 * or after the current trap/syscall if in system mode. 86 */ 87 #define need_resched() { want_resched++; aston(); } 88 89 /* 90 * Give a profiling tick to the current process when the user profiling 91 * buffer pages are invalid. On the hp300, request an ast to send us 92 * through trap, marking the proc as needing a profiling tick. 93 */ 94 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 95 96 /* 97 * Notify the current process (p) that it has a signal pending, 98 * process as soon as possible. 99 */ 100 #define signotify(p) aston() 101 102 #define aston() (astpending++) 103 104 int astpending; /* need to trap before returning to user mode */ 105 int want_resched; /* resched() was called */ 106 107 108 /* 109 * simulated software interrupt register 110 */ 111 extern unsigned char ssir; 112 113 #define SIR_NET 0x1 114 #define SIR_CLOCK 0x2 115 116 #define siroff(x) ssir &= ~(x) 117 #define setsoftnet() ssir |= SIR_NET 118 #define setsoftclock() ssir |= SIR_CLOCK 119 120 /* 121 * CTL_MACHDEP definitions. 122 */ 123 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 124 #define CPU_MAXID 2 /* number of valid machdep ids */ 125 126 #define CTL_MACHDEP_NAMES { \ 127 { 0, 0 }, \ 128 { "console_device", CTLTYPE_STRUCT }, \ 129 } 130 131 #ifdef _KERNEL 132 /* 133 * Associate HP 9000/300 models with CPU/MMU combinations. 134 */ 135 136 /* 137 * HP 68020-based computers. HP320 and HP350 have an HP MMU. 138 * HP330 has a Motorola MMU. 139 */ 140 #if (defined(HP320) || defined(HP330) || defined(HP350)) 141 #ifndef M68020 142 #define M68020 143 #endif /* ! M68020 */ 144 145 #if defined(HP330) && !defined(M68K_MMU_MOTOROLA) 146 #define M68K_MMU_MOTOROLA 147 #endif /* HP330 && ! M68K_MMU_MOTOROLA */ 148 149 #if (defined(HP320) || defined(HP350)) && !defined(M68K_MMU_HP) 150 #define M68K_MMU_HP /* include cheezy VAC support */ 151 #endif /* (HP320 || HP350) && ! M68K_MMU_HP */ 152 #endif /* HP320 || HP330 || HP350 */ 153 154 /* 155 * HP 68030-based computers. HP375 includes support for the 156 * 345, 400t, and 400s. 157 */ 158 #if (defined(HP340) || defined(HP360) || defined(HP370) || defined(HP375)) 159 #ifndef M68030 160 #define M68030 161 #endif /* ! M68030 */ 162 163 #ifndef M68K_MMU_MOTOROLA 164 #define M68K_MMU_MOTOROLA 165 #endif /* ! M68K_MMU_MOTOROLA */ 166 #endif /* HP340 || HP360 || HP370 || HP375 */ 167 168 /* 169 * HP 68040-based computers. HP380 includes support for the 170 * 425t, 425s, and 433s. 171 */ 172 #if defined(HP380) 173 #ifndef M68040 174 #define M68040 175 #endif /* ! M68040 */ 176 177 #ifndef M68K_MMU_MOTOROLA 178 #define M68K_MMU_MOTOROLA 179 #endif /* ! M68K_MMU_MOTOROLA */ 180 #endif /* HP380 */ 181 #endif /* _KERNEL */ 182 183 /* 184 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 185 * although some of it could probably be put into generic 68k headers. 186 */ 187 188 /* values for machineid */ 189 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 190 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 191 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 192 #define HP_360 3 /* 25Mhz 68030 */ 193 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 194 #define HP_340 5 /* 16Mhz 68030 */ 195 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 196 #define HP_380 7 /* 25Mhz 68040 */ 197 #define HP_433 8 /* 33Mhz 68040 */ 198 199 /* values for mmutype (assigned for quick testing) */ 200 #define MMU_68040 -2 /* 68040 on-chip MMU */ 201 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 202 #define MMU_HP 0 /* HP proprietary */ 203 #define MMU_68851 1 /* Motorola 68851 */ 204 205 /* values for ectype */ 206 #define EC_PHYS -1 /* external physical address cache */ 207 #define EC_NONE 0 /* no external cache */ 208 #define EC_VIRT 1 /* external virtual address cache */ 209 210 /* values for cpuspeed (not really related to clock speed due to caches) */ 211 #define MHZ_8 1 212 #define MHZ_16 2 213 #define MHZ_25 3 214 #define MHZ_33 4 215 #define MHZ_50 6 216 217 #ifdef _KERNEL 218 extern int machineid, mmutype, ectype; 219 extern char *intiobase, *intiolimit; 220 221 void doboot __P((int)) 222 __attribute__((__noreturn__)); 223 224 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 225 #define enablertclock() 226 227 #endif 228 229 /* physical memory sections */ 230 #define ROMBASE (0x00000000) 231 #define INTIOBASE (0x00400000) 232 #define INTIOTOP (0x00600000) 233 #define EXTIOBASE (0x00600000) 234 #define EXTIOTOP (0x20000000) 235 #define MAXADDR (0xFFFFF000) 236 237 /* 238 * Internal IO space: 239 * 240 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 241 * 242 * Internal IO space is mapped in the kernel from ``intiobase'' to 243 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 244 * conversion between physical and kernel virtual addresses is easy. 245 */ 246 #define ISIIOVA(va) \ 247 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 248 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 249 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 250 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 251 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 252 253 /* 254 * External IO space: 255 * 256 * DIO ranges from select codes 0-63 at physical addresses given by: 257 * 0x600000 + (sc - 32) * 0x10000 258 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 259 * their control space and the remaining areas, [0x200000-0x400000) and 260 * [0x800000-0x1000000), are for additional space required by a card; 261 * e.g. a display framebuffer. 262 * 263 * DIO-II ranges from select codes 132-255 at physical addresses given by: 264 * 0x1000000 + (sc - 132) * 0x400000 265 * The address range of DIO-II space is thus [0x1000000-0x20000000). 266 * 267 * DIO/DIO-II space is too large to map in its entirety, instead devices 268 * are mapped into kernel virtual address space allocated from a range 269 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 270 */ 271 #define DIOBASE (0x600000) 272 #define DIOTOP (0x1000000) 273 #define DIOCSIZE (0x10000) 274 #define DIOIIBASE (0x01000000) 275 #define DIOIITOP (0x20000000) 276 #define DIOIICSIZE (0x00400000) 277 278 /* 279 * HP MMU 280 */ 281 #define MMUBASE IIOPOFF(0x5F4000) 282 #define MMUSSTP 0x0 283 #define MMUUSTP 0x4 284 #define MMUTBINVAL 0x8 285 #define MMUSTAT 0xC 286 #define MMUCMD MMUSTAT 287 288 #define MMU_UMEN 0x0001 /* enable user mapping */ 289 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 290 #define MMU_CEN 0x0004 /* enable data cache */ 291 #define MMU_BERR 0x0008 /* bus error */ 292 #define MMU_IEN 0x0020 /* enable instruction cache */ 293 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 294 #define MMU_WPF 0x2000 /* write protect fault */ 295 #define MMU_PF 0x4000 /* page fault */ 296 #define MMU_PTF 0x8000 /* page table fault */ 297 298 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 299 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 300 301 /* 302 * 68851 and 68030 MMU 303 */ 304 #define PMMU_LVLMASK 0x0007 305 #define PMMU_INV 0x0400 306 #define PMMU_WP 0x0800 307 #define PMMU_ALV 0x1000 308 #define PMMU_SO 0x2000 309 #define PMMU_LV 0x4000 310 #define PMMU_BE 0x8000 311 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 312 313 /* 314 * 68040 MMU 315 */ 316 #define MMU4_RES 0x001 317 #define MMU4_TTR 0x002 318 #define MMU4_WP 0x004 319 #define MMU4_MOD 0x010 320 #define MMU4_CMMASK 0x060 321 #define MMU4_SUP 0x080 322 #define MMU4_U0 0x100 323 #define MMU4_U1 0x200 324 #define MMU4_GLB 0x400 325 #define MMU4_BE 0x800 326 327 /* 680X0 function codes */ 328 #define FC_USERD 1 /* user data space */ 329 #define FC_USERP 2 /* user program space */ 330 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 331 #define FC_SUPERD 5 /* supervisor data space */ 332 #define FC_SUPERP 6 /* supervisor program space */ 333 #define FC_CPU 7 /* CPU space */ 334 335 /* fields in the 68020 cache control register */ 336 #define IC_ENABLE 0x0001 /* enable instruction cache */ 337 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 338 #define IC_CE 0x0004 /* clear instruction cache entry */ 339 #define IC_CLR 0x0008 /* clear entire instruction cache */ 340 341 /* additional fields in the 68030 cache control register */ 342 #define IC_BE 0x0010 /* instruction burst enable */ 343 #define DC_ENABLE 0x0100 /* data cache enable */ 344 #define DC_FREEZE 0x0200 /* data cache freeze */ 345 #define DC_CE 0x0400 /* clear data cache entry */ 346 #define DC_CLR 0x0800 /* clear entire data cache */ 347 #define DC_BE 0x1000 /* data burst enable */ 348 #define DC_WA 0x2000 /* write allocate */ 349 350 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 351 #define CACHE_OFF (DC_CLR|IC_CLR) 352 #define CACHE_CLR (CACHE_ON) 353 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 354 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 355 356 /* 68040 cache control register */ 357 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 358 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 359 360 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 361 #define CACHE4_OFF (0) 362 363 #endif /* _HP300_CPU_H_ */ 364
Indexes created Thu Sep 25 16:09:42 GMT 2025