dcareg.h revision 1.1.4.2
1 1.1.4.2 skrll /* $NetBSD: dcareg.h,v 1.1.4.2 2004/08/03 10:34:37 skrll Exp $ */ 2 1.1.4.2 skrll 3 1.1.4.2 skrll /* 4 1.1.4.2 skrll * Copyright (c) 1982, 1986, 1990, 1993 5 1.1.4.2 skrll * The Regents of the University of California. All rights reserved. 6 1.1.4.2 skrll * 7 1.1.4.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.4.2 skrll * modification, are permitted provided that the following conditions 9 1.1.4.2 skrll * are met: 10 1.1.4.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.4.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.4.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.4.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.4.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.4.2 skrll * 3. Neither the name of the University nor the names of its contributors 16 1.1.4.2 skrll * may be used to endorse or promote products derived from this software 17 1.1.4.2 skrll * without specific prior written permission. 18 1.1.4.2 skrll * 19 1.1.4.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 1.1.4.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 1.1.4.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 1.1.4.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 1.1.4.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 1.1.4.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 1.1.4.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 1.1.4.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 1.1.4.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 1.1.4.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 1.1.4.2 skrll * SUCH DAMAGE. 30 1.1.4.2 skrll * 31 1.1.4.2 skrll * @(#)dcareg.h 8.1 (Berkeley) 6/10/93 32 1.1.4.2 skrll */ 33 1.1.4.2 skrll 34 1.1.4.2 skrll #include <hp300/dev/iotypes.h> /* XXX */ 35 1.1.4.2 skrll 36 1.1.4.2 skrll #ifdef hp700 37 1.1.4.2 skrll struct dcadevice { 38 1.1.4.2 skrll vu_char dca_reset; 39 1.1.4.2 skrll vu_char dca_pad[0x800-1]; 40 1.1.4.2 skrll vu_char dca_data; /* receive buf or xmit hold */ 41 1.1.4.2 skrll vu_char dca_ier; /* interrupt enable */ 42 1.1.4.2 skrll vu_char dca_iir; /* (RO) interrupt identify */ 43 1.1.4.2 skrll #define dca_fifo dca_iir /* (WO) FIFO control */ 44 1.1.4.2 skrll vu_char dca_cfcr; /* line control */ 45 1.1.4.2 skrll vu_char dca_mcr; /* modem control */ 46 1.1.4.2 skrll vu_char dca_lsr; /* line status */ 47 1.1.4.2 skrll vu_char dca_msr; /* modem status */ 48 1.1.4.2 skrll vu_char dca_scr; /* scratch pad */ 49 1.1.4.2 skrll }; 50 1.1.4.2 skrll #else 51 1.1.4.2 skrll struct dcadevice { 52 1.1.4.2 skrll /* card registers */ 53 1.1.4.2 skrll u_char dca_pad0; 54 1.1.4.2 skrll vu_char dca_id; /* 0x01 (read) */ 55 1.1.4.2 skrll #define dca_reset dca_id /* 0x01 (write) */ 56 1.1.4.2 skrll u_char dca_pad1; 57 1.1.4.2 skrll vu_char dca_ic; /* 0x03 */ 58 1.1.4.2 skrll u_char dca_pad2; 59 1.1.4.2 skrll vu_char dca_ocbrc; /* 0x05 */ 60 1.1.4.2 skrll u_char dca_pad3; 61 1.1.4.2 skrll vu_char dca_lcsm; /* 0x07 */ 62 1.1.4.2 skrll u_char dca_pad4[8]; 63 1.1.4.2 skrll /* chip registers */ 64 1.1.4.2 skrll u_char dca_pad5; 65 1.1.4.2 skrll vu_char dca_data; /* 0x11 */ 66 1.1.4.2 skrll u_char dca_pad6; 67 1.1.4.2 skrll vu_char dca_ier; /* 0x13 */ 68 1.1.4.2 skrll u_char dca_pad7; 69 1.1.4.2 skrll vu_char dca_iir; /* 0x15 (read) */ 70 1.1.4.2 skrll #define dca_fifo dca_iir /* 0x15 (write) */ 71 1.1.4.2 skrll u_char dca_pad8; 72 1.1.4.2 skrll vu_char dca_cfcr; /* 0x17 */ 73 1.1.4.2 skrll u_char dca_pad9; 74 1.1.4.2 skrll vu_char dca_mcr; /* 0x19 */ 75 1.1.4.2 skrll u_char dca_padA; 76 1.1.4.2 skrll vu_char dca_lsr; /* 0x1B */ 77 1.1.4.2 skrll u_char dca_padB; 78 1.1.4.2 skrll vu_char dca_msr; /* 0x1D */ 79 1.1.4.2 skrll }; 80 1.1.4.2 skrll #endif 81 1.1.4.2 skrll 82 1.1.4.2 skrll /* interface reset/id (300 only) */ 83 1.1.4.2 skrll #define DCAID0 0x02 84 1.1.4.2 skrll #define DCAREMID0 0x82 85 1.1.4.2 skrll #define DCAID1 0x42 86 1.1.4.2 skrll #define DCAREMID1 0xC2 87 1.1.4.2 skrll 88 1.1.4.2 skrll /* interrupt control (300 only) */ 89 1.1.4.2 skrll #define DCAIPL(x) ((((x) >> 4) & 3) + 3) 90 1.1.4.2 skrll #define IC_IR 0x40 91 1.1.4.2 skrll #define IC_IE 0x80 92 1.1.4.2 skrll 93 1.1.4.2 skrll /* 94 1.1.4.2 skrll * 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) 95 1.1.4.2 skrll * NB: This constant is for a 7.3728 clock frequency. The 300 clock 96 1.1.4.2 skrll * frequency is 2.4576, giving a constant of 153600. 97 1.1.4.2 skrll */ 98 1.1.4.2 skrll #ifdef hp300 99 1.1.4.2 skrll #define DCABRD(x) (153600 / (x)) 100 1.1.4.2 skrll #endif 101 1.1.4.2 skrll #ifdef hp700 102 1.1.4.2 skrll #define DCABRD(x) (460800 / (x)) 103 1.1.4.2 skrll #endif 104 1.1.4.2 skrll 105 1.1.4.2 skrll /* interrupt enable register */ 106 1.1.4.2 skrll #define IER_ERXRDY 0x1 107 1.1.4.2 skrll #define IER_ETXRDY 0x2 108 1.1.4.2 skrll #define IER_ERLS 0x4 109 1.1.4.2 skrll #define IER_EMSC 0x8 110 1.1.4.2 skrll 111 1.1.4.2 skrll /* interrupt identification register */ 112 1.1.4.2 skrll #define IIR_IMASK 0xf 113 1.1.4.2 skrll #define IIR_RXTOUT 0xc 114 1.1.4.2 skrll #define IIR_RLS 0x6 115 1.1.4.2 skrll #define IIR_RXRDY 0x4 116 1.1.4.2 skrll #define IIR_TXRDY 0x2 117 1.1.4.2 skrll #define IIR_NOPEND 0x1 118 1.1.4.2 skrll #define IIR_MLSC 0x0 119 1.1.4.2 skrll #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 120 1.1.4.2 skrll 121 1.1.4.2 skrll /* fifo control register */ 122 1.1.4.2 skrll #define FIFO_ENABLE 0x01 123 1.1.4.2 skrll #define FIFO_RCV_RST 0x02 124 1.1.4.2 skrll #define FIFO_XMT_RST 0x04 125 1.1.4.2 skrll #define FIFO_DMA_MODE 0x08 126 1.1.4.2 skrll #define FIFO_TRIGGER_1 0x00 127 1.1.4.2 skrll #define FIFO_TRIGGER_4 0x40 128 1.1.4.2 skrll #define FIFO_TRIGGER_8 0x80 129 1.1.4.2 skrll #define FIFO_TRIGGER_14 0xc0 130 1.1.4.2 skrll 131 1.1.4.2 skrll /* character format control register */ 132 1.1.4.2 skrll #define CFCR_DLAB 0x80 133 1.1.4.2 skrll #define CFCR_SBREAK 0x40 134 1.1.4.2 skrll #define CFCR_PZERO 0x30 135 1.1.4.2 skrll #define CFCR_PONE 0x20 136 1.1.4.2 skrll #define CFCR_PEVEN 0x10 137 1.1.4.2 skrll #define CFCR_PODD 0x00 138 1.1.4.2 skrll #define CFCR_PENAB 0x08 139 1.1.4.2 skrll #define CFCR_STOPB 0x04 140 1.1.4.2 skrll #define CFCR_8BITS 0x03 141 1.1.4.2 skrll #define CFCR_7BITS 0x02 142 1.1.4.2 skrll #define CFCR_6BITS 0x01 143 1.1.4.2 skrll #define CFCR_5BITS 0x00 144 1.1.4.2 skrll 145 1.1.4.2 skrll /* modem control register */ 146 1.1.4.2 skrll #define MCR_LOOPBACK 0x10 147 1.1.4.2 skrll #define MCR_IEN 0x08 148 1.1.4.2 skrll #define MCR_DRS 0x04 149 1.1.4.2 skrll #define MCR_RTS 0x02 150 1.1.4.2 skrll #define MCR_DTR 0x01 151 1.1.4.2 skrll 152 1.1.4.2 skrll /* line status register */ 153 1.1.4.2 skrll #define LSR_RCV_FIFO 0x80 154 1.1.4.2 skrll #define LSR_TSRE 0x40 155 1.1.4.2 skrll #define LSR_TXRDY 0x20 156 1.1.4.2 skrll #define LSR_BI 0x10 157 1.1.4.2 skrll #define LSR_FE 0x08 158 1.1.4.2 skrll #define LSR_PE 0x04 159 1.1.4.2 skrll #define LSR_OE 0x02 160 1.1.4.2 skrll #define LSR_RXRDY 0x01 161 1.1.4.2 skrll #define LSR_RCV_MASK 0x1f 162 1.1.4.2 skrll 163 1.1.4.2 skrll /* modem status register */ 164 1.1.4.2 skrll #define MSR_DCD 0x80 165 1.1.4.2 skrll #define MSR_RI 0x40 166 1.1.4.2 skrll #define MSR_DSR 0x20 167 1.1.4.2 skrll #define MSR_CTS 0x10 168 1.1.4.2 skrll #define MSR_DDCD 0x08 169 1.1.4.2 skrll #define MSR_TERI 0x04 170 1.1.4.2 skrll #define MSR_DDSR 0x02 171 1.1.4.2 skrll #define MSR_DCTS 0x01 172
Indexes created Wed Oct 22 13:09:56 GMT 2025