arm_arch.cpp revision 1.5.6.1
1 /* $NetBSD: arm_arch.cpp,v 1.5.6.1 2006/04/22 11:37:28 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <arm/arm_arch.h> 40 #include <console.h> 41 #include <memory.h> 42 #include <arm/arm_sa1100.h> 43 44 ARMArchitecture::ARMArchitecture(Console *&cons, MemoryManager *&mem) 45 : Architecture(cons, mem) 46 { 47 DPRINTF((TEXT("ARM architecture.\n"))); 48 } 49 50 ARMArchitecture::~ARMArchitecture(void) 51 { 52 } 53 54 void 55 ARMArchitecture::systemInfo() 56 { 57 Architecture::systemInfo(); 58 59 _kmode = SetKMode(1); 60 DI(); 61 if ((GetCPSR() & 0x1f) != 0x1f) 62 DPRINTF((TEXT("can't change to System mode\n"))); 63 64 DPRINTF((TEXT("Reg0 :%08x\n"), GetCop15Reg0())); 65 DPRINTF((TEXT("Reg1 :%08x\n"), GetCop15Reg1())); 66 DPRINTF((TEXT("Reg2 :%08x\n"), GetCop15Reg2())); 67 DPRINTF((TEXT("Reg3 :%08x\n"), GetCop15Reg3())); 68 DPRINTF((TEXT("Reg5 :%08x\n"), GetCop15Reg5())); 69 DPRINTF((TEXT("Reg6 :%08x\n"), GetCop15Reg6())); 70 DPRINTF((TEXT("Reg13:%08x\n"), GetCop15Reg13())); 71 DPRINTF((TEXT("Reg14:%08x\n"), GetCop15Reg14())); 72 DPRINTF((TEXT("CPSR :%08x\n"), GetCPSR())); 73 EI(); 74 SetKMode(_kmode); 75 } 76 77 BOOL 78 ARMArchitecture::init(void) 79 { 80 if (!_mem->init()) { 81 DPRINTF((TEXT("can't initialize memory manager.\n"))); 82 return FALSE; 83 } 84 // set D-RAM information 85 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 86 _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 87 _mem->loadBank(DRAM_BANK2_START, DRAM_BANK_SIZE); 88 _mem->loadBank(DRAM_BANK3_START, DRAM_BANK_SIZE); 89 90 return TRUE; 91 } 92 93 BOOL 94 ARMArchitecture::setupLoader() 95 { 96 vaddr_t v; 97 vsize_t sz = BOOT_FUNC_END - BOOT_FUNC_START; 98 99 // check 2nd bootloader size. 100 if (sz > _mem->getPageSize()) { 101 DPRINTF((TEXT("2nd bootloader size(%dbyte) is larger than page size(%d).\n"), 102 sz, _mem->getPageSize())); 103 return FALSE; 104 } 105 106 // get physical mapped page and copy loader to there. 107 // don't writeback D-cache here. make sure to writeback before jump. 108 if (!_mem->getPage(v , _loader_addr)) { 109 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 110 return FALSE; 111 } 112 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 113 (unsigned)v,(unsigned)_loader_addr)); 114 115 memcpy(reinterpret_cast <LPVOID>(v), 116 reinterpret_cast <LPVOID>(BOOT_FUNC_START), sz); 117 DPRINTF((TEXT("2nd bootloader copy done.\n"))); 118 119 return TRUE; 120 } 121 122 void 123 ARMArchitecture::jump(paddr_t info, paddr_t pvec) 124 { 125 kaddr_t sp; 126 vaddr_t v; 127 paddr_t p; 128 129 // stack for bootloader 130 _mem->getPage(v, p); 131 sp = ptokv(p) + _mem->getPageSize(); 132 133 // writeback whole D-cache 134 WritebackDCache(); 135 136 SetKMode(1); 137 FlatJump(info, pvec, sp, _loader_addr); 138 // NOTREACHED 139 } 140 141 void 142 ARMArchitecture::testFramebuffer() 143 { 144 // get frame buffer address from LCD controller register. 145 paddr_t fbaddr_p = _mem->readPhysical4(0xb0100010); // 0xc0002e00 146 // map frame buffer 147 vaddr_t fbaddr_v = _mem->mapPhysicalPage(fbaddr_p, 0x50000, 148 PAGE_READWRITE); 149 150 // test frame buffer 151 int j, k; 152 DI(); 153 for (j = 0; j < 480; j++) 154 for (k = 0; k < 640; k++) 155 VOLATILE_REF8(fbaddr_v + 0x200 + j * 640 + k) 156 = j * k & 0xff; 157 for (j = 120; j < 360; j++) 158 for (k = 120; k < 520; k++) 159 VOLATILE_REF8(fbaddr_v + 0x200 + j * 640 + k) = 0x3; 160 EI(); 161 _mem->unmapPhysicalPage(fbaddr_v); 162 } 163 164 void 165 ARMArchitecture::testUART() 166 { 167 #define TBY VOLATILE_REF(uart + 0x20) 168 #define UTDR VOLATILE_REF(uart + 0x14) 169 #define TBY_BUSY while (TBY & 0x1) 170 #define UTDR_PUTCHAR(c) (UTDR =(c)) 171 #define _(c) \ 172 __BEGIN_MACRO \ 173 TBY_BUSY; \ 174 UTDR_PUTCHAR(c); \ 175 __END_MACRO 176 vaddr_t uart = 177 _mem->mapPhysicalPage(0x80050000, 0x100, PAGE_READWRITE); 178 _('H');_('e');_('l');_('l');_('o');_(' '); 179 _('W');_('o');_('r');_('l');_('d');_('\r');_('\n'); 180 _mem->unmapPhysicalPage(uart); 181 } 182
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