arm_mmu.cpp revision 1.1.4.1 1 1.1.4.1 nathanw /* -*-C++-*- $NetBSD: arm_mmu.cpp,v 1.1.4.1 2001/06/21 19:22:52 nathanw Exp $ */
2 1.1 uch
3 1.1 uch /*-
4 1.1 uch * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation
8 1.1 uch * by UCHIYAMA Yasushi.
9 1.1 uch *
10 1.1 uch * Redistribution and use in source and binary forms, with or without
11 1.1 uch * modification, are permitted provided that the following conditions
12 1.1 uch * are met:
13 1.1 uch * 1. Redistributions of source code must retain the above copyright
14 1.1 uch * notice, this list of conditions and the following disclaimer.
15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 uch * notice, this list of conditions and the following disclaimer in the
17 1.1 uch * documentation and/or other materials provided with the distribution.
18 1.1 uch * 3. All advertising materials mentioning features or use of this software
19 1.1 uch * must display the following acknowledgement:
20 1.1 uch * This product includes software developed by the NetBSD
21 1.1 uch * Foundation, Inc. and its contributors.
22 1.1 uch * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 uch * contributors may be used to endorse or promote products derived
24 1.1 uch * from this software without specific prior written permission.
25 1.1 uch *
26 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 uch * POSSIBILITY OF SUCH DAMAGE.
37 1.1 uch */
38 1.1 uch
39 1.1 uch #include <arm/arm_mmu.h>
40 1.1 uch #include <console.h>
41 1.1 uch
42 1.1 uch MemoryManager_ArmMMU::MemoryManager_ArmMMU(Console *&cons,
43 1.1.4.1 nathanw size_t pagesize)
44 1.1 uch : MemoryManager(cons, pagesize)
45 1.1 uch {
46 1.1 uch DPRINTF((TEXT("Use ARM software MMU.\n")));
47 1.1 uch }
48 1.1 uch
49 1.1 uch MemoryManager_ArmMMU::~MemoryManager_ArmMMU(void)
50 1.1 uch {
51 1.1 uch SetKMode(_kmode);
52 1.1 uch }
53 1.1 uch
54 1.1 uch BOOL
55 1.1 uch MemoryManager_ArmMMU::init(void)
56 1.1 uch {
57 1.1 uch u_int32_t reg;
58 1.1 uch
59 1.1 uch _kmode = SetKMode(1);
60 1.1 uch // Check system mode
61 1.1 uch if ((GetCPSR() & 0x1f) != 0x1f) {
62 1.1 uch DPRINTF((TEXT("not System mode\n")));
63 1.1 uch return FALSE;
64 1.1 uch }
65 1.1 uch // Domain access control.(full access)
66 1.1 uch SetCop15Reg3(~0);
67 1.1 uch
68 1.1 uch // Get Translation table base.
69 1.1 uch reg = GetCop15Reg2();
70 1.1 uch _table_base = reg & ARM_MMU_TABLEBASE_MASK;
71 1.1 uch DPRINTF((TEXT("page directory address=0x%08x->0x%08x(0x%08x)\n"),
72 1.1.4.1 nathanw _table_base, readPhysical4(_table_base), reg));
73 1.1 uch
74 1.1 uch return TRUE;
75 1.1 uch }
76 1.1 uch
77 1.1 uch paddr_t
78 1.1 uch MemoryManager_ArmMMU::searchPage(vaddr_t vaddr)
79 1.1 uch {
80 1.1 uch paddr_t daddr, paddr = ~0;
81 1.1 uch u_int32_t desc1, desc2;
82 1.1 uch
83 1.1 uch // set marker.
84 1.1 uch memset(LPVOID(vaddr), 0xa5, _page_size);
85 1.1 uch
86 1.1 uch // PID virtual address mapping.
87 1.1 uch DPRINTF((TEXT("Virtual Address 0x%08x"), vaddr));
88 1.1 uch vaddr |= GetCop15Reg13();
89 1.1 uch DPRINTF((TEXT("(+PID)-> 0x%08x\n"), vaddr));
90 1.1 uch
91 1.1 uch daddr = _table_base | ARM_MMU_TABLEINDEX(vaddr);
92 1.1 uch desc1 = readPhysical4(daddr);
93 1.1 uch DPRINTF((TEXT("1st level descriptor 0x%08x(addr 0x%08x)\n"),
94 1.1.4.1 nathanw desc1, daddr));
95 1.1 uch
96 1.1 uch switch(ARM_MMU_LEVEL1DESC_TRANSLATE_TYPE(desc1)) {
97 1.1 uch default:
98 1.1 uch DPRINTF((TEXT("1st level descriptor fault.\n")));
99 1.1 uch break;
100 1.1 uch case ARM_MMU_LEVEL1DESC_TRANSLATE_SECTION:
101 1.1 uch paddr = ARM_MMU_SECTION_BASE(desc1) |
102 1.1.4.1 nathanw ARM_MMU_VADDR_SECTION_INDEX(vaddr);
103 1.1 uch DPRINTF((TEXT("section Physical Address 0x%08x\n"), paddr));
104 1.1 uch break;
105 1.1 uch case ARM_MMU_LEVEL1DESC_TRANSLATE_PAGE:
106 1.1 uch DPRINTF((TEXT("-> Level2 page descriptor.\n")));
107 1.1 uch daddr = ARM_MMU_PTE_BASE(desc1) |
108 1.1.4.1 nathanw ARM_MMU_VADDR_PTE_INDEX(vaddr);
109 1.1 uch desc2 = readPhysical4(daddr);
110 1.1 uch DPRINTF((TEXT("2nd level descriptor 0x%08x(addr 0x%08x)\n"),
111 1.1.4.1 nathanw desc2, daddr));
112 1.1 uch switch(desc2 & 0x3) {
113 1.1 uch default:
114 1.1 uch DPRINTF((TEXT("2nd level descriptor fault.\n")));
115 1.1 uch break;
116 1.1 uch case 2: // 4Kpage
117 1.1 uch paddr =(desc2 & 0xfffff000) |(vaddr & 0x00000fff);
118 1.1 uch break;
119 1.1 uch case 1: // 64Kpage
120 1.1 uch paddr =(desc2 & 0xffff0000) |(vaddr & 0x0000ffff);
121 1.1 uch break;
122 1.1 uch }
123 1.1 uch break;
124 1.1 uch }
125 1.1 uch
126 1.1 uch return paddr;
127 1.1 uch }
128