arm_pxa2x0.cpp revision 1.3 1 1.3 nonaka /* $NetBSD: arm_pxa2x0.cpp,v 1.3 2010/04/06 16:20:28 nonaka Exp $ */
2 1.1 rafal
3 1.1 rafal /*-
4 1.1 rafal * Copyright (c) 2008 The NetBSD Foundation, Inc.
5 1.1 rafal * All rights reserved.
6 1.1 rafal *
7 1.1 rafal * This code is derived from software contributed to The NetBSD Foundation
8 1.1 rafal * by UCHIYAMA Yasushi.
9 1.1 rafal *
10 1.1 rafal * Redistribution and use in source and binary forms, with or without
11 1.1 rafal * modification, are permitted provided that the following conditions
12 1.1 rafal * are met:
13 1.1 rafal * 1. Redistributions of source code must retain the above copyright
14 1.1 rafal * notice, this list of conditions and the following disclaimer.
15 1.1 rafal * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 rafal * notice, this list of conditions and the following disclaimer in the
17 1.1 rafal * documentation and/or other materials provided with the distribution.
18 1.1 rafal *
19 1.1 rafal * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 rafal * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 rafal * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 rafal * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 rafal * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 rafal * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 rafal * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 rafal * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 rafal * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 rafal * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 rafal * POSSIBILITY OF SUCH DAMAGE.
30 1.1 rafal */
31 1.1 rafal
32 1.1 rafal #include <arm/arm_arch.h>
33 1.1 rafal #include <console.h>
34 1.1 rafal #include <memory.h>
35 1.1 rafal #include <arm/arm_pxa2x0.h>
36 1.1 rafal
37 1.1 rafal /*
38 1.1 rafal * Intel XScale PXA 2x0
39 1.1 rafal */
40 1.1 rafal
41 1.1 rafal #define PAGE_SIZE 0x1000
42 1.1 rafal #define DRAM_BANK_NUM 4 /* total 256MByte */
43 1.1 rafal #define DRAM_BANK_SIZE 0x04000000 /* 64Mbyte */
44 1.1 rafal
45 1.1 rafal #define DRAM_BANK0_START 0xa0000000
46 1.1 rafal #define DRAM_BANK0_SIZE DRAM_BANK_SIZE
47 1.1 rafal #define DRAM_BANK1_START 0xa4000000
48 1.1 rafal #define DRAM_BANK1_SIZE DRAM_BANK_SIZE
49 1.1 rafal #define DRAM_BANK2_START 0xa8000000
50 1.1 rafal #define DRAM_BANK2_SIZE DRAM_BANK_SIZE
51 1.1 rafal #define DRAM_BANK3_START 0xac000000
52 1.1 rafal #define DRAM_BANK3_SIZE DRAM_BANK_SIZE
53 1.1 rafal #define ZERO_BANK_START 0xe0000000
54 1.1 rafal #define ZERO_BANK_SIZE DRAM_BANK_SIZE
55 1.1 rafal
56 1.1 rafal __BEGIN_DECLS
57 1.1 rafal
58 1.1 rafal // 2nd bootloader
59 1.3 nonaka void boot_func_pxa2x0(kaddr_t, kaddr_t, kaddr_t, kaddr_t);
60 1.3 nonaka extern char boot_func_end_pxa2x0[];
61 1.3 nonaka #define BOOT_FUNC_START reinterpret_cast <vaddr_t>(boot_func_pxa2x0)
62 1.3 nonaka #define BOOT_FUNC_END reinterpret_cast <vaddr_t>(boot_func_end_pxa2x0)
63 1.1 rafal
64 1.1 rafal /* jump to 2nd loader */
65 1.3 nonaka void FlatJump_pxa2x0(kaddr_t, kaddr_t, kaddr_t, kaddr_t);
66 1.1 rafal
67 1.1 rafal __END_DECLS
68 1.1 rafal
69 1.1 rafal PXA2X0Architecture::PXA2X0Architecture(Console *&cons, MemoryManager *&mem)
70 1.1 rafal : ARMArchitecture(cons, mem)
71 1.1 rafal {
72 1.1 rafal DPRINTF((TEXT("PXA-2x0 CPU.\n")));
73 1.1 rafal }
74 1.1 rafal
75 1.1 rafal PXA2X0Architecture::~PXA2X0Architecture(void)
76 1.1 rafal {
77 1.1 rafal }
78 1.1 rafal
79 1.1 rafal BOOL
80 1.1 rafal PXA2X0Architecture::init(void)
81 1.1 rafal {
82 1.1 rafal if (!_mem->init()) {
83 1.1 rafal DPRINTF((TEXT("can't initialize memory manager.\n")));
84 1.1 rafal return FALSE;
85 1.1 rafal }
86 1.1 rafal // set D-RAM information
87 1.1 rafal _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE);
88 1.1 rafal _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE);
89 1.1 rafal _mem->loadBank(DRAM_BANK2_START, DRAM_BANK_SIZE);
90 1.1 rafal _mem->loadBank(DRAM_BANK3_START, DRAM_BANK_SIZE);
91 1.1 rafal
92 1.3 nonaka // set D-cache information
93 1.3 nonaka dcachesize = 32768 * 2;
94 1.3 nonaka DPRINTF((TEXT("D-cache size = %d\n"), dcachesize));
95 1.3 nonaka
96 1.1 rafal #ifdef HW_TEST
97 1.1 rafal DPRINTF((TEXT("Testing framebuffer.\n")));
98 1.1 rafal testFramebuffer();
99 1.1 rafal
100 1.1 rafal DPRINTF((TEXT("Testing UART.\n")));
101 1.1 rafal testUART();
102 1.1 rafal #endif
103 1.1 rafal
104 1.3 nonaka #ifdef REGDUMP
105 1.3 nonaka DPRINTF((TEXT("Dump peripheral registers.\n")));
106 1.3 nonaka dumpPeripheralRegs();
107 1.3 nonaka #endif
108 1.3 nonaka
109 1.3 nonaka #ifdef CS0DUMP
110 1.3 nonaka uint32_t dumpsize = 1024 * 1024; // 1MB
111 1.3 nonaka DPRINTF((TEXT("Dump CS area (size = %d)\n"), dumpsize));
112 1.3 nonaka dumpCS0(dumpsize);
113 1.3 nonaka #endif
114 1.3 nonaka
115 1.1 rafal return TRUE;
116 1.1 rafal }
117 1.1 rafal
118 1.1 rafal void
119 1.1 rafal PXA2X0Architecture::testFramebuffer(void)
120 1.1 rafal {
121 1.1 rafal DPRINTF((TEXT("No framebuffer test yet.\n")));
122 1.1 rafal }
123 1.1 rafal
124 1.1 rafal void
125 1.1 rafal PXA2X0Architecture::testUART(void)
126 1.1 rafal {
127 1.1 rafal #define COM_DATA VOLATILE_REF8(uart + 0x00)
128 1.1 rafal #define COM_IIR VOLATILE_REF8(uart + 0x08)
129 1.1 rafal #define COM_LSR VOLATILE_REF8(uart + 0x14)
130 1.1 rafal #define LSR_TXRDY 0x20
131 1.1 rafal #define COM_TX_CHECK while (!(COM_LSR & LSR_TXRDY))
132 1.1 rafal #define COM_PUTCHAR(c) (COM_DATA = (c))
133 1.1 rafal #define COM_CLR_INTS ((void)COM_IIR)
134 1.1 rafal #define _(c) \
135 1.1 rafal __BEGIN_MACRO \
136 1.1 rafal COM_TX_CHECK; \
137 1.1 rafal COM_PUTCHAR(c); \
138 1.1 rafal COM_TX_CHECK; \
139 1.1 rafal COM_CLR_INTS; \
140 1.1 rafal __END_MACRO
141 1.1 rafal
142 1.1 rafal vaddr_t uart =
143 1.1 rafal _mem->mapPhysicalPage(0x40100000, 0x100, PAGE_READWRITE);
144 1.1 rafal
145 1.1 rafal // Don't turn on the enable-UART bit in the IER; this seems to
146 1.1 rafal // result in WinCE losing the port (and nothing working later).
147 1.1 rafal // All that should be taken care of by using WinCE to open the
148 1.1 rafal // port before we actually use it.
149 1.1 rafal
150 1.1 rafal _('H');_('e');_('l');_('l');_('o');_(' ');
151 1.1 rafal _('W');_('o');_('r');_('l');_('d');_('\r');_('\n');
152 1.1 rafal
153 1.1 rafal _mem->unmapPhysicalPage(uart);
154 1.1 rafal }
155 1.1 rafal
156 1.1 rafal BOOL
157 1.1 rafal PXA2X0Architecture::setupLoader(void)
158 1.1 rafal {
159 1.1 rafal vaddr_t v;
160 1.1 rafal vsize_t sz = BOOT_FUNC_END - BOOT_FUNC_START;
161 1.1 rafal
162 1.1 rafal // check 2nd bootloader size.
163 1.1 rafal if (sz > _mem->getPageSize()) {
164 1.1 rafal DPRINTF((TEXT("2nd bootloader size(%dbyte) is larger than page size(%d).\n"),
165 1.1 rafal sz, _mem->getPageSize()));
166 1.1 rafal return FALSE;
167 1.1 rafal }
168 1.1 rafal
169 1.1 rafal // get physical mapped page and copy loader to there.
170 1.1 rafal // don't writeback D-cache here. make sure to writeback before jump.
171 1.1 rafal if (!_mem->getPage(v , _loader_addr)) {
172 1.1 rafal DPRINTF((TEXT("can't get page for 2nd loader.\n")));
173 1.1 rafal return FALSE;
174 1.1 rafal }
175 1.1 rafal DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"),
176 1.1 rafal (unsigned)v,(unsigned)_loader_addr));
177 1.1 rafal
178 1.1 rafal memcpy(reinterpret_cast <LPVOID>(v),
179 1.1 rafal reinterpret_cast <LPVOID>(BOOT_FUNC_START), sz);
180 1.1 rafal DPRINTF((TEXT("2nd bootloader copy done.\n")));
181 1.1 rafal
182 1.1 rafal return TRUE;
183 1.1 rafal }
184 1.1 rafal
185 1.1 rafal void
186 1.1 rafal PXA2X0Architecture::jump(paddr_t info, paddr_t pvec)
187 1.1 rafal {
188 1.1 rafal kaddr_t sp;
189 1.1 rafal vaddr_t v;
190 1.1 rafal paddr_t p;
191 1.1 rafal
192 1.1 rafal // stack for bootloader
193 1.1 rafal _mem->getPage(v, p);
194 1.1 rafal sp = ptokv(p) + _mem->getPageSize();
195 1.1 rafal DPRINTF((TEXT("sp for bootloader = %08x + %08x = %08x\n"),
196 1.1 rafal ptokv(p), _mem->getPageSize(), sp));
197 1.1 rafal
198 1.1 rafal // writeback whole D-cache
199 1.1 rafal WritebackDCache();
200 1.1 rafal
201 1.1 rafal SetKMode(1);
202 1.3 nonaka FlatJump_pxa2x0(info, pvec, sp, _loader_addr);
203 1.1 rafal // NOTREACHED
204 1.3 nonaka SetKMode(0);
205 1.3 nonaka DPRINTF((TEXT("Return from FlatJump_pxa2x0.\n")));
206 1.3 nonaka }
207 1.3 nonaka
208 1.3 nonaka
209 1.3 nonaka //
210 1.3 nonaka // dump CS0
211 1.3 nonaka //
212 1.3 nonaka void
213 1.3 nonaka PXA2X0Architecture::dumpCS0(uint32_t size)
214 1.3 nonaka {
215 1.3 nonaka static char buf[0x1000];
216 1.3 nonaka vaddr_t mem;
217 1.3 nonaka uint32_t addr;
218 1.3 nonaka uint32_t off;
219 1.3 nonaka HANDLE fh;
220 1.3 nonaka unsigned long wrote;
221 1.3 nonaka
222 1.3 nonaka fh = CreateFile(TEXT("rom.bin"), GENERIC_WRITE, FILE_SHARE_READ,
223 1.3 nonaka 0, OPEN_ALWAYS, FILE_ATTRIBUTE_NORMAL, 0);
224 1.3 nonaka if (fh == INVALID_HANDLE_VALUE) {
225 1.3 nonaka DPRINTF((TEXT("can't open file. (%s)\n"), TEXT("rom.bin")));
226 1.3 nonaka return;
227 1.3 nonaka }
228 1.3 nonaka
229 1.3 nonaka for (addr = 0; addr < size; addr += 0x1000) {
230 1.3 nonaka memset(buf, 0, sizeof(buf));
231 1.3 nonaka mem = _mem->mapPhysicalPage(addr, 0x1000, PAGE_READWRITE);
232 1.3 nonaka for (off = 0; off < 0x1000; off++) {
233 1.3 nonaka buf[off] = VOLATILE_REF8(mem + off);
234 1.3 nonaka }
235 1.3 nonaka _mem->unmapPhysicalPage(mem);
236 1.3 nonaka WriteFile(fh, buf, 0x1000, &wrote, 0);
237 1.3 nonaka }
238 1.3 nonaka
239 1.3 nonaka CloseHandle(fh);
240 1.3 nonaka }
241 1.3 nonaka
242 1.3 nonaka //
243 1.3 nonaka // dump peripheral registers.
244 1.3 nonaka //
245 1.3 nonaka
246 1.3 nonaka #ifdef REGDUMP
247 1.3 nonaka #define PXA250_GPIO_REG_NUM 3
248 1.3 nonaka #define PXA250_GPIO_NUM 96
249 1.3 nonaka #define PXA270_GPIO_REG_NUM 4
250 1.3 nonaka #define PXA270_GPIO_NUM 121
251 1.3 nonaka
252 1.3 nonaka static const TCHAR *pxa270_gpioName[PXA270_GPIO_NUM][7] =
253 1.3 nonaka {
254 1.3 nonaka /*0*/ { TEXT("GPIO<0>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
255 1.3 nonaka /*1*/ { TEXT("GPIO<1>/nRESET_GPIO"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
256 1.3 nonaka /*2*/ { TEXT("SYS_EN5"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
257 1.3 nonaka /*3*/ { TEXT("GPIO<3>/PWR_SCL"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
258 1.3 nonaka /*4*/ { TEXT("GPIO<4>/PWR_SDA"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
259 1.3 nonaka /*5*/ { TEXT("PWR_CAP<0>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
260 1.3 nonaka /*6*/ { TEXT("PWR_CAP<1>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
261 1.3 nonaka /*7*/ { TEXT("PWR_CAP<2>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
262 1.3 nonaka /*8*/ { TEXT("PWR_CAP<3>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
263 1.3 nonaka /*9*/ { TEXT("GPIO<9>"),TEXT(""),TEXT(""),TEXT("FFCTS"),TEXT("HZ_CLK"),TEXT(""),TEXT("CHOUT<0>"), },
264 1.3 nonaka /*10*/ { TEXT("GPIO<10>"),TEXT("FFDCD"),TEXT(""),TEXT("USB_P3_57"),TEXT("HZ_CLK"),TEXT(""),TEXT("CHOUT<1>"), },
265 1.3 nonaka /*11*/ { TEXT("GPIO<11>"),TEXT("EXT_SYNC<0>"),TEXT("SSPRXD2"),TEXT("USB_P3_1"),TEXT("CHOUT<0>"),TEXT("PWM_OUT<2>"),TEXT("48_MHz"), },
266 1.3 nonaka /*12*/ { TEXT("GPIO<12>"),TEXT("EXT_SYNC<1>"),TEXT("CIF_DD<7>"),TEXT(""),TEXT("CHOUT<1>"),TEXT("PWM_OUT<3>"),TEXT("48_MHz"), },
267 1.3 nonaka /*13*/ { TEXT("GPIO<13>"),TEXT("CLK_EXT"),TEXT("KP_DKIN<7>"),TEXT("KP_MKIN<7>"),TEXT("SSPTXD2"),TEXT(""),TEXT(""), },
268 1.3 nonaka /*14*/ { TEXT("GPIO<14>"),TEXT("L_VSYNC"),TEXT("SSPSFRM2"),TEXT(""),TEXT(""),TEXT("SSPSFRM2"),TEXT("UCLK"), },
269 1.3 nonaka /*15*/ { TEXT("GPIO<15>"),TEXT(""),TEXT(""),TEXT(""),TEXT("nPCE<1>"),TEXT("nCS<1>"),TEXT(""), },
270 1.3 nonaka /*16*/ { TEXT("GPIO<16>"),TEXT("KP_MKIN<5>"),TEXT(""),TEXT(""),TEXT(""),TEXT("PWM_OUT<0>"),TEXT("FFTXD"), },
271 1.3 nonaka /*17*/ { TEXT("GPIO<17>"),TEXT("KP_MKIN<6>"),TEXT("CIF_DD<6>"),TEXT(""),TEXT(""),TEXT("PWM_OUT<1>"),TEXT(""), },
272 1.3 nonaka /*18*/ { TEXT("GPIO<18>"),TEXT("RDY"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
273 1.3 nonaka /*19*/ { TEXT("GPIO<19>"),TEXT("SSPSCLK2"),TEXT(""),TEXT("FFRXD"),TEXT("SSPSCLK2"),TEXT("L_CS"),TEXT("nURST"), },
274 1.3 nonaka /*20*/ { TEXT("GPIO<20>"),TEXT("DREQ<0>"),TEXT("MBREQ"),TEXT(""),TEXT("nSDCS<2>"),TEXT(""),TEXT(""), },
275 1.3 nonaka /*21*/ { TEXT("GPIO<21>"),TEXT(""),TEXT(""),TEXT(""),TEXT("nSDCS<3>"),TEXT("DVAL<0>"),TEXT("MBGNT"), },
276 1.3 nonaka /*22*/ { TEXT("GPIO<22>"),TEXT("SSPEXTCLK2"),TEXT("SSPSCLK2EN"),TEXT("SSPSCLK2"),TEXT("KP_MKOUT<7>"),TEXT("SSPSYSCLK2"),TEXT("SSPSCLK2"), },
277 1.3 nonaka /*23*/ { TEXT("GPIO<23>"),TEXT(""),TEXT("SSPSCLK"),TEXT(""),TEXT("CIF_MCLK"),TEXT("SSPSCLK"),TEXT(""), },
278 1.3 nonaka /*24*/ { TEXT("GPIO<24>"),TEXT("CIF_FV"),TEXT("SSPSFRM"),TEXT(""),TEXT("CIF_FV"),TEXT("SSPSFRM"),TEXT(""), },
279 1.3 nonaka /*25*/ { TEXT("GPIO<25>"),TEXT("CIF_LV"),TEXT(""),TEXT(""),TEXT("CIF_LV"),TEXT("SSPTXD"),TEXT(""), },
280 1.3 nonaka /*26*/ { TEXT("GPIO<26>"),TEXT("SSPRXD"),TEXT("CIF_PCLK"),TEXT("FFCTS"),TEXT(""),TEXT(""),TEXT(""), },
281 1.3 nonaka /*27*/ { TEXT("GPIO<27>"),TEXT("SSPEXTCLK"),TEXT("SSPSCLKEN"),TEXT("CIF_DD<0>"),TEXT("SSPSYSCLK"),TEXT(""),TEXT("FFRTS"), },
282 1.3 nonaka /*28*/ { TEXT("GPIO<28>"),TEXT("AC97_BITCLK"),TEXT("I2S_BITCLK"),TEXT("SSPSFRM"),TEXT("I2S_BITCLK"),TEXT(""),TEXT("SSPSFRM"), },
283 1.3 nonaka /*29*/ { TEXT("GPIO<29>"),TEXT("AC97_SDATA_IN_0"),TEXT("I2S_SDATA_IN"),TEXT("SSPSCLK"),TEXT("SSPRXD2"),TEXT(""),TEXT("SSPSCLK"), },
284 1.3 nonaka /*30*/ { TEXT("GPIO<30>"),TEXT(""),TEXT(""),TEXT(""),TEXT("I2S_SDATA_OUT"),TEXT("AC97_SDATA_OUT"),TEXT("USB_P3_2"), },
285 1.3 nonaka /*31*/ { TEXT("GPIO<31>"),TEXT(""),TEXT(""),TEXT(""),TEXT("I2S_SYNC"),TEXT("AC97_SYNC"),TEXT("USB_P3_6"), },
286 1.3 nonaka /*32*/ { TEXT("GPIO<32>"),TEXT(""),TEXT(""),TEXT(""),TEXT("MSSCLK"),TEXT("MMCLK"),TEXT(""), },
287 1.3 nonaka /*33*/ { TEXT("GPIO<33>"),TEXT("FFRXD"),TEXT("FFDSR"),TEXT(""),TEXT("DVAL<1>"),TEXT("nCS<5>"),TEXT("MBGNT"), },
288 1.3 nonaka /*34*/ { TEXT("GPIO<34>"),TEXT("FFRXD"),TEXT("KP_MKIN<3>"),TEXT("SSPSCLK3"),TEXT("USB_P2_2"),TEXT(""),TEXT("SSPSCLK3"), },
289 1.3 nonaka /*35*/ { TEXT("GPIO<35>"),TEXT("FFCTS"),TEXT("USB_P2_1"),TEXT("SSPSFRM3"),TEXT(""),TEXT("KP_MKOUT<6>"),TEXT("SSPTXD3"), },
290 1.3 nonaka /*36*/ { TEXT("GPIO<36>"),TEXT("FFDCD"),TEXT("SSPSCLK2"),TEXT("KP_MKIN<7>"),TEXT("USB_P2_4"),TEXT("SSPSCLK2"),TEXT(""), },
291 1.3 nonaka /*37*/ { TEXT("GPIO<37>"),TEXT("FFDSR"),TEXT("SSPSFRM2"),TEXT("KP_MKIN<3>"),TEXT("USB_P2_8"),TEXT("SSPSFRM2"),TEXT("FFTXD"), },
292 1.3 nonaka /*38*/ { TEXT("GPIO<38>"),TEXT("FFRI"),TEXT("KP_MKIN<4>"),TEXT("USB_P2_3"),TEXT("SSPTXD3"),TEXT("SSPTXD2"),TEXT("PWM_OUT<1>"), },
293 1.3 nonaka /*39*/ { TEXT("GPIO<39>"),TEXT("KP_MKIN<4>"),TEXT(""),TEXT("SSPSFRM3"),TEXT("USB_P2_6"),TEXT("FFTXD"),TEXT("SSPSFRM3"), },
294 1.3 nonaka /*40*/ { TEXT("GPIO<40>"),TEXT("SSPRXD2"),TEXT(""),TEXT("USB_P2_5"),TEXT("KP_MKOUT<6>"),TEXT("FFDTR"),TEXT("SSPSCLK3"), },
295 1.3 nonaka /*41*/ { TEXT("GPIO<41>"),TEXT("FFRXD"),TEXT("USB_P2_7"),TEXT("SSPRXD3"),TEXT("KP_MKOUT<7>"),TEXT("FFRTS"),TEXT(""), },
296 1.3 nonaka /*42*/ { TEXT("GPIO<42>"),TEXT("BTRXD"),TEXT("ICP_RXD"),TEXT(""),TEXT(""),TEXT(""),TEXT("CIF_MCLK"), },
297 1.3 nonaka /*43*/ { TEXT("GPIO<43>"),TEXT(""),TEXT(""),TEXT("CIF_FV"),TEXT("ICP_TXD"),TEXT("BTTXD"),TEXT("CIF_FV"), },
298 1.3 nonaka /*44*/ { TEXT("GPIO<44>"),TEXT("BTCTS"),TEXT(""),TEXT("CIF_LV"),TEXT(""),TEXT(""),TEXT("CIF_LV"), },
299 1.3 nonaka /*45*/ { TEXT("GPIO<45>"),TEXT(""),TEXT(""),TEXT("CIF_PCLK"),TEXT("AC97_SYSCLK"),TEXT("BTRTS"),TEXT("SSPSYSCLK3"), },
300 1.3 nonaka /*46*/ { TEXT("GPIO<46>"),TEXT("ICP_RXD"),TEXT("STD_RXD"),TEXT(""),TEXT(""),TEXT("PWM_OUT<2>"),TEXT(""), },
301 1.3 nonaka /*47*/ { TEXT("GPIO<47>"),TEXT("CIF_DD<0>"),TEXT(""),TEXT(""),TEXT("STD_TXD"),TEXT("ICP_TXD"),TEXT("PWM_OUT<3>"), },
302 1.3 nonaka /*48*/ { TEXT("GPIO<48>"),TEXT("CIF_DD<5>"),TEXT(""),TEXT(""),TEXT("BB_OB_DAT<1>"),TEXT("nPOE"),TEXT(""), },
303 1.3 nonaka /*49*/ { TEXT("GPIO<49>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT("nPWE"),TEXT(""), },
304 1.3 nonaka /*50*/ { TEXT("GPIO<50>"),TEXT("CIF_DD<3>"),TEXT(""),TEXT("SSPSCLK2"),TEXT("BB_OB_DAT<2>"),TEXT("nPIOR"),TEXT("SSPSCLK2"), },
305 1.3 nonaka /*51*/ { TEXT("GPIO<51>"),TEXT("CIF_DD<2>"),TEXT(""),TEXT(""),TEXT("BB_OB_DAT<3>"),TEXT("nPIOW"),TEXT(""), },
306 1.3 nonaka /*52*/ { TEXT("GPIO<52>"),TEXT("CIF_DD<4>"),TEXT("SSPSCLK3"),TEXT(""),TEXT("BB_OB_CLK"),TEXT("SSPSCLK3"),TEXT(""), },
307 1.3 nonaka /*53*/ { TEXT("GPIO<53>"),TEXT("FFRXD"),TEXT("USB_P2_3"),TEXT(""),TEXT("BB_OB_STB"),TEXT("CIF_MCLK"),TEXT("SSPSYSCLK"), },
308 1.3 nonaka /*54*/ { TEXT("GPIO<54>"),TEXT(""),TEXT("BB_OB_WAIT"),TEXT("CIF_PCLK"),TEXT(""),TEXT("nPCE<2>"),TEXT(""), },
309 1.3 nonaka /*55*/ { TEXT("GPIO<55>"),TEXT("CIF_DD<1>"),TEXT("BB_IB_DAT<1>"),TEXT(""),TEXT(""),TEXT("nPREG"),TEXT(""), },
310 1.3 nonaka /*56*/ { TEXT("GPIO<56>"),TEXT("nPWAIT"),TEXT("BB_IB_DAT<2>"),TEXT(""),TEXT("USB_P3_4"),TEXT(""),TEXT(""), },
311 1.3 nonaka /*57*/ { TEXT("GPIO<57>"),TEXT("nIOIS16"),TEXT("BB_IB_DAT<3>"),TEXT(""),TEXT(""),TEXT(""),TEXT("SSPTXD"), },
312 1.3 nonaka /*58*/ { TEXT("GPIO<58>"),TEXT(""),TEXT("LDD<0>"),TEXT(""),TEXT(""),TEXT("LDD<0>"),TEXT(""), },
313 1.3 nonaka /*59*/ { TEXT("GPIO<59>"),TEXT(""),TEXT("LDD<1>"),TEXT(""),TEXT(""),TEXT("LDD<1>"),TEXT(""), },
314 1.3 nonaka /*60*/ { TEXT("GPIO<60>"),TEXT(""),TEXT("LDD<2>"),TEXT(""),TEXT(""),TEXT("LDD<2>"),TEXT(""), },
315 1.3 nonaka /*61*/ { TEXT("GPIO<61>"),TEXT(""),TEXT("LDD<3>"),TEXT(""),TEXT(""),TEXT("LDD<3>"),TEXT(""), },
316 1.3 nonaka /*62*/ { TEXT("GPIO<62>"),TEXT(""),TEXT("LDD<4>"),TEXT(""),TEXT(""),TEXT("LDD<4>"),TEXT(""), },
317 1.3 nonaka /*63*/ { TEXT("GPIO<63>"),TEXT(""),TEXT("LDD<5>"),TEXT(""),TEXT(""),TEXT("LDD<5>"),TEXT(""), },
318 1.3 nonaka /*64*/ { TEXT("GPIO<64>"),TEXT(""),TEXT("LDD<6>"),TEXT(""),TEXT(""),TEXT("LDD<6>"),TEXT(""), },
319 1.3 nonaka /*65*/ { TEXT("GPIO<65>"),TEXT(""),TEXT("LDD<7>"),TEXT(""),TEXT(""),TEXT("LDD<7>"),TEXT(""), },
320 1.3 nonaka /*66*/ { TEXT("GPIO<66>"),TEXT(""),TEXT("LDD<8>"),TEXT(""),TEXT(""),TEXT("LDD<8>"),TEXT(""), },
321 1.3 nonaka /*67*/ { TEXT("GPIO<67>"),TEXT(""),TEXT("LDD<9>"),TEXT(""),TEXT(""),TEXT("LDD<9>"),TEXT(""), },
322 1.3 nonaka /*68*/ { TEXT("GPIO<68>"),TEXT(""),TEXT("LDD<10>"),TEXT(""),TEXT(""),TEXT("LDD<10>"),TEXT(""), },
323 1.3 nonaka /*69*/ { TEXT("GPIO<69>"),TEXT(""),TEXT("LDD<11>"),TEXT(""),TEXT(""),TEXT("LDD<11>"),TEXT(""), },
324 1.3 nonaka /*70*/ { TEXT("GPIO<70>"),TEXT(""),TEXT("LDD<12>"),TEXT(""),TEXT(""),TEXT("LDD<12>"),TEXT(""), },
325 1.3 nonaka /*71*/ { TEXT("GPIO<71>"),TEXT(""),TEXT("LDD<13>"),TEXT(""),TEXT(""),TEXT("LDD<13>"),TEXT(""), },
326 1.3 nonaka /*72*/ { TEXT("GPIO<72>"),TEXT(""),TEXT("LDD<14>"),TEXT(""),TEXT(""),TEXT("LDD<14>"),TEXT(""), },
327 1.3 nonaka /*73*/ { TEXT("GPIO<73>"),TEXT(""),TEXT("LDD<15>"),TEXT(""),TEXT(""),TEXT("LDD<15>"),TEXT(""), },
328 1.3 nonaka /*74*/ { TEXT("GPIO<74>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT("L_FCLK_RD"),TEXT(""), },
329 1.3 nonaka /*75*/ { TEXT("GPIO<75>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT("L_LCLK_A0"),TEXT(""), },
330 1.3 nonaka /*76*/ { TEXT("GPIO<76>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT("L_PCLK_WR"),TEXT(""), },
331 1.3 nonaka /*77*/ { TEXT("GPIO<77>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT("L_BIAS"),TEXT(""), },
332 1.3 nonaka /*78*/ { TEXT("GPIO<78>"),TEXT(""),TEXT(""),TEXT(""),TEXT("nPCE<2>"),TEXT("nCS<2>"),TEXT(""), },
333 1.3 nonaka /*79*/ { TEXT("GPIO<79>"),TEXT(""),TEXT(""),TEXT(""),TEXT("PSKTSEL"),TEXT("nCS<3>"),TEXT("PWM_OUT<2>"), },
334 1.3 nonaka /*80*/ { TEXT("GPIO<80>"),TEXT("DREQ<1>"),TEXT("MBREQ"),TEXT(""),TEXT(""),TEXT("nCS<4>"),TEXT("PWM_OUT<3>"), },
335 1.3 nonaka /*81*/ { TEXT("GPIO<81>"),TEXT(""),TEXT("CIF_DD<0>"),TEXT(""),TEXT("SSPTXD3"),TEXT("BB_OB_DAT<0>"),TEXT(""), },
336 1.3 nonaka /*82*/ { TEXT("GPIO<82>"),TEXT("SSPRXD3"),TEXT("BB_IB_DAT<0>"),TEXT("CIF_DD<5>"),TEXT(""),TEXT(""),TEXT("FFDTR"), },
337 1.3 nonaka /*83*/ { TEXT("GPIO<83>"),TEXT("SSPSFRM3"),TEXT("BB_IB_CLK"),TEXT("CIF_DD<4>"),TEXT("SSPSFRM3"),TEXT("FFTXD"),TEXT("FFRTS"), },
338 1.3 nonaka /*84*/ { TEXT("GPIO<84>"),TEXT("SSPCLK3"),TEXT("BB_IB_STB"),TEXT("CIF_FV"),TEXT("SSPCLK3"),TEXT(""),TEXT("CIF_FV"), },
339 1.3 nonaka /*85*/ { TEXT("GPIO<85>"),TEXT("FFRXD"),TEXT("DREQ<2>"),TEXT("CIF_LV"),TEXT("nPCE<1>"),TEXT("BB_IB_WAIT"),TEXT("CIF_LV"), },
340 1.3 nonaka /*86*/ { TEXT("GPIO<86>"),TEXT("SSPRXD2"),TEXT("LDD<16>"),TEXT("USB_P3_5"),TEXT("nPCE<1>"),TEXT("LDD<16>"),TEXT(""), },
341 1.3 nonaka /*87*/ { TEXT("GPIO<87>"),TEXT("nPCE<2>"),TEXT("LDD<17>"),TEXT("USB_P3_1"),TEXT("SSPTXD2"),TEXT("LDD<17>"),TEXT("SSPSFRM2"), },
342 1.3 nonaka /*88*/ { TEXT("GPIO<88>"),TEXT("USBHPWR<1>"),TEXT("SSPRXD2"),TEXT("SSPSFRM2"),TEXT(""),TEXT(""),TEXT("SSPSFRM2"), },
343 1.3 nonaka /*89*/ { TEXT("GPIO<89>"),TEXT("SSPRXD3"),TEXT(""),TEXT("FFRI"),TEXT("AC97_SYSCLK"),TEXT("USBHPEN<1>"),TEXT("SSPTXD2"), },
344 1.3 nonaka /*90*/ { TEXT("GPIO<90>"),TEXT("KP_MKIN<5>"),TEXT("USB_P3_5"),TEXT("CIF_DD<4>"),TEXT(""),TEXT("nURST"),TEXT(""), },
345 1.3 nonaka /*91*/ { TEXT("GPIO<91>"),TEXT("KP_MKIN<6>"),TEXT("USB_P3_1"),TEXT("CIF_DD<5>"),TEXT(""),TEXT("UCLK"),TEXT(""), },
346 1.3 nonaka /*92*/ { TEXT("GPIO<92>"),TEXT("MMDAT<0>"),TEXT(""),TEXT(""),TEXT("MMDAT<0>"),TEXT("MSBS"),TEXT(""), },
347 1.3 nonaka /*93*/ { TEXT("GPIO<93>"),TEXT("KP_DKIN<0>"),TEXT("CIF_DD<6>"),TEXT(""),TEXT("AC97_SDATA_OUT"),TEXT(""),TEXT(""), },
348 1.3 nonaka /*94*/ { TEXT("GPIO<94>"),TEXT("KP_DKIN<1>"),TEXT("CIF_DD<5>"),TEXT(""),TEXT("AC97_SYNC"),TEXT(""),TEXT(""), },
349 1.3 nonaka /*95*/ { TEXT("GPIO<95>"),TEXT("KP_DKIN<2>"),TEXT("CIF_DD<4>"),TEXT("KP_MKIN<6>"),TEXT("AC97_RESET_n"),TEXT(""),TEXT(""), },
350 1.3 nonaka /*96*/ { TEXT("GPIO<96>"),TEXT("KP_DKIN<3>"),TEXT("MBREQ"),TEXT("FFRXD"),TEXT(""),TEXT("DVAL<1>"),TEXT("KP_MKOUT<6>"), },
351 1.3 nonaka /*97*/ { TEXT("GPIO<97>"),TEXT("KP_DKIN<4>"),TEXT("DREQ<1>"),TEXT("KP_MKIN<3>"),TEXT(""),TEXT("MBGNT"),TEXT(""), },
352 1.3 nonaka /*98*/ { TEXT("GPIO<98>"),TEXT("KP_DKIN<5>"),TEXT("CIF_DD<0>"),TEXT("KP_MKIN<4>"),TEXT("AC97_SYSCLK"),TEXT(""),TEXT("FFRTS"), },
353 1.3 nonaka /*99*/ { TEXT("GPIO<99>"),TEXT("KP_DKIN<6>"),TEXT("AC97_SDATA_IN_1"),TEXT("KP_MKIN<5>"),TEXT(""),TEXT(""),TEXT("FFTXD"), },
354 1.3 nonaka /*100*/ { TEXT("GPIO<100>"),TEXT("KP_MKIN<0>"),TEXT("DREQ<2>"),TEXT("FFCTS"),TEXT(""),TEXT(""),TEXT(""), },
355 1.3 nonaka /*101*/ { TEXT("GPIO<101>"),TEXT("KP_MKIN<1>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
356 1.3 nonaka /*102*/ { TEXT("GPIO<102>"),TEXT("KP_MKIN<2>"),TEXT(""),TEXT("FFRXD"),TEXT("nPCE<1>"),TEXT(""),TEXT(""), },
357 1.3 nonaka /*103*/ { TEXT("GPIO<103>"),TEXT("CIF_DD<3>"),TEXT(""),TEXT(""),TEXT(""),TEXT("KP_MKOUT<0>"),TEXT(""), },
358 1.3 nonaka /*104*/ { TEXT("GPIO<104>"),TEXT("CIF_DD<2>"),TEXT(""),TEXT(""),TEXT("PSKTSEL"),TEXT("KP_MKOUT<1>"),TEXT(""), },
359 1.3 nonaka /*105*/ { TEXT("GPIO<105>"),TEXT("CIF_DD<1>"),TEXT(""),TEXT(""),TEXT("nPCE<2>"),TEXT("KP_MKOUT<2>"),TEXT(""), },
360 1.3 nonaka /*106*/ { TEXT("GPIO<106>"),TEXT("CIF_DD<9>"),TEXT(""),TEXT(""),TEXT(""),TEXT("KP_MKOUT<3>"),TEXT(""), },
361 1.3 nonaka /*107*/ { TEXT("GPIO<107>"),TEXT("CIF_DD<8>"),TEXT(""),TEXT(""),TEXT(""),TEXT("KP_MKOUT<4>"),TEXT(""), },
362 1.3 nonaka /*108*/ { TEXT("GPIO<108>"),TEXT("CIF_DD<7>"),TEXT(""),TEXT(""),TEXT("CHOUT<0>"),TEXT("KP_MKOUT<5>"),TEXT(""), },
363 1.3 nonaka /*109*/ { TEXT("GPIO<109>"),TEXT("MMDAT<1>"),TEXT("MSSDIO"),TEXT(""),TEXT("MMDAT<1>"),TEXT("MSSDIO"),TEXT(""), },
364 1.3 nonaka /*110*/ { TEXT("GPIO<110>"),TEXT("MMDAT<2>/MMCCS<0>"),TEXT(""),TEXT(""),TEXT("MMDAT<2>/MMCCS<0>"),TEXT(""),TEXT(""), },
365 1.3 nonaka /*111*/ { TEXT("GPIO<111>"),TEXT("MMDAT<3>/MMCCS<1>"),TEXT(""),TEXT(""),TEXT("MMDAT<3>/MMCCS<1>"),TEXT(""),TEXT(""), },
366 1.3 nonaka /*112*/ { TEXT("GPIO<112>"),TEXT("MMCMD"),TEXT("nMSINS"),TEXT(""),TEXT("MMCMD"),TEXT(""),TEXT(""), },
367 1.3 nonaka /*113*/ { TEXT("GPIO<113>"),TEXT(""),TEXT(""),TEXT("USB_P3_3"),TEXT("I2S_SYSCLK"),TEXT("AC97_RESET_n"),TEXT(""), },
368 1.3 nonaka /*114*/ { TEXT("GPIO<114>"),TEXT("CIF_DD<1>"),TEXT(""),TEXT(""),TEXT("UEN"),TEXT("UVS0"),TEXT(""), },
369 1.3 nonaka /*115*/ { TEXT("GPIO<115>"),TEXT("DREQ<0>"),TEXT("CIF_DD<3>"),TEXT("MBREQ"),TEXT("UEN"),TEXT("nUVS1"),TEXT("PWM_OUT<1>"), },
370 1.3 nonaka /*116*/ { TEXT("GPIO<116>"),TEXT("CIF_DD<2>"),TEXT("AC97_SDATA_IN_0"),TEXT("UDET"),TEXT("DVAL<0>"),TEXT("nUVS2"),TEXT("MBGNT"), },
371 1.3 nonaka /*117*/ { TEXT("GPIO<117>"),TEXT("SCL"),TEXT(""),TEXT(""),TEXT("SCL"),TEXT(""),TEXT(""), },
372 1.3 nonaka /*118*/ { TEXT("GPIO<118>"),TEXT("SDA"),TEXT(""),TEXT(""),TEXT("SDA"),TEXT(""),TEXT(""), },
373 1.3 nonaka /*119*/ { TEXT("GPIO<119>"),TEXT("USBHPWR<2>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
374 1.3 nonaka /*120*/ { TEXT("GPIO<120>"),TEXT("USBHPEN<2>"),TEXT(""),TEXT(""),TEXT(""),TEXT(""),TEXT(""), },
375 1.3 nonaka };
376 1.3 nonaka #endif
377 1.3 nonaka
378 1.3 nonaka void
379 1.3 nonaka PXA2X0Architecture::dumpPeripheralRegs(void)
380 1.3 nonaka {
381 1.3 nonaka #ifdef REGDUMP
382 1.3 nonaka uint32_t reg;
383 1.3 nonaka bool first;
384 1.3 nonaka int i, n;
385 1.3 nonaka
386 1.3 nonaka #define GPIO_OFFSET(r,o) ((r == 3) ? (o + 0x100) : (o + (r * 4)))
387 1.3 nonaka // GPIO
388 1.3 nonaka if (platid_match(&platid, &platid_mask_CPU_ARM_XSCALE_PXA270))
389 1.3 nonaka n = PXA270_GPIO_REG_NUM;
390 1.3 nonaka else
391 1.3 nonaka n = PXA250_GPIO_REG_NUM;
392 1.3 nonaka
393 1.3 nonaka vaddr_t gpio =
394 1.3 nonaka _mem->mapPhysicalPage(0x40e00000, 0x1000, PAGE_READWRITE);
395 1.3 nonaka DPRINTF((TEXT("Dump GPIO registers.\n")));
396 1.3 nonaka for (i = 0; i < n; i++) {
397 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x00));
398 1.3 nonaka DPRINTF((TEXT("GPLR%d: 0x%08x\n"), i, reg));
399 1.3 nonaka }
400 1.3 nonaka for (i = 0; i < n; i++) {
401 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x0c));
402 1.3 nonaka DPRINTF((TEXT("GPDR%d: 0x%08x\n"), i, reg));
403 1.3 nonaka }
404 1.3 nonaka #if 0 /* write-only register */
405 1.3 nonaka for (i = 0; i < n; i++) {
406 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x18));
407 1.3 nonaka DPRINTF((TEXT("GPSR%d: 0x%08x\n"), reg));
408 1.3 nonaka }
409 1.3 nonaka for (i = 0; i < n; i++) {
410 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x24));
411 1.3 nonaka DPRINTF((TEXT("GPCR%d: 0x%08x\n"), reg));
412 1.3 nonaka }
413 1.3 nonaka #endif
414 1.3 nonaka for (i = 0; i < n; i++) {
415 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x30));
416 1.3 nonaka DPRINTF((TEXT("GRER%d: 0x%08x\n"), i, reg));
417 1.3 nonaka }
418 1.3 nonaka for (i = 0; i < n; i++) {
419 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x3c));
420 1.3 nonaka DPRINTF((TEXT("GFER%d: 0x%08x\n"), i, reg));
421 1.3 nonaka }
422 1.3 nonaka for (i = 0; i < n; i++) {
423 1.3 nonaka reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x48));
424 1.3 nonaka DPRINTF((TEXT("GEDR%d: 0x%08x\n"), i, reg));
425 1.3 nonaka }
426 1.3 nonaka for (i = 0; i < n; i++) {
427 1.3 nonaka reg = VOLATILE_REF(gpio + 0x54 + (i * 8));
428 1.3 nonaka DPRINTF((TEXT("GAFR%d_L: 0x%08x\n"), i, reg));
429 1.3 nonaka reg = VOLATILE_REF(gpio + 0x58 + (i * 8));
430 1.3 nonaka DPRINTF((TEXT("GAFR%d_U: 0x%08x\n"), i, reg));
431 1.3 nonaka }
432 1.3 nonaka
433 1.3 nonaka //
434 1.3 nonaka // display detail
435 1.3 nonaka //
436 1.3 nonaka
437 1.3 nonaka if (!platid_match(&platid, &platid_mask_CPU_ARM_XSCALE_PXA270))
438 1.3 nonaka return;
439 1.3 nonaka
440 1.3 nonaka // header
441 1.3 nonaka DPRINTF((TEXT("pin#,function,name,rising,falling,status\n")));
442 1.3 nonaka
443 1.3 nonaka n = PXA270_GPIO_NUM;
444 1.3 nonaka for (i = 0; i < n; i++) {
445 1.3 nonaka const TCHAR *fn_name, *pin_name;
446 1.3 nonaka uint32_t dir, altfn, redge, fedge, status;
447 1.3 nonaka
448 1.3 nonaka // pin function
449 1.3 nonaka dir = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x0c));
450 1.3 nonaka dir = (dir >> (i % 32)) & 1;
451 1.3 nonaka altfn = VOLATILE_REF(gpio + 0x54 + ((i / 16) * 4));
452 1.3 nonaka altfn = (altfn >> ((i % 16) * 2)) & 3;
453 1.3 nonaka if (altfn == 0) {
454 1.3 nonaka if (dir == 0) {
455 1.3 nonaka fn_name = TEXT("GPIO_IN");
456 1.3 nonaka } else {
457 1.3 nonaka fn_name = TEXT("GPIO_OUT");
458 1.3 nonaka }
459 1.3 nonaka DPRINTF((TEXT("%d,%s,%s,"), i, fn_name,
460 1.3 nonaka pxa270_gpioName[i][0]));
461 1.3 nonaka } else {
462 1.3 nonaka if (dir == 0) {
463 1.3 nonaka fn_name = TEXT("IN");
464 1.3 nonaka pin_name = pxa270_gpioName[i][altfn];
465 1.3 nonaka } else {
466 1.3 nonaka fn_name = TEXT("OUT");
467 1.3 nonaka pin_name = pxa270_gpioName[i][altfn+3];
468 1.3 nonaka }
469 1.3 nonaka DPRINTF((TEXT("%d,ALT_FN_%d_%s,%s,"), i, altfn,
470 1.3 nonaka fn_name, pin_name));
471 1.3 nonaka }
472 1.3 nonaka
473 1.3 nonaka // edge detect
474 1.3 nonaka redge = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x30));
475 1.3 nonaka redge = (redge >> (i % 32)) & 1;
476 1.3 nonaka fedge = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x3c));
477 1.3 nonaka fedge = (fedge >> (i % 32)) & 1;
478 1.3 nonaka DPRINTF((TEXT("%s,%s,"),
479 1.3 nonaka redge ? TEXT("enable") : TEXT("disable"),
480 1.3 nonaka fedge ? TEXT("enable") : TEXT("disable")));
481 1.3 nonaka
482 1.3 nonaka // status
483 1.3 nonaka status = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x00));
484 1.3 nonaka status = (status >> (i % 32)) & 1;
485 1.3 nonaka DPRINTF((TEXT("%s"), status ? TEXT("high") : TEXT("low")));
486 1.3 nonaka
487 1.3 nonaka DPRINTF((TEXT("\n")));
488 1.3 nonaka }
489 1.3 nonaka _mem->unmapPhysicalPage(gpio);
490 1.3 nonaka
491 1.3 nonaka // LCDC
492 1.3 nonaka DPRINTF((TEXT("Dump LCDC registers.\n")));
493 1.3 nonaka vaddr_t lcdc =
494 1.3 nonaka _mem->mapPhysicalPage(0x44000000, 0x1000, PAGE_READWRITE);
495 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x00);
496 1.3 nonaka DPRINTF((TEXT("LCCR0: 0x%08x\n"), reg));
497 1.3 nonaka DPRINTF((TEXT("-> ")));
498 1.3 nonaka first = true;
499 1.3 nonaka if (reg & (1U << 26)) {
500 1.3 nonaka DPRINTF((TEXT("%sLDDALT"), first ? TEXT("") : TEXT("/")));
501 1.3 nonaka first = false;
502 1.3 nonaka }
503 1.3 nonaka if (reg & (1U << 25)) {
504 1.3 nonaka DPRINTF((TEXT("%sOUC"), first ? TEXT("") : TEXT("/")));
505 1.3 nonaka first = false;
506 1.3 nonaka }
507 1.3 nonaka if (reg & (1U << 22)) {
508 1.3 nonaka DPRINTF((TEXT("%sLCDT"), first ? TEXT("") : TEXT("/")));
509 1.3 nonaka first = false;
510 1.3 nonaka }
511 1.3 nonaka if (reg & (1U << 9)) {
512 1.3 nonaka DPRINTF((TEXT("%sDPD"), first ? TEXT("") : TEXT("/")));
513 1.3 nonaka first = false;
514 1.3 nonaka }
515 1.3 nonaka if (reg & (1U << 7)) {
516 1.3 nonaka DPRINTF((TEXT("%sPAS"), first ? TEXT("") : TEXT("/")));
517 1.3 nonaka first = false;
518 1.3 nonaka }
519 1.3 nonaka if (reg & (1U << 2)) {
520 1.3 nonaka DPRINTF((TEXT("%sSDS"), first ? TEXT("") : TEXT("/")));
521 1.3 nonaka first = false;
522 1.3 nonaka }
523 1.3 nonaka if (reg & (1U << 1)) {
524 1.3 nonaka DPRINTF((TEXT("%sCMS"), first ? TEXT("") : TEXT("/")));
525 1.3 nonaka first = false;
526 1.3 nonaka }
527 1.3 nonaka if (reg & (1U << 0)) {
528 1.3 nonaka DPRINTF((TEXT("%sENB"), first ? TEXT("") : TEXT("/")));
529 1.3 nonaka first = false;
530 1.3 nonaka }
531 1.3 nonaka DPRINTF((TEXT("\n")));
532 1.3 nonaka DPRINTF((TEXT("-> PDD = 0x%02x\n"), (reg >> 12) & 0xff));
533 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x04);
534 1.3 nonaka DPRINTF((TEXT("LCCR1: 0x%08x\n"), reg));
535 1.3 nonaka DPRINTF((TEXT("-> BLW = 0x%02x, ELW = 0x%02x, HSW = 0x%02x, PPL = 0x%03x\n"),
536 1.3 nonaka (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 10) & 0x3f,
537 1.3 nonaka reg & 0x3ff));
538 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x08);
539 1.3 nonaka DPRINTF((TEXT("LCCR2: 0x%08x\n"), reg));
540 1.3 nonaka DPRINTF((TEXT("-> BFW = 0x%02x, EFW = 0x%02x, VSW = 0x%02x, LPP = 0x%03x\n"),
541 1.3 nonaka (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 10) & 0x3f,
542 1.3 nonaka reg & 0x3ff));
543 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x0c);
544 1.3 nonaka DPRINTF((TEXT("LCCR3: 0x%08x\n"), reg));
545 1.3 nonaka DPRINTF((TEXT("-> ")));
546 1.3 nonaka first = true;
547 1.3 nonaka if (reg & (1U << 27)) {
548 1.3 nonaka DPRINTF((TEXT("%sDPC"), first ? TEXT("") : TEXT("/")));
549 1.3 nonaka first = false;
550 1.3 nonaka }
551 1.3 nonaka if (reg & (1U << 23)) {
552 1.3 nonaka DPRINTF((TEXT("%sOEP"), first ? TEXT("") : TEXT("/")));
553 1.3 nonaka first = false;
554 1.3 nonaka }
555 1.3 nonaka if (reg & (1U << 22)) {
556 1.3 nonaka DPRINTF((TEXT("%sPCP"), first ? TEXT("") : TEXT("/")));
557 1.3 nonaka first = false;
558 1.3 nonaka }
559 1.3 nonaka if (reg & (1U << 21)) {
560 1.3 nonaka DPRINTF((TEXT("%sHSP"), first ? TEXT("") : TEXT("/")));
561 1.3 nonaka first = false;
562 1.3 nonaka }
563 1.3 nonaka if (reg & (1U << 20)) {
564 1.3 nonaka DPRINTF((TEXT("%sVSP"), first ? TEXT("") : TEXT("/")));
565 1.3 nonaka first = false;
566 1.3 nonaka }
567 1.3 nonaka if (reg & (1U << 19)) {
568 1.3 nonaka DPRINTF((TEXT("%sVSP"), first ? TEXT("") : TEXT("/")));
569 1.3 nonaka first = false;
570 1.3 nonaka }
571 1.3 nonaka DPRINTF((TEXT("\n")));
572 1.3 nonaka DPRINTF((TEXT("-> PDFOR = %d\n"), (reg >> 30) & 3));
573 1.3 nonaka DPRINTF((TEXT("-> BPP = 0x%02x\n"), ((reg >> 29) & 1 << 3) | ((reg >> 24) & 7)));
574 1.3 nonaka DPRINTF((TEXT("-> API = 0x%x\n"), (reg >> 16) & 0xf));
575 1.3 nonaka DPRINTF((TEXT("-> ACB = 0x%02x\n"), (reg >> 8) & 0xff));
576 1.3 nonaka DPRINTF((TEXT("-> PCD = 0x%02x\n"), reg & 0xff));
577 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x10);
578 1.3 nonaka DPRINTF((TEXT("LCCR4: 0x%08x\n"), reg));
579 1.3 nonaka DPRINTF((TEXT("-> PCDDIV = %d\n"), (reg >> 31) & 1));
580 1.3 nonaka DPRINTF((TEXT("-> PAL_FOR = %d\n"), (reg >> 15) & 3));
581 1.3 nonaka DPRINTF((TEXT("-> K3 = 0x%x, K2 = 0x%x, K1 = 0x%x\n"),
582 1.3 nonaka (reg >> 6) & 7, (reg >> 3) & 7, reg & 7));
583 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x14);
584 1.3 nonaka DPRINTF((TEXT("LCCR5: 0x%08x\n"), reg));
585 1.3 nonaka reg = VOLATILE_REF(lcdc + 0x54);
586 1.3 nonaka DPRINTF((TEXT("LCDBSCNTR: 0x%08x\n"), reg));
587 1.3 nonaka _mem->unmapPhysicalPage(lcdc);
588 1.3 nonaka #endif
589 1.1 rafal }
590