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mips_arch.cpp revision 1.3.24.3 
      1 /* -*-C++-*-	$NetBSD: mips_arch.cpp,v 1.3.24.3 2004/09/21 13:15:53 skrll Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 #undef DEBUG_KERNADDR_ACCESS
     39 #undef DEBUG_CP0_ACCESS
     40 
     41 #include <hpcboot.h>
     42 #include <mips/mips_arch.h>
     43 #include <console.h>
     44 #include <memory.h>
     45 
     46 MIPSArchitecture::MIPSArchitecture(Console *&cons, MemoryManager *&mem)
     47 	: Architecture(cons, mem)
     48 {
     49 	/* NO-OP */
     50 }
     51 
     52 MIPSArchitecture::~MIPSArchitecture(void)
     53 {
     54 	/* NO-OP */
     55 }
     56 
     57 void
     58 MIPSArchitecture::systemInfo()
     59 {
     60 	u_int32_t r0, r1;
     61 	Architecture::systemInfo();
     62 	r0 = r1 = 0;
     63 
     64 #ifdef DEBUG_CP0_ACCESS
     65 	/* CP0 access test */
     66 	_kmode = SetKMode(1);
     67 
     68 	DPRINTF((TEXT("status register test\n")));
     69 	GET_SR(r0);
     70 	DPRINTF((TEXT("current value: 0x%08x\n"), r0));
     71 	SET_SR(r1);
     72 	GET_SR(r1);
     73 	DPRINTF((TEXT("write test:    0x%08x\n"), r1));
     74 	SET_SR(r0);
     75 
     76 	SetKMode(_kmode);
     77 #endif // DEBUG_CP0_ACCESS
     78 }
     79 
     80 BOOL
     81 MIPSArchitecture::init()
     82 {
     83 	if (!_mem->init()) {
     84 		DPRINTF((TEXT("can't initialize memory manager.\n")));
     85 		return FALSE;
     86 	}
     87 
     88 	return TRUE;
     89 }
     90 
     91 BOOL
     92 MIPSArchitecture::setupLoader()
     93 {
     94 	vaddr_t v;
     95 
     96 #ifdef DEBUG_KERNADDR_ACCESS // kernel address access test
     97 #define	TEST_MAGIC		0xac1dcafe
     98 	paddr_t p;
     99 	u_int32_t r0;
    100 
    101 	_kmode = SetKMode(1);
    102 	_mem->getPage(v, p);
    103 	VOLATILE_REF(ptokv(p)) = TEST_MAGIC;
    104 	cacheFlush();
    105 	r0 = VOLATILE_REF(v);
    106 	DPRINTF((TEXT("kernel address access test: %S\n"),
    107 	    r0 == TEST_MAGIC ? "OK" : "NG"));
    108 	SetKMode(_kmode);
    109 #endif // DEBUG_KERNADDR_ACCESS
    110 
    111 	if (!_mem->getPage(v , _loader_addr)) {
    112 		DPRINTF((TEXT("can't get page for 2nd loader.\n")));
    113 		return FALSE;
    114 	}
    115 	DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"),
    116 	    (unsigned)v,(unsigned)_loader_addr));
    117 
    118 	memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize());
    119 	DPRINTF((TEXT("2nd bootloader copy done.\n")));
    120 
    121 	return TRUE;
    122 }
    123 
    124 void
    125 MIPSArchitecture::jump(paddr_t info, paddr_t pvec)
    126 {
    127 	kaddr_t sp;
    128 	vaddr_t v;
    129 	paddr_t p;
    130 
    131 	// stack for bootloader(but mips loader don't use stack)
    132 	_mem->getPage(v, p);
    133 	sp = ptokv(p + _mem->getPageSize() - 0x10);
    134 
    135 	info = ptokv(info);
    136 	pvec = ptokv(pvec);
    137 	_loader_addr = ptokv(_loader_addr);
    138 
    139 	// switch kernel mode.
    140 	SetKMode(1);
    141 	if (SetKMode(1) != 1) {
    142 		DPRINTF((TEXT("SetKMode(1) failed.\n")));
    143 		return;
    144 	}
    145 	DPRINTF((TEXT("jump to 0x%08x (info=0x%08x, pvec=0x%08x)\n"),
    146 	    _loader_addr, info, pvec));
    147 
    148 	// writeback whole D-cache and invalidate whole I-cache.
    149 	// 2nd boot-loader access data via kseg0 which were writed via kuseg,
    150 	cacheFlush();
    151 
    152 	// jump to 2nd-loader(run kseg0)
    153 	__asm(".set noreorder;"
    154 	    "jr	a3;"
    155 	    "move	sp, a2;"
    156 	    ".set reorder", info, pvec, sp, _loader_addr);
    157 	// NOTREACHED
    158 }
    159