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      1  1.4  martin /* -*-C++-*-	$NetBSD: mips_tx39.h,v 1.4 2008/04/28 20:23:20 martin Exp $	*/
      2  1.1     uch 
      3  1.1     uch /*-
      4  1.1     uch  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  1.1     uch  * All rights reserved.
      6  1.1     uch  *
      7  1.1     uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1     uch  * by UCHIYAMA Yasushi.
      9  1.1     uch  *
     10  1.1     uch  * Redistribution and use in source and binary forms, with or without
     11  1.1     uch  * modification, are permitted provided that the following conditions
     12  1.1     uch  * are met:
     13  1.1     uch  * 1. Redistributions of source code must retain the above copyright
     14  1.1     uch  *    notice, this list of conditions and the following disclaimer.
     15  1.1     uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1     uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.1     uch  *    documentation and/or other materials provided with the distribution.
     18  1.1     uch  *
     19  1.1     uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.1     uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.1     uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.1     uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.1     uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.1     uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.1     uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.1     uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.1     uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.1     uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.1     uch  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1     uch  */
     31  1.1     uch 
     32  1.1     uch #include <hpcboot.h>
     33  1.1     uch #include <mips/mips_arch.h>
     34  1.1     uch 
     35  1.1     uch class TX39XX : public MIPSArchitecture {
     36  1.1     uch private:
     37  1.2     uch 
     38  1.1     uch public:
     39  1.1     uch 	TX39XX(Console *&, MemoryManager *&, enum ArchitectureOps);
     40  1.1     uch 	~TX39XX(void);
     41  1.1     uch 
     42  1.1     uch 	virtual BOOL init(void);
     43  1.1     uch 	virtual void systemInfo(void);
     44  1.1     uch 	virtual void cacheFlush(void);
     45  1.1     uch 	static void boot_func(struct BootArgs *, struct PageTag *);
     46  1.1     uch };
     47  1.1     uch 
     48  1.2     uch #define	MIPS_TX39XX_CACHE_FLUSH()					\
     49  1.1     uch __asm(									\
     50  1.1     uch 	".set	noreorder;"						\
     51  1.1     uch 	"li	t1, 16384;"						\
     52  1.1     uch 	"li	t2, 8192;"						\
     53  1.1     uch 									\
     54  1.1     uch 	/* Disable I-cache */						\
     55  1.1     uch 	"li	t5, ~0x00000020;"					\
     56  1.1     uch 	"mfc0	t6, $3;"						\
     57  1.1     uch 	"and	t5, t5, t6;"						\
     58  1.1     uch 	"nop;"								\
     59  1.1     uch 	"mtc0	t5, $3;"						\
     60  1.1     uch 									\
     61  1.1     uch 	/* Stop streaming */						\
     62  1.1     uch 	"beq	zero, zero, 1f;"					\
     63  1.1     uch 	"nop;"								\
     64  1.1     uch "1:"									\
     65  1.1     uch 	/* Flush I-cache */						\
     66  1.1     uch 	"li	t0, 0x80000000;"					\
     67  1.1     uch 	"addu	t1, t0, t1;"						\
     68  1.1     uch 	"subu	t1, t1, 128;"						\
     69  1.1     uch "2:"									\
     70  1.1     uch 	"cache	0x0, 0($0);"						\
     71  1.1     uch 	"cache	0x0, 16(t0);"						\
     72  1.1     uch 	"cache	0x0, 32(t0);"						\
     73  1.1     uch 	"cache	0x0, 48(t0);"						\
     74  1.1     uch 	"cache	0x0, 64(t0);"						\
     75  1.1     uch 	"cache	0x0, 80(t0);"						\
     76  1.1     uch 	"cache	0x0, 96(t0);"						\
     77  1.1     uch 	"cache	0x0, 112(t0);"						\
     78  1.1     uch 	"bne	t0, t1, 2b;"						\
     79  1.1     uch 	"addu	t0, t0, 128;"						\
     80  1.1     uch 									\
     81  1.1     uch 	/* Flush D-cache */						\
     82  1.1     uch 	"li	t0, 0x80000000;"					\
     83  1.1     uch 	"addu	t1, t0, t2;"						\
     84  1.1     uch 									\
     85  1.1     uch "3:"									\
     86  1.1     uch 	"lw	t2, 0(t0);"						\
     87  1.1     uch 	"bne	t1, t0, 3b;"						\
     88  1.1     uch 	"addiu	t0, t0, 4;"						\
     89  1.1     uch 									\
     90  1.1     uch 	/* Enable I-cache */						\
     91  1.1     uch 	"nop;"								\
     92  1.1     uch 	"mtc0	t6, $3;"						\
     93  1.1     uch 	"nop;"								\
     94  1.1     uch 	".set reorder;"							\
     95  1.1     uch )
     96