7707.h revision 1.5.2.2
1 1.5.2.2 uwe /* $NetBSD: 7707.h,v 1.5.2.2 2006/03/05 04:05:40 uwe Exp $ */ 2 1.5.2.2 uwe 3 1.5.2.2 uwe /*- 4 1.5.2.2 uwe * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 1.5.2.2 uwe * All rights reserved. 6 1.5.2.2 uwe * 7 1.5.2.2 uwe * This code is derived from software contributed to The NetBSD Foundation 8 1.5.2.2 uwe * by UCHIYAMA Yasushi. 9 1.5.2.2 uwe * 10 1.5.2.2 uwe * Redistribution and use in source and binary forms, with or without 11 1.5.2.2 uwe * modification, are permitted provided that the following conditions 12 1.5.2.2 uwe * are met: 13 1.5.2.2 uwe * 1. Redistributions of source code must retain the above copyright 14 1.5.2.2 uwe * notice, this list of conditions and the following disclaimer. 15 1.5.2.2 uwe * 2. Redistributions in binary form must reproduce the above copyright 16 1.5.2.2 uwe * notice, this list of conditions and the following disclaimer in the 17 1.5.2.2 uwe * documentation and/or other materials provided with the distribution. 18 1.5.2.2 uwe * 3. All advertising materials mentioning features or use of this software 19 1.5.2.2 uwe * must display the following acknowledgement: 20 1.5.2.2 uwe * This product includes software developed by the NetBSD 21 1.5.2.2 uwe * Foundation, Inc. and its contributors. 22 1.5.2.2 uwe * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.5.2.2 uwe * contributors may be used to endorse or promote products derived 24 1.5.2.2 uwe * from this software without specific prior written permission. 25 1.5.2.2 uwe * 26 1.5.2.2 uwe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.5.2.2 uwe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.5.2.2 uwe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.5.2.2 uwe * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.5.2.2 uwe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.5.2.2 uwe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.5.2.2 uwe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.5.2.2 uwe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.5.2.2 uwe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.5.2.2 uwe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.5.2.2 uwe * POSSIBILITY OF SUCH DAMAGE. 37 1.5.2.2 uwe */ 38 1.5.2.2 uwe 39 1.5.2.2 uwe #ifndef _HPCBOOT_SH_CPU_7707_H_ 40 1.5.2.2 uwe #define _HPCBOOT_SH_CPU_7707_H_ 41 1.5.2.2 uwe 42 1.5.2.2 uwe #define SH7707_LCDAR 0xa40000c0 /* address register */ 43 1.5.2.2 uwe #define SH7707_LCDDR 0xa40000c2 /* display control register */ 44 1.5.2.2 uwe #define SH7707_LCDPR 0xa40000c6 /* palette register */ 45 1.5.2.2 uwe #define SH7707_LCDDMR 0xa40000ce /* DMA control register */ 46 1.5.2.2 uwe 47 1.5.2.2 uwe #define SH7707_LCDAR_LCDDMR0 0x0 48 1.5.2.2 uwe #define SH7707_LCDAR_LCDDMR1 0x1 49 1.5.2.2 uwe #define SH7707_LCDAR_LCDDMR2 0x2 50 1.5.2.2 uwe #define SH7707_LCDAR_LCDDMR3 0x3 51 1.5.2.2 uwe #define SH7707_LCDAR_LCDDMR4 0x4 52 1.5.2.2 uwe 53 1.5.2.2 uwe #define SH7707_CACHE_LINESZ 16 54 1.5.2.2 uwe #define SH7707_CACHE_ENTRY 128 55 1.5.2.2 uwe #define SH7707_CACHE_WAY 4 /* 2-way in RAM mode */ 56 1.5.2.2 uwe #define SH7707_CACHE_SIZE \ 57 1.5.2.2 uwe (SH7707_CACHE_LINESZ * SH7707_CACHE_ENTRY * SH7707_CACHE_WAY) 58 1.5.2.2 uwe 59 1.5.2.2 uwe #define SH7707_CACHE_ENTRY_SHIFT 4 60 1.5.2.2 uwe #define SH7707_CACHE_ENTRY_MASK 0x000007f0 61 1.5.2.2 uwe #define SH7707_CACHE_WAY_SHIFT 11 62 1.5.2.2 uwe #define SH7707_CACHE_WAY_MASK 0x00001800 63 1.5.2.2 uwe 64 1.5.2.2 uwe #define SH7707_CACHE_FLUSH() \ 65 1.5.2.2 uwe __BEGIN_MACRO \ 66 1.5.2.2 uwe uint32_t __e, __w, __wa, __a; \ 67 1.5.2.2 uwe \ 68 1.5.2.2 uwe for (__w = 0; __w < SH7707_CACHE_WAY; __w++) { \ 69 1.5.2.2 uwe __wa = SH3_CCA | __w << SH7707_CACHE_WAY_SHIFT; \ 70 1.5.2.2 uwe for (__e = 0; __e < SH7707_CACHE_ENTRY; __e++) { \ 71 1.5.2.2 uwe __a = __wa |(__e << SH7707_CACHE_ENTRY_SHIFT); \ 72 1.5.2.2 uwe _reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \ 73 1.5.2.2 uwe } \ 74 1.5.2.2 uwe } \ 75 1.5.2.2 uwe __END_MACRO 76 1.5.2.2 uwe 77 1.5.2.2 uwe #define SH7707_MMU_DISABLE SH3_MMU_DISABLE 78 1.5.2.2 uwe 79 1.5.2.2 uwe #endif // _HPCBOOT_SH_CPU_7707_H_ 80 1.5.2.2 uwe 81
Indexes created Wed Oct 01 07:09:59 GMT 2025