7707.h revision 1.6
1 1.6 martin /* $NetBSD: 7707.h,v 1.6 2008/04/28 20:23:20 martin Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.3 uch * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.1 uch * by UCHIYAMA Yasushi. 9 1.1 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 uch * notice, this list of conditions and the following disclaimer in the 17 1.1 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch #ifndef _HPCBOOT_SH_CPU_7707_H_ 33 1.2 uch #define _HPCBOOT_SH_CPU_7707_H_ 34 1.1 uch 35 1.2 uch #define SH7707_LCDAR 0xa40000c0 /* address register */ 36 1.2 uch #define SH7707_LCDDR 0xa40000c2 /* display control register */ 37 1.2 uch #define SH7707_LCDPR 0xa40000c6 /* palette register */ 38 1.2 uch #define SH7707_LCDDMR 0xa40000ce /* DMA control register */ 39 1.1 uch 40 1.2 uch #define SH7707_LCDAR_LCDDMR0 0x0 41 1.2 uch #define SH7707_LCDAR_LCDDMR1 0x1 42 1.2 uch #define SH7707_LCDAR_LCDDMR2 0x2 43 1.2 uch #define SH7707_LCDAR_LCDDMR3 0x3 44 1.2 uch #define SH7707_LCDAR_LCDDMR4 0x4 45 1.1 uch 46 1.3 uch #define SH7707_CACHE_LINESZ 16 47 1.3 uch #define SH7707_CACHE_ENTRY 128 48 1.3 uch #define SH7707_CACHE_WAY 4 /* 2-way in RAM mode */ 49 1.3 uch #define SH7707_CACHE_SIZE \ 50 1.3 uch (SH7707_CACHE_LINESZ * SH7707_CACHE_ENTRY * SH7707_CACHE_WAY) 51 1.3 uch 52 1.3 uch #define SH7707_CACHE_ENTRY_SHIFT 4 53 1.3 uch #define SH7707_CACHE_ENTRY_MASK 0x000007f0 54 1.3 uch #define SH7707_CACHE_WAY_SHIFT 11 55 1.3 uch #define SH7707_CACHE_WAY_MASK 0x00001800 56 1.3 uch 57 1.3 uch #define SH7707_CACHE_FLUSH() \ 58 1.3 uch __BEGIN_MACRO \ 59 1.5 uwe uint32_t __e, __w, __wa, __a; \ 60 1.3 uch \ 61 1.3 uch for (__w = 0; __w < SH7707_CACHE_WAY; __w++) { \ 62 1.3 uch __wa = SH3_CCA | __w << SH7707_CACHE_WAY_SHIFT; \ 63 1.3 uch for (__e = 0; __e < SH7707_CACHE_ENTRY; __e++) { \ 64 1.3 uch __a = __wa |(__e << SH7707_CACHE_ENTRY_SHIFT); \ 65 1.3 uch _reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \ 66 1.3 uch } \ 67 1.3 uch } \ 68 1.3 uch __END_MACRO 69 1.3 uch 70 1.3 uch #define SH7707_MMU_DISABLE SH3_MMU_DISABLE 71 1.3 uch 72 1.1 uch #endif // _HPCBOOT_SH_CPU_7707_H_ 73 1.3 uch 74
Indexes created Sat Sep 27 14:09:57 GMT 2025