sh.h revision 1.4
1 /* -*-C++-*- $NetBSD: sh.h,v 1.4 2006/03/05 04:05:39 uwe Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _HPCBOOT_SH_DEV_SH_H_ 40 #define _HPCBOOT_SH_DEV_SH_H_ 41 42 /* 43 * SH3, SH4 embeded devices. 44 */ 45 46 /* 47 * INTC 48 */ 49 /* SH7709/7709A */ 50 /* R/W 16bit */ 51 #define SH3_ICR0 0xfffffee0 52 #define SH3_ICR1 0xa4000010 53 #define SH3_ICR2 0xa4000012 54 #define SH3_PINTER 0xa4000014 55 #define SH3_IPRA 0xfffffee2 56 #define SH3_IPRB 0xfffffee4 57 #define SH3_IPRC 0xa4000016 58 #define SH3_IPRD 0xa4000018 59 #define SH3_IPRE 0xa400001a 60 /* R/W 8bit */ 61 #define SH3_IRR0 0xa4000004 62 /* R 8bit */ 63 #define SH3_IRR1 0xa4000006 64 #define SH3_IRR2 0xa4000008 65 66 #define SH3_ICR0_NMIL 0x8000 67 #define SH3_ICR0_NMIE 0x0100 68 69 #define SH3_ICR1_MAI 0x8000 70 #define SH3_ICR1_IRQLVL 0x4000 71 #define SH3_ICR1_BLMSK 0x2000 72 #define SH3_ICR1_IRLSEN 0x1000 73 #define SH3_ICR1_IRQ51S 0x0800 74 #define SH3_ICR1_IRQ50S 0x0400 75 #define SH3_ICR1_IRQ41S 0x0200 76 #define SH3_ICR1_IRQ40S 0x0100 77 #define SH3_ICR1_IRQ31S 0x0080 78 #define SH3_ICR1_IRQ30S 0x0040 79 #define SH3_ICR1_IRQ21S 0x0020 80 #define SH3_ICR1_IRQ20S 0x0010 81 #define SH3_ICR1_IRQ11S 0x0008 82 #define SH3_ICR1_IRQ10S 0x0004 83 #define SH3_ICR1_IRQ01S 0x0002 84 #define SH3_ICR1_IRQ00S 0x0001 85 86 #define SH3_SENSE_SELECT_MASK 0x3 87 #define SH3_SENSE_SELECT_FALLING_EDGE 0x0 88 #define SH3_SENSE_SELECT_RAISING_EDGE 0x1 89 #define SH3_SENSE_SELECT_LOW_LEVEL 0x2 90 #define SH3_SENSE_SELECT_RESERVED 0x3 91 92 #define SH3_ICR2_PINT15S 0x8000 93 #define SH3_ICR2_PINT14S 0x4000 94 #define SH3_ICR2_PINT13S 0x2000 95 #define SH3_ICR2_PINT12S 0x1000 96 #define SH3_ICR2_PINT11S 0x0800 97 #define SH3_ICR2_PINT10S 0x0400 98 #define SH3_ICR2_PINT9S 0x0200 99 #define SH3_ICR2_PINT8S 0x0100 100 #define SH3_ICR2_PINT7S 0x0080 101 #define SH3_ICR2_PINT6S 0x0040 102 #define SH3_ICR2_PINT5S 0x0020 103 #define SH3_ICR2_PINT4S 0x0010 104 #define SH3_ICR2_PINT3S 0x0008 105 #define SH3_ICR2_PINT2S 0x0004 106 #define SH3_ICR2_PINT1S 0x0002 107 #define SH3_ICR2_PINT0S 0x0001 108 109 #define SH_IPR_MASK 0xf 110 111 /* SH7750 */ 112 #define SH4_ICR 0xffd00000 113 #define SH4_ICR_NMIL 0x8000 114 #define SH4_ICR_MAI 0x4000 115 #define SH4_ICR_NMIB 0x0200 116 #define SH4_ICR_NMIE 0x0100 117 #define SH4_ICR_IRLM 0x0080 118 #define SH4_IPRA 0xffd00004 119 #define SH4_IPRB 0xffd00008 120 #define SH4_IPRC 0xffd0000c 121 /* SH7750S */ 122 #define SH4_IPRD 0xffd00010 123 124 /* 125 * Bus State Controller 126 */ 127 #define SH3_BCR1 0xffffff60 128 #define SH3_BCR2 0xffffff62 129 #define SH3_WCR1 0xffffff64 130 #define SH3_WCR2 0xffffff66 131 #define SH3_MCR 0xffffff68 132 #define SH3_DCR 0xffffff6a 133 #define SH3_PCR 0xffffff6c 134 #define SH3_RTCSR 0xffffff6e 135 #define SH3_RTCNT 0xffffff70 136 #define SH3_RTCOR 0xffffff72 137 #define SH3_RFCR 0xffffff74 138 #define SH3_BCR3 0xffffff7e 139 140 /* 141 * Pin Function Controller 142 */ 143 #define SH3_PACR 0xa4000100 144 #define SH3_PBCR 0xa4000102 145 #define SH3_PCCR 0xa4000104 146 #define SH3_PDCR 0xa4000106 147 #define SH3_PECR 0xa4000108 148 #define SH3_PFCR 0xa400010a 149 #define SH3_PGCR 0xa400010c 150 #define SH3_PHCR 0xa400010e 151 #define SH3_PJCR 0xa4000110 152 #define SH3_PKCR 0xa4000112 153 #define SH3_PLCR 0xa4000114 154 #define SH3_SCPCR 0xa4000116 155 156 /* 157 * I/O port 158 */ 159 #define SH3_PADR 0xa4000120 160 #define SH3_PBDR 0xa4000122 161 #define SH3_PCDR 0xa4000124 162 #define SH3_PDDR 0xa4000126 163 #define SH3_PEDR 0xa4000128 164 #define SH3_PFDR 0xa400012a 165 #define SH3_PGDR 0xa400012c 166 #define SH3_PHDR 0xa400012e 167 #define SH3_PJDR 0xa4000130 168 #define SH3_PKDR 0xa4000132 169 #define SH3_PLDR 0xa4000134 170 #define SH3_SCPDR 0xa4000136 171 172 /* 173 * TMU 174 */ 175 #define SH3_TOCR 0xfffffe90 176 #define SH3_TOCR_TCOE 0x01 177 #define SH3_TSTR 0xfffffe92 178 #define SH3_TSTR_STR2 0x04 179 #define SH3_TSTR_STR1 0x02 180 #define SH3_TSTR_STR0 0x01 181 #define SH3_TCOR0 0xfffffe94 182 #define SH3_TCNT0 0xfffffe98 183 #define SH3_TCR0 0xfffffe9c 184 #define SH3_TCOR1 0xfffffea0 185 #define SH3_TCNT1 0xfffffea4 186 #define SH3_TCR1 0xfffffea8 187 #define SH3_TCOR2 0xfffffeac 188 #define SH3_TCNT2 0xfffffeb0 189 #define SH3_TCR2 0xfffffeb4 190 #define SH3_TCPR2 0xfffffeb8 191 #define SH3_TCR_ICPF 0x0200 192 #define SH3_TCR_UNF 0x0100 193 #define SH3_TCR_ICPE1 0x0080 194 #define SH3_TCR_ICPE0 0x0040 195 #define SH3_TCR_UNIE 0x0020 196 #define SH3_TCR_CKEG1 0x0010 197 #define SH3_TCR_CKEG0 0x0008 198 #define SH3_TCR_TPSC2 0x0004 199 #define SH3_TCR_TPSC1 0x0002 200 #define SH3_TCR_TPSC0 0x0001 201 202 #define SH3_TCR_TPSC_P4 0x0000 203 #define SH3_TCR_TPSC_P16 0x0001 204 #define SH3_TCR_TPSC_P64 0x0002 205 #define SH3_TCR_TPSC_P256 0x0003 206 207 /* 208 * SCI 209 */ 210 #define SH4_SCSMR 0xffe00000 211 #define SH4_SCBRR 0xffe00004 212 #define SH4_SCSCR 0xffe00008 213 #define SH4_SCTDR 0xffe0000c 214 #define SH4_SCSSR 0xffe00010 215 #define SH4_SCRDR 0xffe00014 216 217 #define SH3_SCRSR /* can't access from CPU */ 218 #define SH3_SCTSR /* can't access from CPU */ 219 #define SH3_SCSMR 0xfffffe80 220 #define SH3_SCBRR 0xfffffe82 221 #define SH3_SCSCR 0xfffffe84 222 #define SH3_SCTDR 0xfffffe86 223 #define SH3_SCSSR 0xfffffe88 224 #define SH3_SCRDR 0xfffffe8a 225 #define SH3_SCPCR 0xa4000116 226 #define SH3_SCPDR 0xa4000136 227 228 #define SCSSR_TDRE 0x80 229 230 #define SH3_SCI_TX_BUSY() \ 231 while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0) 232 233 #define SH3_SCI_PUTC(c) \ 234 __BEGIN_MACRO \ 235 SH3_SCI_TX_BUSY(); \ 236 _reg_write_1(SH3_SCTDR, c); \ 237 _reg_write_1(SH3_SCSSR, \ 238 _reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \ 239 __END_MACRO 240 241 #define SH3_SCI_PRINT(s) \ 242 __BEGIN_MACRO \ 243 char *__s =(char *)(s); \ 244 int __i; \ 245 for (__i = 0; __s[__i] != '\0'; __i++) { \ 246 char __c = __s[__i]; \ 247 if (__c == '\n') \ 248 SH3_SCI_PUTC('\r'); \ 249 SH3_SCI_PUTC(__c); \ 250 } \ 251 __END_MACRO 252 253 /* 254 * SCIF 255 */ 256 #define SH4_SCSMR2 0xffe80000 257 #define SH4_SCBRR2 0xffe80004 258 #define SH4_SCSCR2 0xffe80008 259 #define SH4_SCFTDR2 0xffe8000c 260 #define SH4_SCFSR2 0xffe80010 261 #define SH4_SCFRDR2 0xffe80014 262 #define SH4_SCFCR2 0xffe80018 263 #define SH4_SCFDR2 0xffe8001c 264 #define SH4_SCSPTR2 0xffe80020 265 #define SH4_SCLSR2 0xffe80024 266 #define SH4_SCSMR2 0xffe80000 267 #define SH4_SCBRR2 0xffe80004 268 #define SH4_SCSCR2 0xffe80008 269 #define SH4_SCFTDR2 0xffe8000c 270 #define SH4_SCFSR2 0xffe80010 271 #define SH4_SCFRDR2 0xffe80014 272 #define SH4_SCFCR2 0xffe80018 273 #define SH4_SCFDR2 0xffe8001c 274 #define SH4_SCSPTR2 0xffe80020 275 #define SH4_SCLSR2 0xffe80024 276 277 #define SH4_SCSSR2 SH4_SCFSR2 278 #define SH4_SCSSR2 SH4_SCFSR2 279 280 #define SH3_SCSMR2 0xa4000150 /* R/W */ 281 #define SH3_SCBRR2 0xa4000152 /* R/W */ 282 #define SH3_SCSCR2 0xa4000154 /* R/W */ 283 #define SH3_SCFTDR2 0xa4000156 /* W */ 284 #define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */ 285 #define SH3_SCFRDR2 0xa400015a /* R */ 286 #define SH3_SCFCR2 0xa400015c /* R/W */ 287 #define SH3_SCFDR2 0xa400015e /* R */ 288 #define SH3_SCSMR2 0xa4000150 /* R/W */ 289 #define SH3_SCBRR2 0xa4000152 /* R/W */ 290 #define SH3_SCSCR2 0xa4000154 /* R/W */ 291 #define SH3_SCFTDR2 0xa4000156 /* W */ 292 #define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */ 293 #define SH3_SCFRDR2 0xa400015a /* R */ 294 #define SH3_SCFCR2 0xa400015c /* R/W */ 295 #define SH3_SCFDR2 0xa400015e /* R */ 296 297 #define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */ 298 #define SCSCR2_RIE 0x0040 /* Receive Interrupt Enable */ 299 #define SCSCR2_TE 0x0020 /* Transmit Enable */ 300 #define SCSCR2_RE 0x0010 /* Receive Enable */ 301 #define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */ 302 #define SCSCR2_CKE0 0x0001 /* ClocK Enable 0 */ 303 #define SCSCR2_CKE 0x0003 /* ClocK Enable mask */ 304 305 #define SCSSR2_ER 0x0080 /* ERror */ 306 #define SCSSR2_TEND 0x0040 /* Transmit END */ 307 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 308 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 309 #define SCSSR2_FER 0x0008 /* Framing ERror */ 310 #define SCSSR2_PER 0x0004 /* Parity ERror */ 311 #define SCSSR2_RDF 0x0002 /* Receive fifo Data Full */ 312 #define SCSSR2_DR 0x0001 /* Data Ready */ 313 314 #define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */ 315 #define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */ 316 #define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */ 317 #define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */ 318 #define SCFCR2_MCE 0x0008 /* Modem Control Enable */ 319 #define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */ 320 #define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */ 321 #define SCFCR2_LOOP 0x0001 /* LOOP back test */ 322 #define FIFO_RCV_TRIGGER_1 0x0000 323 #define FIFO_RCV_TRIGGER_4 0x0040 324 #define FIFO_RCV_TRIGGER_8 0x0080 325 #define FIFO_RCV_TRIGGER_14 0x00c0 326 #define FIFO_XMT_TRIGGER_8 0x0000 327 #define FIFO_XMT_TRIGGER_4 0x0010 328 #define FIFO_XMT_TRIGGER_2 0x0020 329 #define FIFO_XMT_TRIGGER_1 0x0030 330 331 #define SCFDR2_TXCNT 0xff00 /* Tx CouNT */ 332 #define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */ 333 #define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */ 334 #define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */ 335 336 #define SCSMR2_CHR 0x40 /* Character length */ 337 #define SCSMR2_PE 0x20 /* Parity enable */ 338 #define SCSMR2_OE 0x10 /* Parity mode */ 339 #define SCSMR2_STOP 0x08 /* Stop bit length */ 340 #define SCSMR2_CKS 0x03 /* Clock select */ 341 342 /* simple serial console macros. */ 343 #define SH3_SCIF_TX_BUSY() \ 344 while ((_reg_read_2(SH3_SCSSR2) & SCSSR2_TDFE) == 0) 345 346 #define SH3_SCIF_PUTC(c) \ 347 __BEGIN_MACRO \ 348 SH3_SCIF_TX_BUSY(); \ 349 /* wait until previous transmit done. */ \ 350 _reg_write_1(SH3_SCFTDR2, c); \ 351 /* Clear transmit FIFO empty flag */ \ 352 _reg_write_1(SH3_SCSSR2, \ 353 _reg_read_1(SH3_SCSSR2) & ~(SCSSR2_TDFE | SCSSR2_TEND)); \ 354 __END_MACRO 355 356 #define SH3_SCIF_PRINT(s) \ 357 __BEGIN_MACRO \ 358 char *__s =(char *)(s); \ 359 int __i; \ 360 for (__i = 0; __s[__i] != '\0'; __i++) { \ 361 char __c = __s[__i]; \ 362 if (__c == '\n') \ 363 SH3_SCIF_PUTC('\r'); \ 364 SH3_SCIF_PUTC(__c); \ 365 } \ 366 __END_MACRO 367 368 #define SH3_SCIF_PRINT_HEX(h) \ 369 __BEGIN_MACRO \ 370 uint32_t __h =(uint32_t)(h); \ 371 int __i; \ 372 SH3_SCIF_PUTC('0'); SH3_SCIF_PUTC('x'); \ 373 for (__i = 0; __i < 8; __i++, __h <<= 4) { \ 374 int __n =(__h >> 28) & 0xf; \ 375 char __c = __n > 9 ? 'A' + __n - 10 : '0' + __n; \ 376 SH3_SCIF_PUTC(__c); \ 377 } \ 378 SH3_SCIF_PUTC('\r'); SH3_SCIF_PUTC('\n'); \ 379 __END_MACRO 380 381 #endif /* _HPCBOOT_SH_DEV_SH_H_ */ 382
Indexes created Fri Sep 26 08:10:20 GMT 2025