sh3_dev.cpp revision 1.2.2.3
1 /* -*-C++-*- $NetBSD: sh3_dev.cpp,v 1.2.2.3 2004/09/21 13:15:54 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcboot.h> 40 #include <hpcmenu.h> 41 #include <console.h> 42 43 #include <sh3/cpu/sh3.h> 44 #include <sh3/dev/sh.h> 45 #include <sh3/dev/sh_dev.h> 46 #include <sh3/dev/hd64461.h> 47 48 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); 49 50 struct SH3dev::intr_priority SH3dev::_ipr_table[] = { 51 { "TMU0", SH3_IPRA, 12 }, 52 { "TMU1", SH3_IPRA, 8 }, 53 { "TMU2", SH3_IPRA, 4 }, 54 { "RTC", SH3_IPRA, 0 }, 55 { "WDT", SH3_IPRB, 12 }, 56 { "REF", SH3_IPRB, 8 }, 57 { "SCI", SH3_IPRB, 4 }, 58 { "reserve", SH3_IPRB, 0 }, 59 { "IRQ3", SH3_IPRC, 12 }, 60 { "IRQ2", SH3_IPRC, 8 }, 61 { "IRQ1", SH3_IPRC, 4 }, 62 { "IRQ0", SH3_IPRC, 0 }, 63 { "PINT0-7", SH3_IPRD, 12 }, 64 { "PINT8-15", SH3_IPRD, 8 }, 65 { "IRQ5", SH3_IPRD, 4 }, 66 { "IRQ4", SH3_IPRD, 0 }, 67 { "DMAC", SH3_IPRE, 12 }, 68 { "IrDA", SH3_IPRE, 8 }, 69 { "SCIF", SH3_IPRE, 4 }, 70 { "ADC", SH3_IPRE, 0 }, 71 { 0, 0, 0} /* terminator */ 72 }; 73 74 void 75 SH3dev::dump(u_int8_t bit) 76 { 77 int kmode; 78 79 super::dump(bit); 80 81 kmode = SetKMode(1); 82 83 if (bit & DUMP_DEV) { 84 // INTC 85 icu_dump(); 86 87 // BSC 88 bsc_dump(); 89 90 // TMU 91 tmu_dump(); 92 93 // PFC , I/O port 94 pfc_dump(); 95 } 96 97 if (bit & DUMP_COMPANION) { 98 // HD64461 99 platid_t platform; 100 platform.dw.dw0 = _menu->_pref.platid_hi; 101 platform.dw.dw1 = _menu->_pref.platid_lo; 102 hd64461_dump(platform); 103 } 104 105 SetKMode(kmode); 106 } 107 108 void 109 SH3dev::icu_dump() 110 { 111 112 super::icu_dump_priority(_ipr_table); 113 icu_control(); 114 DPRINTF((TEXT("ICR0 0x%08x\n"), _reg_read_2(SH3_ICR0))); 115 DPRINTF((TEXT("ICR1 0x%08x\n"), _reg_read_2(SH3_ICR1))); 116 DPRINTF((TEXT("ICR2 0x%08x\n"), _reg_read_2(SH3_ICR2))); 117 DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER))); 118 DPRINTF((TEXT("IPRA 0x%08x\n"), _reg_read_2(SH3_IPRA))); 119 DPRINTF((TEXT("IPRB 0x%08x\n"), _reg_read_2(SH3_IPRB))); 120 DPRINTF((TEXT("IPRC 0x%08x\n"), _reg_read_2(SH3_IPRC))); 121 DPRINTF((TEXT("IPRD 0x%08x\n"), _reg_read_2(SH3_IPRD))); 122 DPRINTF((TEXT("IPRE 0x%08x\n"), _reg_read_2(SH3_IPRE))); 123 DPRINTF((TEXT("IRR0 0x%08x\n"), _reg_read_1(SH3_IRR0))); 124 DPRINTF((TEXT("IRR1 0x%08x\n"), _reg_read_1(SH3_IRR1))); 125 DPRINTF((TEXT("IRR2 0x%08x\n"), _reg_read_1(SH3_IRR2))); 126 } 127 128 void 129 SH3dev::icu_control() 130 { 131 const char *sense_select[] = { 132 "falling edge", 133 "raising edge", 134 "low level", 135 "reserved", 136 }; 137 u_int16_t r; 138 139 // PINT0-15 140 DPRINTF((TEXT("PINT enable(on |) :"))); 141 bitdisp(_reg_read_2(SH3_PINTER)); 142 DPRINTF((TEXT("PINT detect(high |):"))); 143 bitdisp(_reg_read_2(SH3_ICR2)); 144 // NMI 145 r = _reg_read_2(SH3_ICR0); 146 DPRINTF((TEXT("NMI(%S %S-edge),"), 147 r & SH3_ICR0_NMIL ? "High" : "Low", 148 r & SH3_ICR0_NMIE ? "raising" : "falling")); 149 r = _reg_read_2(SH3_ICR1); 150 DPRINTF((TEXT(" %S maskable,"), r & SH3_ICR1_MAI ? "" : "never")); 151 DPRINTF((TEXT(" SR.BL %S\n"), 152 r & SH3_ICR1_BLMSK ? "ignored" : "maskable")); 153 // IRQ0-5 154 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 155 r & SH3_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 156 if (r & SH3_ICR1_IRQLVL) { 157 DPRINTF((TEXT("IRLS[0:3] %S\n"), 158 r & SH3_ICR1_IRLSEN ? "enabled" : "disabled")); 159 } 160 // sense select 161 for (int i = 5; i >= 0; i--) { 162 DPRINTF((TEXT("IRQ[%d] %S\n"), i, 163 sense_select [ 164 (r >>(i * 2)) & SH3_SENSE_SELECT_MASK])); 165 } 166 } 167 168 // 169 // Debug Functions. 170 // 171 void 172 SH3dev::bsc_dump() 173 { 174 175 DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 176 #define DUMP_BSC_REG(x) \ 177 DPRINTF((TEXT("%-8S"), #x)); \ 178 bitdisp(_reg_read_2(SH3_ ## x)) 179 DUMP_BSC_REG(BCR1); 180 DUMP_BSC_REG(BCR2); 181 DUMP_BSC_REG(WCR1); 182 DUMP_BSC_REG(WCR2); 183 DUMP_BSC_REG(MCR); 184 DUMP_BSC_REG(DCR); 185 DUMP_BSC_REG(PCR); 186 DUMP_BSC_REG(RTCSR); 187 DUMP_BSC_REG(RTCNT); 188 DUMP_BSC_REG(RTCOR); 189 DUMP_BSC_REG(RFCR); 190 DUMP_BSC_REG(BCR3); 191 #undef DUMP_BSC_REG 192 } 193 194 void 195 SH3dev::pfc_dump() 196 { 197 DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 198 DPRINTF((TEXT("[control]\n"))); 199 #define DUMP_PFC_REG(x) \ 200 DPRINTF((TEXT("P%SCR :"), #x)); \ 201 bitdisp(_reg_read_2(SH3_P##x##CR)) 202 DUMP_PFC_REG(A); 203 DUMP_PFC_REG(B); 204 DUMP_PFC_REG(C); 205 DUMP_PFC_REG(D); 206 DUMP_PFC_REG(E); 207 DUMP_PFC_REG(F); 208 DUMP_PFC_REG(G); 209 DUMP_PFC_REG(H); 210 DUMP_PFC_REG(J); 211 DUMP_PFC_REG(K); 212 DUMP_PFC_REG(L); 213 #undef DUMP_PFC_REG 214 DPRINTF((TEXT("SCPCR :"))); 215 bitdisp(_reg_read_2(SH3_SCPCR)); 216 DPRINTF((TEXT("\n[data]\n"))); 217 #define DUMP_IOPORT_REG(x) \ 218 DPRINTF((TEXT("P%SDR :"), #x)); \ 219 bitdisp(_reg_read_1(SH3_P##x##DR)) 220 DUMP_IOPORT_REG(A); 221 DUMP_IOPORT_REG(B); 222 DUMP_IOPORT_REG(C); 223 DUMP_IOPORT_REG(D); 224 DUMP_IOPORT_REG(E); 225 DUMP_IOPORT_REG(F); 226 DUMP_IOPORT_REG(G); 227 DUMP_IOPORT_REG(H); 228 DUMP_IOPORT_REG(J); 229 DUMP_IOPORT_REG(K); 230 DUMP_IOPORT_REG(L); 231 #undef DUMP_IOPORT_REG 232 DPRINTF((TEXT("SCPDR :"))); 233 bitdisp(_reg_read_1(SH3_SCPDR)); 234 } 235 236 void 237 SH3dev::tmu_dump() 238 { 239 u_int8_t r8; 240 241 DPRINTF((TEXT("<<<TMU>>>\n"))); 242 /* Common */ 243 /* TOCR timer output control register */ 244 r8 = _reg_read_1(SH3_TOCR); 245 DPRINTF((TEXT("TCLK = %S\n"), 246 r8 & SH3_TOCR_TCOE ? "RTC output" : "input")); 247 /* TSTR */ 248 r8 = _reg_read_1(SH3_TSTR); 249 DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), 250 r8 & SH3_TSTR_STR0 ? 'x' : '_', 251 r8 & SH3_TSTR_STR1 ? 'x' : '_', 252 r8 & SH3_TSTR_STR2 ? 'x' : '_')); 253 254 #define CHANNEL_DUMP(a, x) \ 255 tmu_channel_dump(x, SH##a##_TCOR##x, \ 256 SH##a##_TCNT##x, \ 257 SH##a##_TCR##x##) 258 CHANNEL_DUMP(3, 0); 259 CHANNEL_DUMP(3, 1); 260 CHANNEL_DUMP(3, 2); 261 #undef CHANNEL_DUMP 262 DPRINTF((TEXT("\n"))); 263 } 264 265 void 266 SH3dev::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, 267 paddr_t tcr) 268 { 269 u_int32_t r32; 270 u_int16_t r16; 271 272 DPRINTF((TEXT("TMU#%d:"), unit)); 273 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SH3_TCR_##m, #m) 274 /* TCR*/ 275 r16 = _reg_read_2(tcr); 276 DBG_BIT_PRINT(r16, UNF); 277 DBG_BIT_PRINT(r16, UNIE); 278 DBG_BIT_PRINT(r16, CKEG1); 279 DBG_BIT_PRINT(r16, CKEG0); 280 DBG_BIT_PRINT(r16, TPSC2); 281 DBG_BIT_PRINT(r16, TPSC1); 282 DBG_BIT_PRINT(r16, TPSC0); 283 /* channel 2 has input capture. */ 284 if (unit == 2) { 285 DBG_BIT_PRINT(r16, ICPF); 286 DBG_BIT_PRINT(r16, ICPE1); 287 DBG_BIT_PRINT(r16, ICPE0); 288 } 289 #undef DBG_BIT_PRINT 290 /* TCNT0 timer counter */ 291 r32 = _reg_read_4(tcnt); 292 DPRINTF((TEXT("\ncnt=0x%08x"), r32)); 293 /* TCOR0 timer constant register */ 294 r32 = _reg_read_4(tcor); 295 DPRINTF((TEXT(" constant=0x%04x"), r32)); 296 297 if (unit == 2) 298 DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2)); 299 else 300 DPRINTF((TEXT("\n"))); 301 } 302 303 void 304 SH3dev::hd64461_dump(platid_t &platform) 305 { 306 u_int16_t r16; 307 u_int8_t r8; 308 309 #define MATCH(p) \ 310 platid_match(&platform, &platid_mask_MACH_##p) 311 312 DPRINTF((TEXT("<<<HD64461>>>\n"))); 313 if (!MATCH(HP_LX) && 314 !MATCH(HP_JORNADA_6XX) && 315 !MATCH(HITACHI_PERSONA_HPW230JC)) { 316 DPRINTF((TEXT("don't exist."))); 317 return; 318 } 319 320 #if 0 321 DPRINTF((TEXT("frame buffer test start\n"))); 322 u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 323 324 for (int i = 0; i < 320 * 240 * 2 / 8; i++) 325 *fb++ = 0xff; 326 DPRINTF((TEXT("frame buffer test end\n"))); 327 #endif 328 // System 329 DPRINTF((TEXT("STBCR (System Control Register)\n"))); 330 r16 = _reg_read_2(HD64461_SYSSTBCR_REG16); 331 bitdisp(r16); 332 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 333 DBG_BIT_PRINT(r16, CKIO_STBY); 334 DBG_BIT_PRINT(r16, SAFECKE_IST); 335 DBG_BIT_PRINT(r16, SLCKE_IST); 336 DBG_BIT_PRINT(r16, SAFECKE_OST); 337 DBG_BIT_PRINT(r16, SLCKE_OST); 338 DBG_BIT_PRINT(r16, SMIAST); 339 DBG_BIT_PRINT(r16, SLCDST); 340 DBG_BIT_PRINT(r16, SPC0ST); 341 DBG_BIT_PRINT(r16, SPC1ST); 342 DBG_BIT_PRINT(r16, SAFEST); 343 DBG_BIT_PRINT(r16, STM0ST); 344 DBG_BIT_PRINT(r16, STM1ST); 345 DBG_BIT_PRINT(r16, SIRST); 346 DBG_BIT_PRINT(r16, SURTSD); 347 #undef DBG_BIT_PRINT 348 DPRINTF((TEXT("\n"))); 349 350 DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 351 r16 = _reg_read_2(HD64461_SYSSYSCR_REG16); 352 bitdisp(r16); 353 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 354 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 355 DBG_BIT_PRINT(r16, SPTA_IR); 356 DBG_BIT_PRINT(r16, SPTA_TM); 357 DBG_BIT_PRINT(r16, SPTB_UR); 358 DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 359 DBG_BIT_PRINT(r16, SMODE1); 360 DBG_BIT_PRINT(r16, SMODE0); 361 #undef DBG_BIT_PRINT 362 DPRINTF((TEXT("\n"))); 363 364 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 365 r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16); 366 bitdisp(r16); 367 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 368 DBG_BIT_PRINT(r16, SPDSTOF); 369 DBG_BIT_PRINT(r16, SPDSTIG); 370 DBG_BIT_PRINT(r16, SPCSTOF); 371 DBG_BIT_PRINT(r16, SPCSTIG); 372 DBG_BIT_PRINT(r16, SPBSTOF); 373 DBG_BIT_PRINT(r16, SPBSTIG); 374 DBG_BIT_PRINT(r16, SPASTOF); 375 DBG_BIT_PRINT(r16, SPASTIG); 376 DBG_BIT_PRINT(r16, SLCDSTIG); 377 DBG_BIT_PRINT(r16, SCPU_CS56_EP); 378 DBG_BIT_PRINT(r16, SCPU_CMD_EP); 379 DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 380 DBG_BIT_PRINT(r16, SCPDPU); 381 DBG_BIT_PRINT(r16, SCPU_A2319_EP); 382 #undef DBG_BIT_PRINT 383 DPRINTF((TEXT("\n"))); 384 385 DPRINTF((TEXT("\n"))); 386 387 // INTC 388 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 389 r16 = _reg_read_2(HD64461_INTCNIRR_REG16); 390 bitdisp(r16); 391 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 392 DBG_BIT_PRINT(r16, PCC0R); 393 DBG_BIT_PRINT(r16, PCC1R); 394 DBG_BIT_PRINT(r16, AFER); 395 DBG_BIT_PRINT(r16, GPIOR); 396 DBG_BIT_PRINT(r16, TMU0R); 397 DBG_BIT_PRINT(r16, TMU1R); 398 DBG_BIT_PRINT(r16, IRDAR); 399 DBG_BIT_PRINT(r16, UARTR); 400 #undef DBG_BIT_PRINT 401 DPRINTF((TEXT("\n"))); 402 403 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 404 r16 = _reg_read_2(HD64461_INTCNIMR_REG16); 405 bitdisp(r16); 406 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 407 DBG_BIT_PRINT(r16, PCC0M); 408 DBG_BIT_PRINT(r16, PCC1M); 409 DBG_BIT_PRINT(r16, AFEM); 410 DBG_BIT_PRINT(r16, GPIOM); 411 DBG_BIT_PRINT(r16, TMU0M); 412 DBG_BIT_PRINT(r16, TMU1M); 413 DBG_BIT_PRINT(r16, IRDAM); 414 DBG_BIT_PRINT(r16, UARTM); 415 #undef DBG_BIT_PRINT 416 DPRINTF((TEXT("\n"))); 417 418 DPRINTF((TEXT("\n"))); 419 420 // PCMCIA 421 // PCC0 422 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 423 DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 424 r8 = _reg_read_1(HD64461_PCC0ISR_REG8); 425 bitdisp(r8); 426 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 427 DBG_BIT_PRINT(r8, P0READY); 428 DBG_BIT_PRINT(r8, P0MWP); 429 DBG_BIT_PRINT(r8, P0VS2); 430 DBG_BIT_PRINT(r8, P0VS1); 431 DBG_BIT_PRINT(r8, P0CD2); 432 DBG_BIT_PRINT(r8, P0CD1); 433 DBG_BIT_PRINT(r8, P0BVD2); 434 DBG_BIT_PRINT(r8, P0BVD1); 435 #undef DBG_BIT_PRINT 436 DPRINTF((TEXT("\n"))); 437 438 DPRINTF((TEXT("PCC0 General Control Register\n"))); 439 r8 = _reg_read_1(HD64461_PCC0GCR_REG8); 440 bitdisp(r8); 441 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 442 DBG_BIT_PRINT(r8, P0DRVE); 443 DBG_BIT_PRINT(r8, P0PCCR); 444 DBG_BIT_PRINT(r8, P0PCCT); 445 DBG_BIT_PRINT(r8, P0VCC0); 446 DBG_BIT_PRINT(r8, P0MMOD); 447 DBG_BIT_PRINT(r8, P0PA25); 448 DBG_BIT_PRINT(r8, P0PA24); 449 DBG_BIT_PRINT(r8, P0REG); 450 #undef DBG_BIT_PRINT 451 DPRINTF((TEXT("\n"))); 452 453 DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 454 r8 = _reg_read_1(HD64461_PCC0CSCR_REG8); 455 bitdisp(r8); 456 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 457 DBG_BIT_PRINT(r8, P0SCDI); 458 DBG_BIT_PRINT(r8, P0IREQ); 459 DBG_BIT_PRINT(r8, P0SC); 460 DBG_BIT_PRINT(r8, P0CDC); 461 DBG_BIT_PRINT(r8, P0RC); 462 DBG_BIT_PRINT(r8, P0BW); 463 DBG_BIT_PRINT(r8, P0BD); 464 #undef DBG_BIT_PRINT 465 DPRINTF((TEXT("\n"))); 466 467 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 468 r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8); 469 bitdisp(r8); 470 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 471 DBG_BIT_PRINT(r8, P0CRE); 472 DBG_BIT_PRINT(r8, P0SCE); 473 DBG_BIT_PRINT(r8, P0CDE); 474 DBG_BIT_PRINT(r8, P0RE); 475 DBG_BIT_PRINT(r8, P0BWE); 476 DBG_BIT_PRINT(r8, P0BDE); 477 #undef DBG_BIT_PRINT 478 DPRINTF((TEXT("\ninterrupt type: "))); 479 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 480 case HD64461_PCC0CSCIER_P0IREQE_NONE: 481 DPRINTF((TEXT("none\n"))); 482 break; 483 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 484 DPRINTF((TEXT("level\n"))); 485 break; 486 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 487 DPRINTF((TEXT("falling edge\n"))); 488 break; 489 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 490 DPRINTF((TEXT("rising edge\n"))); 491 break; 492 } 493 494 DPRINTF((TEXT("PCC0 Software Control Register\n"))); 495 r8 = _reg_read_1(HD64461_PCC0SCR_REG8); 496 bitdisp(r8); 497 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 498 DBG_BIT_PRINT(r8, P0VCC1); 499 DBG_BIT_PRINT(r8, P0SWP); 500 #undef DBG_BIT_PRINT 501 DPRINTF((TEXT("\n"))); 502 503 // PCC1 504 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 505 DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 506 r8 = _reg_read_1(HD64461_PCC1ISR_REG8); 507 bitdisp(r8); 508 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 509 DBG_BIT_PRINT(r8, P1READY); 510 DBG_BIT_PRINT(r8, P1MWP); 511 DBG_BIT_PRINT(r8, P1VS2); 512 DBG_BIT_PRINT(r8, P1VS1); 513 DBG_BIT_PRINT(r8, P1CD2); 514 DBG_BIT_PRINT(r8, P1CD1); 515 DBG_BIT_PRINT(r8, P1BVD2); 516 DBG_BIT_PRINT(r8, P1BVD1); 517 #undef DBG_BIT_PRINT 518 DPRINTF((TEXT("\n"))); 519 520 DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 521 r8 = _reg_read_1(HD64461_PCC1GCR_REG8); 522 bitdisp(r8); 523 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 524 DBG_BIT_PRINT(r8, P1DRVE); 525 DBG_BIT_PRINT(r8, P1PCCR); 526 DBG_BIT_PRINT(r8, P1VCC0); 527 DBG_BIT_PRINT(r8, P1MMOD); 528 DBG_BIT_PRINT(r8, P1PA25); 529 DBG_BIT_PRINT(r8, P1PA24); 530 DBG_BIT_PRINT(r8, P1REG); 531 #undef DBG_BIT_PRINT 532 DPRINTF((TEXT("\n"))); 533 534 DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 535 r8 = _reg_read_1(HD64461_PCC1CSCR_REG8); 536 bitdisp(r8); 537 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 538 DBG_BIT_PRINT(r8, P1SCDI); 539 DBG_BIT_PRINT(r8, P1CDC); 540 DBG_BIT_PRINT(r8, P1RC); 541 DBG_BIT_PRINT(r8, P1BW); 542 DBG_BIT_PRINT(r8, P1BD); 543 #undef DBG_BIT_PRINT 544 DPRINTF((TEXT("\n"))); 545 546 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 547 r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8); 548 bitdisp(r8); 549 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 550 DBG_BIT_PRINT(r8, P1CRE); 551 DBG_BIT_PRINT(r8, P1CDE); 552 DBG_BIT_PRINT(r8, P1RE); 553 DBG_BIT_PRINT(r8, P1BWE); 554 DBG_BIT_PRINT(r8, P1BDE); 555 #undef DBG_BIT_PRINT 556 DPRINTF((TEXT("\n"))); 557 558 DPRINTF((TEXT("PCC1 Software Control Register\n"))); 559 r8 = _reg_read_1(HD64461_PCC1SCR_REG8); 560 bitdisp(r8); 561 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 562 DBG_BIT_PRINT(r8, P1VCC1); 563 DBG_BIT_PRINT(r8, P1SWP); 564 #undef DBG_BIT_PRINT 565 DPRINTF((TEXT("\n"))); 566 567 // General Control 568 DPRINTF((TEXT("[General Control]\n"))); 569 DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 570 r8 = _reg_read_1(HD64461_PCCP0OCR_REG8); 571 bitdisp(r8); 572 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 573 DBG_BIT_PRINT(r8, P0DEPLUP); 574 DBG_BIT_PRINT(r8, P0AEPLUP); 575 #undef DBG_BIT_PRINT 576 DPRINTF((TEXT("\n"))); 577 578 DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 579 r8 = _reg_read_1(HD64461_PCCP1OCR_REG8); 580 bitdisp(r8); 581 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 582 DBG_BIT_PRINT(r8, P1RST8MA); 583 DBG_BIT_PRINT(r8, P1RST4MA); 584 DBG_BIT_PRINT(r8, P1RAS8MA); 585 DBG_BIT_PRINT(r8, P1RAS4MA); 586 #undef DBG_BIT_PRINT 587 DPRINTF((TEXT("\n"))); 588 589 DPRINTF((TEXT("PC Card General Control Register\n"))); 590 r8 = _reg_read_1(HD64461_PCCPGCR_REG8); 591 bitdisp(r8); 592 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 593 DBG_BIT_PRINT(r8, PSSDIR); 594 DBG_BIT_PRINT(r8, PSSRDWR); 595 #undef DBG_BIT_PRINT 596 DPRINTF((TEXT("\n"))); 597 598 // GPIO 599 #define GPIO_DUMP(x) \ 600 bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16)); \ 601 bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16)); \ 602 bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16)); \ 603 bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16)) 604 605 DPRINTF((TEXT("GPIO Port Control Register\n"))); 606 GPIO_DUMP(C); 607 DPRINTF((TEXT("GPIO Port Data Register\n"))); 608 GPIO_DUMP(D); 609 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 610 GPIO_DUMP(IC); 611 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 612 GPIO_DUMP(IS); 613 } 614 615 #ifdef SH7709TEST 616 u_int32_t sh7707_fb_dma_addr; 617 u_int16_t val; 618 int s; 619 620 s = suspendIntr(); 621 VOLATILE_REF16(SH7707_LCDAR) = SH7707_LCDAR_LCDDMR0; 622 val = VOLATILE_REF16(SH7707_LCDDMR); 623 sh7707_fb_dma_addr = val; 624 VOLATILE_REF16(SH7707_LCDAR) = SH7707_LCDAR_LCDDMR1; 625 val = VOLATILE_REF16(SH7707_LCDDMR); 626 sh7707_fb_dma_addr |= (val << 16); 627 resumeIntr(s); 628 629 DPRINTF((TEXT("SH7707 frame buffer DMA address: 0x%08x\n"), 630 sh7707_fb_dma_addr)); 631 #endif 632
Indexes created Mon Sep 22 13:09:51 GMT 2025