sh_arch.cpp revision 1.1.2.2
1 1.1.2.2 bouyer /* $NetBSD: sh_arch.cpp,v 1.1.2.2 2001/02/11 19:10:12 bouyer Exp $ */ 2 1.1.2.2 bouyer 3 1.1.2.2 bouyer /*- 4 1.1.2.2 bouyer * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1.2.2 bouyer * All rights reserved. 6 1.1.2.2 bouyer * 7 1.1.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 bouyer * by UCHIYAMA Yasushi. 9 1.1.2.2 bouyer * 10 1.1.2.2 bouyer * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 bouyer * modification, are permitted provided that the following conditions 12 1.1.2.2 bouyer * are met: 13 1.1.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 bouyer * documentation and/or other materials provided with the distribution. 18 1.1.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 bouyer * must display the following acknowledgement: 20 1.1.2.2 bouyer * This product includes software developed by the NetBSD 21 1.1.2.2 bouyer * Foundation, Inc. and its contributors. 22 1.1.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 bouyer * contributors may be used to endorse or promote products derived 24 1.1.2.2 bouyer * from this software without specific prior written permission. 25 1.1.2.2 bouyer * 26 1.1.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 bouyer */ 38 1.1.2.2 bouyer 39 1.1.2.2 bouyer #include <sh3/sh_arch.h> 40 1.1.2.2 bouyer #include "scifreg.h" 41 1.1.2.2 bouyer 42 1.1.2.2 bouyer struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 43 1.1.2.2 bouyer { "TMU0", ICU_IPRA_REG16, 12 }, 44 1.1.2.2 bouyer { "TMU1", ICU_IPRA_REG16, 8 }, 45 1.1.2.2 bouyer { "TMU2", ICU_IPRA_REG16, 4 }, 46 1.1.2.2 bouyer { "RTC", ICU_IPRA_REG16, 0 }, 47 1.1.2.2 bouyer { "WDT", ICU_IPRB_REG16, 12 }, 48 1.1.2.2 bouyer { "REF", ICU_IPRB_REG16, 8 }, 49 1.1.2.2 bouyer { "SCI", ICU_IPRB_REG16, 4 }, 50 1.1.2.2 bouyer { "reserve", ICU_IPRB_REG16, 0 }, 51 1.1.2.2 bouyer { "IRQ3", ICU_IPRC_REG16, 12 }, 52 1.1.2.2 bouyer { "IRQ2", ICU_IPRC_REG16, 8 }, 53 1.1.2.2 bouyer { "IRQ1", ICU_IPRC_REG16, 4 }, 54 1.1.2.2 bouyer { "IRQ0", ICU_IPRC_REG16, 0 }, 55 1.1.2.2 bouyer { "PINT0-7", ICU_IPRD_REG16, 12 }, 56 1.1.2.2 bouyer { "PINT8-15", ICU_IPRD_REG16, 8 }, 57 1.1.2.2 bouyer { "IRQ5", ICU_IPRD_REG16, 4 }, 58 1.1.2.2 bouyer { "IRQ4", ICU_IPRD_REG16, 0 }, 59 1.1.2.2 bouyer { "DMAC", ICU_IPRE_REG16, 12 }, 60 1.1.2.2 bouyer { "IrDA", ICU_IPRE_REG16, 8 }, 61 1.1.2.2 bouyer { "SCIF", ICU_IPRE_REG16, 4 }, 62 1.1.2.2 bouyer { "ADC", ICU_IPRE_REG16, 0 }, 63 1.1.2.2 bouyer { 0, 0, 0} /* terminator */ 64 1.1.2.2 bouyer }; 65 1.1.2.2 bouyer 66 1.1.2.2 bouyer BOOL 67 1.1.2.2 bouyer SHArchitecture::init(void) 68 1.1.2.2 bouyer { 69 1.1.2.2 bouyer if (!_mem->init()) { 70 1.1.2.2 bouyer DPRINTF((TEXT("can't initialize memory manager.\n"))); 71 1.1.2.2 bouyer return FALSE; 72 1.1.2.2 bouyer } 73 1.1.2.2 bouyer // set D-RAM information 74 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 75 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 76 1.1.2.2 bouyer 77 1.1.2.2 bouyer return TRUE; 78 1.1.2.2 bouyer } 79 1.1.2.2 bouyer 80 1.1.2.2 bouyer BOOL 81 1.1.2.2 bouyer SHArchitecture::setupLoader() 82 1.1.2.2 bouyer { 83 1.1.2.2 bouyer vaddr_t v; 84 1.1.2.2 bouyer 85 1.1.2.2 bouyer if (!_mem->getPage(v , _loader_addr)) { 86 1.1.2.2 bouyer DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 87 1.1.2.2 bouyer return FALSE; 88 1.1.2.2 bouyer } 89 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 90 1.1.2.2 bouyer (unsigned)v,(unsigned)_loader_addr)); 91 1.1.2.2 bouyer 92 1.1.2.2 bouyer memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 93 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader copy done.\n"))); 94 1.1.2.2 bouyer 95 1.1.2.2 bouyer return TRUE; 96 1.1.2.2 bouyer } 97 1.1.2.2 bouyer 98 1.1.2.2 bouyer void 99 1.1.2.2 bouyer SHArchitecture::jump(paddr_t info, paddr_t pvec) 100 1.1.2.2 bouyer { 101 1.1.2.2 bouyer kaddr_t sp; 102 1.1.2.2 bouyer vaddr_t v; 103 1.1.2.2 bouyer paddr_t p; 104 1.1.2.2 bouyer 105 1.1.2.2 bouyer // stack for bootloader 106 1.1.2.2 bouyer _mem->getPage(v, p); 107 1.1.2.2 bouyer sp = ptokv(p + _mem->getPageSize() / 2); 108 1.1.2.2 bouyer 109 1.1.2.2 bouyer info = ptokv(info); 110 1.1.2.2 bouyer pvec = ptokv(pvec); 111 1.1.2.2 bouyer _loader_addr = ptokv(_loader_addr); 112 1.1.2.2 bouyer DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 113 1.1.2.2 bouyer info, sp)); 114 1.1.2.2 bouyer 115 1.1.2.2 bouyer // Change to privilege-mode. 116 1.1.2.2 bouyer SetKMode(1); 117 1.1.2.2 bouyer 118 1.1.2.2 bouyer // Disable external interrupt. 119 1.1.2.2 bouyer suspendIntr(); 120 1.1.2.2 bouyer 121 1.1.2.2 bouyer // Cache flush(for 2nd bootloader) 122 1.1.2.2 bouyer cache_flush(); 123 1.1.2.2 bouyer 124 1.1.2.2 bouyer // jump to 2nd loader.(run P1) at this time I still use MMU. 125 1.1.2.2 bouyer __asm("mov r6, r15\n" 126 1.1.2.2 bouyer "jmp @r7\n" 127 1.1.2.2 bouyer "nop\n", info, pvec, sp, _loader_addr); 128 1.1.2.2 bouyer // NOTREACHED 129 1.1.2.2 bouyer } 130 1.1.2.2 bouyer 131 1.1.2.2 bouyer // disable external interrupt and save its priority. 132 1.1.2.2 bouyer u_int32_t 133 1.1.2.2 bouyer suspendIntr(void) 134 1.1.2.2 bouyer { 135 1.1.2.2 bouyer u_int32_t sr; 136 1.1.2.2 bouyer __asm("stc sr, r0\n" 137 1.1.2.2 bouyer "mov.l r0, @r4\n" 138 1.1.2.2 bouyer "or r5, r0\n" 139 1.1.2.2 bouyer "ldc r0, sr\n", &sr, 0x000000f0); 140 1.1.2.2 bouyer return sr & 0x000000f0; 141 1.1.2.2 bouyer } 142 1.1.2.2 bouyer 143 1.1.2.2 bouyer // resume external interrupt priority. 144 1.1.2.2 bouyer void 145 1.1.2.2 bouyer resumeIntr(u_int32_t s) 146 1.1.2.2 bouyer { 147 1.1.2.2 bouyer __asm("stc sr, r0\n" 148 1.1.2.2 bouyer "and r5, r0\n" 149 1.1.2.2 bouyer "or r4, r0\n" 150 1.1.2.2 bouyer "ldc r0, sr\n", s, 0xffffff0f); 151 1.1.2.2 bouyer } 152 1.1.2.2 bouyer 153 1.1.2.2 bouyer void 154 1.1.2.2 bouyer SHArchitecture::print_stack_pointer(void) 155 1.1.2.2 bouyer { 156 1.1.2.2 bouyer int sp; 157 1.1.2.2 bouyer __asm("mov.l r15, @r4", &sp); 158 1.1.2.2 bouyer DPRINTF((TEXT("SP 0x%08x\n"), sp)); 159 1.1.2.2 bouyer } 160 1.1.2.2 bouyer 161 1.1.2.2 bouyer void 162 1.1.2.2 bouyer SHArchitecture::systemInfo() 163 1.1.2.2 bouyer { 164 1.1.2.2 bouyer u_int32_t reg; 165 1.1.2.2 bouyer 166 1.1.2.2 bouyer Architecture::systemInfo(); 167 1.1.2.2 bouyer 168 1.1.2.2 bouyer _kmode = SetKMode(1); 169 1.1.2.2 bouyer 170 1.1.2.2 bouyer // Cache 171 1.1.2.2 bouyer reg = VOLATILE_REF(CCR); 172 1.1.2.2 bouyer DPRINTF((TEXT("Cache "))); 173 1.1.2.2 bouyer if (reg & CCR_CE) 174 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 175 1.1.2.2 bouyer reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 176 1.1.2.2 bouyer reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 177 1.1.2.2 bouyer reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 178 1.1.2.2 bouyer else 179 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 180 1.1.2.2 bouyer 181 1.1.2.2 bouyer // MMU 182 1.1.2.2 bouyer reg = VOLATILE_REF(MMUCR); 183 1.1.2.2 bouyer DPRINTF((TEXT("MMU "))); 184 1.1.2.2 bouyer if (reg & MMUCR_AT) 185 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 186 1.1.2.2 bouyer reg & MMUCR_IX 187 1.1.2.2 bouyer ? TEXT("ASID + VPN") : TEXT("VPN only"), 188 1.1.2.2 bouyer reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 189 1.1.2.2 bouyer else 190 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 191 1.1.2.2 bouyer 192 1.1.2.2 bouyer // Status register 193 1.1.2.2 bouyer reg = 0; 194 1.1.2.2 bouyer __asm("stc sr, r0\n" 195 1.1.2.2 bouyer "mov.l r0, @r4", ®); 196 1.1.2.2 bouyer DPRINTF((TEXT("SR 0x%08x\n"), reg)); 197 1.1.2.2 bouyer 198 1.1.2.2 bouyer // SCIF 199 1.1.2.2 bouyer scif_dump(19200); 200 1.1.2.2 bouyer 201 1.1.2.2 bouyer // ICU 202 1.1.2.2 bouyer print_stack_pointer(); 203 1.1.2.2 bouyer icu_dump(); 204 1.1.2.2 bouyer 205 1.1.2.2 bouyer #if 0 // Frame Buffer (this test is destructive.) 206 1.1.2.2 bouyer hd64461_framebuffer_test(); 207 1.1.2.2 bouyer #endif 208 1.1.2.2 bouyer 209 1.1.2.2 bouyer SetKMode(_kmode); 210 1.1.2.2 bouyer } 211 1.1.2.2 bouyer 212 1.1.2.2 bouyer void 213 1.1.2.2 bouyer SHArchitecture::icu_dump(void) 214 1.1.2.2 bouyer { 215 1.1.2.2 bouyer print_stack_pointer(); 216 1.1.2.2 bouyer 217 1.1.2.2 bouyer DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read16(ICU_ICR0_REG16))); 218 1.1.2.2 bouyer DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read16(ICU_ICR1_REG16))); 219 1.1.2.2 bouyer DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read16(ICU_ICR2_REG16))); 220 1.1.2.2 bouyer DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read16(ICU_PINTER_REG16))); 221 1.1.2.2 bouyer DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read16(ICU_IPRA_REG16))); 222 1.1.2.2 bouyer DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read16(ICU_IPRB_REG16))); 223 1.1.2.2 bouyer DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read16(ICU_IPRC_REG16))); 224 1.1.2.2 bouyer DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read16(ICU_IPRD_REG16))); 225 1.1.2.2 bouyer DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read16(ICU_IPRE_REG16))); 226 1.1.2.2 bouyer DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read8(ICU_IRR0_REG8))); 227 1.1.2.2 bouyer DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read8(ICU_IRR1_REG8))); 228 1.1.2.2 bouyer DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read8(ICU_IRR2_REG8))); 229 1.1.2.2 bouyer icu_control(); 230 1.1.2.2 bouyer icu_priority(); 231 1.1.2.2 bouyer } 232 1.1.2.2 bouyer 233 1.1.2.2 bouyer void 234 1.1.2.2 bouyer SHArchitecture::icu_priority(void) 235 1.1.2.2 bouyer { 236 1.1.2.2 bouyer struct intr_priority *tab; 237 1.1.2.2 bouyer DPRINTF((TEXT("----interrupt priority----\n"))); 238 1.1.2.2 bouyer for (tab = ipr_table; tab->name; tab++) { 239 1.1.2.2 bouyer DPRINTF((TEXT("%-10S %d\n"), tab->name, 240 1.1.2.2 bouyer (reg_read16(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 241 1.1.2.2 bouyer } 242 1.1.2.2 bouyer DPRINTF((TEXT("--------------------------\n"))); 243 1.1.2.2 bouyer } 244 1.1.2.2 bouyer 245 1.1.2.2 bouyer void 246 1.1.2.2 bouyer SHArchitecture::icu_control(void) 247 1.1.2.2 bouyer { 248 1.1.2.2 bouyer const char *sense_select[] = { 249 1.1.2.2 bouyer "falling edge", 250 1.1.2.2 bouyer "raising edge", 251 1.1.2.2 bouyer "low level", 252 1.1.2.2 bouyer "reserved", 253 1.1.2.2 bouyer }; 254 1.1.2.2 bouyer u_int16_t r; 255 1.1.2.2 bouyer // PINT0-15 256 1.1.2.2 bouyer DPRINTF((TEXT("PINT enable(on |) :"))); 257 1.1.2.2 bouyer bitdisp(reg_read16(ICU_PINTER_REG16)); 258 1.1.2.2 bouyer DPRINTF((TEXT("PINT detect(high |):"))); 259 1.1.2.2 bouyer bitdisp(reg_read16(ICU_ICR2_REG16)); 260 1.1.2.2 bouyer // NMI 261 1.1.2.2 bouyer r = reg_read16(ICU_ICR0_REG16); 262 1.1.2.2 bouyer DPRINTF((TEXT("NMI(%S %S-edge),"), 263 1.1.2.2 bouyer r & ICU_ICR0_NMIL ? "High" : "Low", 264 1.1.2.2 bouyer r & ICU_ICR0_NMIE ? "raising" : "falling")); 265 1.1.2.2 bouyer r = reg_read16(ICU_ICR1_REG16); 266 1.1.2.2 bouyer DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 267 1.1.2.2 bouyer DPRINTF((TEXT(" SR.BL %S\n"), 268 1.1.2.2 bouyer r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 269 1.1.2.2 bouyer // IRQ0-5 270 1.1.2.2 bouyer DPRINTF((TEXT("IRQ[3:0] : %S source\n"), 271 1.1.2.2 bouyer r & ICU_ICR1_IRQLVL ? "IRL 15level" : 272 1.1.2.2 bouyer "dependent IRQ[0:3](IRL disabled)")); 273 1.1.2.2 bouyer if (r & ICU_ICR1_IRQLVL) { 274 1.1.2.2 bouyer DPRINTF((TEXT("IRLS[0:3] %S\n"), 275 1.1.2.2 bouyer r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 276 1.1.2.2 bouyer } 277 1.1.2.2 bouyer // sense select 278 1.1.2.2 bouyer for (int i = 5; i >= 0; i--) { 279 1.1.2.2 bouyer DPRINTF((TEXT("IRQ[%d] %S\n"), i, 280 1.1.2.2 bouyer sense_select [ 281 1.1.2.2 bouyer (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 282 1.1.2.2 bouyer } 283 1.1.2.2 bouyer } 284 1.1.2.2 bouyer 285 1.1.2.2 bouyer SH_BOOT_FUNC_(7709); 286 1.1.2.2 bouyer SH_BOOT_FUNC_(7709A); 287 1.1.2.2 bouyer 288 1.1.2.2 bouyer // 289 1.1.2.2 bouyer // Debug Functions. 290 1.1.2.2 bouyer // 291 1.1.2.2 bouyer void 292 1.1.2.2 bouyer SHArchitecture::scif_dump(int bps) 293 1.1.2.2 bouyer { 294 1.1.2.2 bouyer u_int16_t r16; 295 1.1.2.2 bouyer u_int8_t r8; 296 1.1.2.2 bouyer int n; 297 1.1.2.2 bouyer 298 1.1.2.2 bouyer /* mode */ 299 1.1.2.2 bouyer r8 = SHREG_SCSMR2; 300 1.1.2.2 bouyer n = 1 <<((r8 & SCSMR2_CKS) << 1); 301 1.1.2.2 bouyer DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 302 1.1.2.2 bouyer r8 & SCSMR2_CHR ? 7 : 8, 303 1.1.2.2 bouyer r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 304 1.1.2.2 bouyer r8 & SCSMR2_STOP ? 2 : 1, 305 1.1.2.2 bouyer n)); 306 1.1.2.2 bouyer /* bit rate */ 307 1.1.2.2 bouyer r8 = SHREG_SCBRR2; 308 1.1.2.2 bouyer DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 309 1.1.2.2 bouyer 32 * bps *(r8 + 1) * n)); 310 1.1.2.2 bouyer 311 1.1.2.2 bouyer /* control */ 312 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 313 1.1.2.2 bouyer DPRINTF((TEXT("SCSCR2: "))); 314 1.1.2.2 bouyer r8 = SHREG_SCSCR2; 315 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TIE); 316 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RIE); 317 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TE); 318 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RE); 319 1.1.2.2 bouyer DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 320 1.1.2.2 bouyer #undef DBG_BIT_PRINT 321 1.1.2.2 bouyer 322 1.1.2.2 bouyer /* status */ 323 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 324 1.1.2.2 bouyer r16 = SHREG_SCSSR2; 325 1.1.2.2 bouyer DPRINTF((TEXT("SCSSR2: "))); 326 1.1.2.2 bouyer DBG_BIT_PRINT(r16, ER); 327 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TEND); 328 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TDFE); 329 1.1.2.2 bouyer DBG_BIT_PRINT(r16, BRK); 330 1.1.2.2 bouyer DBG_BIT_PRINT(r16, FER); 331 1.1.2.2 bouyer DBG_BIT_PRINT(r16, PER); 332 1.1.2.2 bouyer DBG_BIT_PRINT(r16, RDF); 333 1.1.2.2 bouyer DBG_BIT_PRINT(r16, DR); 334 1.1.2.2 bouyer #undef DBG_BIT_PRINT 335 1.1.2.2 bouyer 336 1.1.2.2 bouyer /* FIFO control */ 337 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 338 1.1.2.2 bouyer r8 = SHREG_SCFCR2; 339 1.1.2.2 bouyer DPRINTF((TEXT("SCFCR2: "))); 340 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG1); 341 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG0); 342 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG1); 343 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG0); 344 1.1.2.2 bouyer DBG_BIT_PRINT(r8, MCE); 345 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TFRST); 346 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RFRST); 347 1.1.2.2 bouyer DBG_BIT_PRINT(r8, LOOP); 348 1.1.2.2 bouyer DPRINTF((TEXT("\n"))); 349 1.1.2.2 bouyer #undef DBG_BIT_PRINT 350 1.1.2.2 bouyer } 351 1.1.2.2 bouyer 352 1.1.2.2 bouyer void 353 1.1.2.2 bouyer SHArchitecture::hd64461_framebuffer_test() 354 1.1.2.2 bouyer { 355 1.1.2.2 bouyer DPRINTF((TEXT("frame buffer test start\n"))); 356 1.1.2.2 bouyer #if SH7709TEST 357 1.1.2.2 bouyer u_int32_t sh7707_fb_dma_addr; 358 1.1.2.2 bouyer u_int16_t val; 359 1.1.2.2 bouyer int s; 360 1.1.2.2 bouyer 361 1.1.2.2 bouyer s = suspendIntr(); 362 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 363 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 364 1.1.2.2 bouyer sh7707_fb_dma_addr = val; 365 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 366 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 367 1.1.2.2 bouyer sh7707_fb_dma_addr |= (val << 16); 368 1.1.2.2 bouyer resumeIntr(s); 369 1.1.2.2 bouyer 370 1.1.2.2 bouyer DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 371 1.1.2.2 bouyer sh7707_fb_dma_addr)); 372 1.1.2.2 bouyer #else 373 1.1.2.2 bouyer u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FB_ADDR); 374 1.1.2.2 bouyer 375 1.1.2.2 bouyer for (int i = 0; i < 480 * 240 * 2 / 8; i++) 376 1.1.2.2 bouyer *fb++ = 0xff; 377 1.1.2.2 bouyer #endif 378 1.1.2.2 bouyer DPRINTF((TEXT("frame buffer test end\n"))); 379 1.1.2.2 bouyer } 380
Indexes created Tue Sep 23 07:09:52 GMT 2025