sh_arch.cpp revision 1.1.2.3
1 1.1.2.3 bouyer /* $NetBSD: sh_arch.cpp,v 1.1.2.3 2001/03/12 13:28:17 bouyer Exp $ */ 2 1.1.2.2 bouyer 3 1.1.2.2 bouyer /*- 4 1.1.2.2 bouyer * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1.2.2 bouyer * All rights reserved. 6 1.1.2.2 bouyer * 7 1.1.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 bouyer * by UCHIYAMA Yasushi. 9 1.1.2.2 bouyer * 10 1.1.2.2 bouyer * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 bouyer * modification, are permitted provided that the following conditions 12 1.1.2.2 bouyer * are met: 13 1.1.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 bouyer * documentation and/or other materials provided with the distribution. 18 1.1.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 bouyer * must display the following acknowledgement: 20 1.1.2.2 bouyer * This product includes software developed by the NetBSD 21 1.1.2.2 bouyer * Foundation, Inc. and its contributors. 22 1.1.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 bouyer * contributors may be used to endorse or promote products derived 24 1.1.2.2 bouyer * from this software without specific prior written permission. 25 1.1.2.2 bouyer * 26 1.1.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 bouyer */ 38 1.1.2.2 bouyer 39 1.1.2.3 bouyer #include <hpcmenu.h> 40 1.1.2.2 bouyer #include <sh3/sh_arch.h> 41 1.1.2.3 bouyer #include <sh3/hd64461.h> 42 1.1.2.2 bouyer #include "scifreg.h" 43 1.1.2.2 bouyer 44 1.1.2.2 bouyer struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 45 1.1.2.2 bouyer { "TMU0", ICU_IPRA_REG16, 12 }, 46 1.1.2.2 bouyer { "TMU1", ICU_IPRA_REG16, 8 }, 47 1.1.2.2 bouyer { "TMU2", ICU_IPRA_REG16, 4 }, 48 1.1.2.2 bouyer { "RTC", ICU_IPRA_REG16, 0 }, 49 1.1.2.2 bouyer { "WDT", ICU_IPRB_REG16, 12 }, 50 1.1.2.2 bouyer { "REF", ICU_IPRB_REG16, 8 }, 51 1.1.2.2 bouyer { "SCI", ICU_IPRB_REG16, 4 }, 52 1.1.2.2 bouyer { "reserve", ICU_IPRB_REG16, 0 }, 53 1.1.2.2 bouyer { "IRQ3", ICU_IPRC_REG16, 12 }, 54 1.1.2.2 bouyer { "IRQ2", ICU_IPRC_REG16, 8 }, 55 1.1.2.2 bouyer { "IRQ1", ICU_IPRC_REG16, 4 }, 56 1.1.2.2 bouyer { "IRQ0", ICU_IPRC_REG16, 0 }, 57 1.1.2.2 bouyer { "PINT0-7", ICU_IPRD_REG16, 12 }, 58 1.1.2.2 bouyer { "PINT8-15", ICU_IPRD_REG16, 8 }, 59 1.1.2.2 bouyer { "IRQ5", ICU_IPRD_REG16, 4 }, 60 1.1.2.2 bouyer { "IRQ4", ICU_IPRD_REG16, 0 }, 61 1.1.2.2 bouyer { "DMAC", ICU_IPRE_REG16, 12 }, 62 1.1.2.2 bouyer { "IrDA", ICU_IPRE_REG16, 8 }, 63 1.1.2.2 bouyer { "SCIF", ICU_IPRE_REG16, 4 }, 64 1.1.2.2 bouyer { "ADC", ICU_IPRE_REG16, 0 }, 65 1.1.2.2 bouyer { 0, 0, 0} /* terminator */ 66 1.1.2.2 bouyer }; 67 1.1.2.2 bouyer 68 1.1.2.2 bouyer BOOL 69 1.1.2.2 bouyer SHArchitecture::init(void) 70 1.1.2.2 bouyer { 71 1.1.2.2 bouyer if (!_mem->init()) { 72 1.1.2.2 bouyer DPRINTF((TEXT("can't initialize memory manager.\n"))); 73 1.1.2.2 bouyer return FALSE; 74 1.1.2.2 bouyer } 75 1.1.2.2 bouyer // set D-RAM information 76 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 77 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 78 1.1.2.2 bouyer 79 1.1.2.2 bouyer return TRUE; 80 1.1.2.2 bouyer } 81 1.1.2.2 bouyer 82 1.1.2.2 bouyer BOOL 83 1.1.2.2 bouyer SHArchitecture::setupLoader() 84 1.1.2.2 bouyer { 85 1.1.2.2 bouyer vaddr_t v; 86 1.1.2.2 bouyer 87 1.1.2.2 bouyer if (!_mem->getPage(v , _loader_addr)) { 88 1.1.2.2 bouyer DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 89 1.1.2.2 bouyer return FALSE; 90 1.1.2.2 bouyer } 91 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 92 1.1.2.2 bouyer (unsigned)v,(unsigned)_loader_addr)); 93 1.1.2.2 bouyer 94 1.1.2.2 bouyer memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 95 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader copy done.\n"))); 96 1.1.2.2 bouyer 97 1.1.2.2 bouyer return TRUE; 98 1.1.2.2 bouyer } 99 1.1.2.2 bouyer 100 1.1.2.2 bouyer void 101 1.1.2.2 bouyer SHArchitecture::jump(paddr_t info, paddr_t pvec) 102 1.1.2.2 bouyer { 103 1.1.2.2 bouyer kaddr_t sp; 104 1.1.2.2 bouyer vaddr_t v; 105 1.1.2.2 bouyer paddr_t p; 106 1.1.2.2 bouyer 107 1.1.2.2 bouyer // stack for bootloader 108 1.1.2.2 bouyer _mem->getPage(v, p); 109 1.1.2.2 bouyer sp = ptokv(p + _mem->getPageSize() / 2); 110 1.1.2.2 bouyer 111 1.1.2.2 bouyer info = ptokv(info); 112 1.1.2.2 bouyer pvec = ptokv(pvec); 113 1.1.2.2 bouyer _loader_addr = ptokv(_loader_addr); 114 1.1.2.2 bouyer DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 115 1.1.2.2 bouyer info, sp)); 116 1.1.2.2 bouyer 117 1.1.2.2 bouyer // Change to privilege-mode. 118 1.1.2.2 bouyer SetKMode(1); 119 1.1.2.2 bouyer 120 1.1.2.2 bouyer // Disable external interrupt. 121 1.1.2.2 bouyer suspendIntr(); 122 1.1.2.2 bouyer 123 1.1.2.2 bouyer // Cache flush(for 2nd bootloader) 124 1.1.2.2 bouyer cache_flush(); 125 1.1.2.2 bouyer 126 1.1.2.2 bouyer // jump to 2nd loader.(run P1) at this time I still use MMU. 127 1.1.2.2 bouyer __asm("mov r6, r15\n" 128 1.1.2.2 bouyer "jmp @r7\n" 129 1.1.2.2 bouyer "nop\n", info, pvec, sp, _loader_addr); 130 1.1.2.2 bouyer // NOTREACHED 131 1.1.2.2 bouyer } 132 1.1.2.2 bouyer 133 1.1.2.2 bouyer // disable external interrupt and save its priority. 134 1.1.2.2 bouyer u_int32_t 135 1.1.2.2 bouyer suspendIntr(void) 136 1.1.2.2 bouyer { 137 1.1.2.2 bouyer u_int32_t sr; 138 1.1.2.2 bouyer __asm("stc sr, r0\n" 139 1.1.2.2 bouyer "mov.l r0, @r4\n" 140 1.1.2.2 bouyer "or r5, r0\n" 141 1.1.2.2 bouyer "ldc r0, sr\n", &sr, 0x000000f0); 142 1.1.2.2 bouyer return sr & 0x000000f0; 143 1.1.2.2 bouyer } 144 1.1.2.2 bouyer 145 1.1.2.2 bouyer // resume external interrupt priority. 146 1.1.2.2 bouyer void 147 1.1.2.2 bouyer resumeIntr(u_int32_t s) 148 1.1.2.2 bouyer { 149 1.1.2.2 bouyer __asm("stc sr, r0\n" 150 1.1.2.2 bouyer "and r5, r0\n" 151 1.1.2.2 bouyer "or r4, r0\n" 152 1.1.2.2 bouyer "ldc r0, sr\n", s, 0xffffff0f); 153 1.1.2.2 bouyer } 154 1.1.2.2 bouyer 155 1.1.2.2 bouyer void 156 1.1.2.2 bouyer SHArchitecture::print_stack_pointer(void) 157 1.1.2.2 bouyer { 158 1.1.2.2 bouyer int sp; 159 1.1.2.2 bouyer __asm("mov.l r15, @r4", &sp); 160 1.1.2.2 bouyer DPRINTF((TEXT("SP 0x%08x\n"), sp)); 161 1.1.2.2 bouyer } 162 1.1.2.2 bouyer 163 1.1.2.2 bouyer void 164 1.1.2.2 bouyer SHArchitecture::systemInfo() 165 1.1.2.2 bouyer { 166 1.1.2.2 bouyer u_int32_t reg; 167 1.1.2.3 bouyer HpcMenuInterface &menu = HpcMenuInterface::Instance(); 168 1.1.2.2 bouyer 169 1.1.2.2 bouyer Architecture::systemInfo(); 170 1.1.2.2 bouyer 171 1.1.2.3 bouyer // check debug level. 172 1.1.2.3 bouyer if (menu._cons_parameter == 0) 173 1.1.2.3 bouyer return; 174 1.1.2.3 bouyer 175 1.1.2.2 bouyer _kmode = SetKMode(1); 176 1.1.2.2 bouyer 177 1.1.2.2 bouyer // Cache 178 1.1.2.2 bouyer reg = VOLATILE_REF(CCR); 179 1.1.2.2 bouyer DPRINTF((TEXT("Cache "))); 180 1.1.2.2 bouyer if (reg & CCR_CE) 181 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 182 1.1.2.2 bouyer reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 183 1.1.2.2 bouyer reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 184 1.1.2.2 bouyer reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 185 1.1.2.2 bouyer else 186 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 187 1.1.2.2 bouyer 188 1.1.2.2 bouyer // MMU 189 1.1.2.2 bouyer reg = VOLATILE_REF(MMUCR); 190 1.1.2.2 bouyer DPRINTF((TEXT("MMU "))); 191 1.1.2.2 bouyer if (reg & MMUCR_AT) 192 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 193 1.1.2.2 bouyer reg & MMUCR_IX 194 1.1.2.2 bouyer ? TEXT("ASID + VPN") : TEXT("VPN only"), 195 1.1.2.2 bouyer reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 196 1.1.2.2 bouyer else 197 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 198 1.1.2.2 bouyer 199 1.1.2.2 bouyer // Status register 200 1.1.2.2 bouyer reg = 0; 201 1.1.2.2 bouyer __asm("stc sr, r0\n" 202 1.1.2.2 bouyer "mov.l r0, @r4", ®); 203 1.1.2.2 bouyer DPRINTF((TEXT("SR 0x%08x\n"), reg)); 204 1.1.2.2 bouyer 205 1.1.2.3 bouyer // BSC 206 1.1.2.3 bouyer bsc_dump(); 207 1.1.2.3 bouyer 208 1.1.2.2 bouyer // ICU 209 1.1.2.2 bouyer print_stack_pointer(); 210 1.1.2.2 bouyer icu_dump(); 211 1.1.2.2 bouyer 212 1.1.2.3 bouyer // PFC , I/O port 213 1.1.2.3 bouyer pfc_dump(); 214 1.1.2.3 bouyer 215 1.1.2.3 bouyer // SCIF 216 1.1.2.3 bouyer scif_dump(19200); 217 1.1.2.3 bouyer 218 1.1.2.3 bouyer // HD64461 219 1.1.2.3 bouyer platid_t platform; 220 1.1.2.3 bouyer platform.dw.dw0 = menu._pref.platid_hi; 221 1.1.2.3 bouyer platform.dw.dw1 = menu._pref.platid_lo; 222 1.1.2.3 bouyer hd64461_dump(platform); 223 1.1.2.2 bouyer 224 1.1.2.2 bouyer SetKMode(_kmode); 225 1.1.2.2 bouyer } 226 1.1.2.2 bouyer 227 1.1.2.2 bouyer void 228 1.1.2.2 bouyer SHArchitecture::icu_dump(void) 229 1.1.2.2 bouyer { 230 1.1.2.3 bouyer DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 231 1.1.2.2 bouyer print_stack_pointer(); 232 1.1.2.2 bouyer 233 1.1.2.3 bouyer DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 234 1.1.2.3 bouyer DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 235 1.1.2.3 bouyer DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 236 1.1.2.3 bouyer DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 237 1.1.2.3 bouyer DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 238 1.1.2.3 bouyer DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 239 1.1.2.3 bouyer DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 240 1.1.2.3 bouyer DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 241 1.1.2.3 bouyer DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 242 1.1.2.3 bouyer DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 243 1.1.2.3 bouyer DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 244 1.1.2.3 bouyer DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 245 1.1.2.2 bouyer icu_control(); 246 1.1.2.2 bouyer icu_priority(); 247 1.1.2.2 bouyer } 248 1.1.2.2 bouyer 249 1.1.2.2 bouyer void 250 1.1.2.2 bouyer SHArchitecture::icu_priority(void) 251 1.1.2.2 bouyer { 252 1.1.2.2 bouyer struct intr_priority *tab; 253 1.1.2.2 bouyer DPRINTF((TEXT("----interrupt priority----\n"))); 254 1.1.2.2 bouyer for (tab = ipr_table; tab->name; tab++) { 255 1.1.2.2 bouyer DPRINTF((TEXT("%-10S %d\n"), tab->name, 256 1.1.2.3 bouyer (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 257 1.1.2.2 bouyer } 258 1.1.2.2 bouyer DPRINTF((TEXT("--------------------------\n"))); 259 1.1.2.2 bouyer } 260 1.1.2.2 bouyer 261 1.1.2.2 bouyer void 262 1.1.2.2 bouyer SHArchitecture::icu_control(void) 263 1.1.2.2 bouyer { 264 1.1.2.2 bouyer const char *sense_select[] = { 265 1.1.2.2 bouyer "falling edge", 266 1.1.2.2 bouyer "raising edge", 267 1.1.2.2 bouyer "low level", 268 1.1.2.2 bouyer "reserved", 269 1.1.2.2 bouyer }; 270 1.1.2.2 bouyer u_int16_t r; 271 1.1.2.3 bouyer 272 1.1.2.2 bouyer // PINT0-15 273 1.1.2.2 bouyer DPRINTF((TEXT("PINT enable(on |) :"))); 274 1.1.2.3 bouyer bitdisp(reg_read_2(ICU_PINTER_REG16)); 275 1.1.2.2 bouyer DPRINTF((TEXT("PINT detect(high |):"))); 276 1.1.2.3 bouyer bitdisp(reg_read_2(ICU_ICR2_REG16)); 277 1.1.2.2 bouyer // NMI 278 1.1.2.3 bouyer r = reg_read_2(ICU_ICR0_REG16); 279 1.1.2.2 bouyer DPRINTF((TEXT("NMI(%S %S-edge),"), 280 1.1.2.2 bouyer r & ICU_ICR0_NMIL ? "High" : "Low", 281 1.1.2.2 bouyer r & ICU_ICR0_NMIE ? "raising" : "falling")); 282 1.1.2.3 bouyer r = reg_read_2(ICU_ICR1_REG16); 283 1.1.2.2 bouyer DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 284 1.1.2.2 bouyer DPRINTF((TEXT(" SR.BL %S\n"), 285 1.1.2.2 bouyer r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 286 1.1.2.2 bouyer // IRQ0-5 287 1.1.2.3 bouyer DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 288 1.1.2.3 bouyer r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 289 1.1.2.2 bouyer if (r & ICU_ICR1_IRQLVL) { 290 1.1.2.2 bouyer DPRINTF((TEXT("IRLS[0:3] %S\n"), 291 1.1.2.2 bouyer r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 292 1.1.2.2 bouyer } 293 1.1.2.2 bouyer // sense select 294 1.1.2.2 bouyer for (int i = 5; i >= 0; i--) { 295 1.1.2.2 bouyer DPRINTF((TEXT("IRQ[%d] %S\n"), i, 296 1.1.2.2 bouyer sense_select [ 297 1.1.2.2 bouyer (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 298 1.1.2.2 bouyer } 299 1.1.2.2 bouyer } 300 1.1.2.2 bouyer 301 1.1.2.2 bouyer SH_BOOT_FUNC_(7709); 302 1.1.2.2 bouyer SH_BOOT_FUNC_(7709A); 303 1.1.2.2 bouyer 304 1.1.2.2 bouyer // 305 1.1.2.2 bouyer // Debug Functions. 306 1.1.2.2 bouyer // 307 1.1.2.2 bouyer void 308 1.1.2.3 bouyer SHArchitecture::bsc_dump() 309 1.1.2.3 bouyer { 310 1.1.2.3 bouyer DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 311 1.1.2.3 bouyer #define DUMP_BSC_REG(x) \ 312 1.1.2.3 bouyer DPRINTF((TEXT("%-8S"), #x)); \ 313 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 314 1.1.2.3 bouyer DUMP_BSC_REG(BCR1); 315 1.1.2.3 bouyer DUMP_BSC_REG(BCR2); 316 1.1.2.3 bouyer DUMP_BSC_REG(WCR1); 317 1.1.2.3 bouyer DUMP_BSC_REG(WCR2); 318 1.1.2.3 bouyer DUMP_BSC_REG(MCR); 319 1.1.2.3 bouyer DUMP_BSC_REG(DCR); 320 1.1.2.3 bouyer DUMP_BSC_REG(PCR); 321 1.1.2.3 bouyer DUMP_BSC_REG(RTCSR); 322 1.1.2.3 bouyer DUMP_BSC_REG(RTCNT); 323 1.1.2.3 bouyer DUMP_BSC_REG(RTCOR); 324 1.1.2.3 bouyer DUMP_BSC_REG(RFCR); 325 1.1.2.3 bouyer DUMP_BSC_REG(BCR3); 326 1.1.2.3 bouyer #undef DUMP_BSC_REG 327 1.1.2.3 bouyer } 328 1.1.2.3 bouyer 329 1.1.2.3 bouyer void 330 1.1.2.2 bouyer SHArchitecture::scif_dump(int bps) 331 1.1.2.2 bouyer { 332 1.1.2.2 bouyer u_int16_t r16; 333 1.1.2.2 bouyer u_int8_t r8; 334 1.1.2.2 bouyer int n; 335 1.1.2.2 bouyer 336 1.1.2.3 bouyer DPRINTF((TEXT("<<<SCIF>>>\n"))); 337 1.1.2.2 bouyer /* mode */ 338 1.1.2.2 bouyer r8 = SHREG_SCSMR2; 339 1.1.2.2 bouyer n = 1 <<((r8 & SCSMR2_CKS) << 1); 340 1.1.2.2 bouyer DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 341 1.1.2.2 bouyer r8 & SCSMR2_CHR ? 7 : 8, 342 1.1.2.2 bouyer r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 343 1.1.2.2 bouyer r8 & SCSMR2_STOP ? 2 : 1, 344 1.1.2.2 bouyer n)); 345 1.1.2.2 bouyer /* bit rate */ 346 1.1.2.2 bouyer r8 = SHREG_SCBRR2; 347 1.1.2.2 bouyer DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 348 1.1.2.2 bouyer 32 * bps *(r8 + 1) * n)); 349 1.1.2.2 bouyer 350 1.1.2.2 bouyer /* control */ 351 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 352 1.1.2.2 bouyer DPRINTF((TEXT("SCSCR2: "))); 353 1.1.2.2 bouyer r8 = SHREG_SCSCR2; 354 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TIE); 355 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RIE); 356 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TE); 357 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RE); 358 1.1.2.2 bouyer DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 359 1.1.2.2 bouyer #undef DBG_BIT_PRINT 360 1.1.2.2 bouyer 361 1.1.2.2 bouyer /* status */ 362 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 363 1.1.2.2 bouyer r16 = SHREG_SCSSR2; 364 1.1.2.2 bouyer DPRINTF((TEXT("SCSSR2: "))); 365 1.1.2.2 bouyer DBG_BIT_PRINT(r16, ER); 366 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TEND); 367 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TDFE); 368 1.1.2.2 bouyer DBG_BIT_PRINT(r16, BRK); 369 1.1.2.2 bouyer DBG_BIT_PRINT(r16, FER); 370 1.1.2.2 bouyer DBG_BIT_PRINT(r16, PER); 371 1.1.2.2 bouyer DBG_BIT_PRINT(r16, RDF); 372 1.1.2.2 bouyer DBG_BIT_PRINT(r16, DR); 373 1.1.2.2 bouyer #undef DBG_BIT_PRINT 374 1.1.2.2 bouyer 375 1.1.2.2 bouyer /* FIFO control */ 376 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 377 1.1.2.2 bouyer r8 = SHREG_SCFCR2; 378 1.1.2.2 bouyer DPRINTF((TEXT("SCFCR2: "))); 379 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG1); 380 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG0); 381 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG1); 382 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG0); 383 1.1.2.2 bouyer DBG_BIT_PRINT(r8, MCE); 384 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TFRST); 385 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RFRST); 386 1.1.2.2 bouyer DBG_BIT_PRINT(r8, LOOP); 387 1.1.2.2 bouyer DPRINTF((TEXT("\n"))); 388 1.1.2.2 bouyer #undef DBG_BIT_PRINT 389 1.1.2.2 bouyer } 390 1.1.2.2 bouyer 391 1.1.2.2 bouyer void 392 1.1.2.3 bouyer SHArchitecture::pfc_dump() 393 1.1.2.3 bouyer { 394 1.1.2.3 bouyer DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 395 1.1.2.3 bouyer DPRINTF((TEXT("[control]\n"))); 396 1.1.2.3 bouyer #define DUMP_PFC_REG(x) \ 397 1.1.2.3 bouyer DPRINTF((TEXT("P%SCR :"), #x)); \ 398 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 399 1.1.2.3 bouyer DUMP_PFC_REG(A); 400 1.1.2.3 bouyer DUMP_PFC_REG(B); 401 1.1.2.3 bouyer DUMP_PFC_REG(C); 402 1.1.2.3 bouyer DUMP_PFC_REG(D); 403 1.1.2.3 bouyer DUMP_PFC_REG(E); 404 1.1.2.3 bouyer DUMP_PFC_REG(F); 405 1.1.2.3 bouyer DUMP_PFC_REG(G); 406 1.1.2.3 bouyer DUMP_PFC_REG(H); 407 1.1.2.3 bouyer DUMP_PFC_REG(J); 408 1.1.2.3 bouyer DUMP_PFC_REG(K); 409 1.1.2.3 bouyer DUMP_PFC_REG(L); 410 1.1.2.3 bouyer #undef DUMP_PFC_REG 411 1.1.2.3 bouyer DPRINTF((TEXT("SCPCR :"))); 412 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_SCPCR_REG16)); 413 1.1.2.3 bouyer DPRINTF((TEXT("\n[data]\n"))); 414 1.1.2.3 bouyer #define DUMP_IOPORT_REG(x) \ 415 1.1.2.3 bouyer DPRINTF((TEXT("P%SDR :"), #x)); \ 416 1.1.2.3 bouyer bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 417 1.1.2.3 bouyer DUMP_IOPORT_REG(A); 418 1.1.2.3 bouyer DUMP_IOPORT_REG(B); 419 1.1.2.3 bouyer DUMP_IOPORT_REG(C); 420 1.1.2.3 bouyer DUMP_IOPORT_REG(D); 421 1.1.2.3 bouyer DUMP_IOPORT_REG(E); 422 1.1.2.3 bouyer DUMP_IOPORT_REG(F); 423 1.1.2.3 bouyer DUMP_IOPORT_REG(G); 424 1.1.2.3 bouyer DUMP_IOPORT_REG(H); 425 1.1.2.3 bouyer DUMP_IOPORT_REG(J); 426 1.1.2.3 bouyer DUMP_IOPORT_REG(K); 427 1.1.2.3 bouyer DUMP_IOPORT_REG(L); 428 1.1.2.3 bouyer #undef DUMP_IOPORT_REG 429 1.1.2.3 bouyer DPRINTF((TEXT("SCPDR :"))); 430 1.1.2.3 bouyer bitdisp(reg_read_1(SH3_SCPDR_REG8)); 431 1.1.2.3 bouyer } 432 1.1.2.3 bouyer 433 1.1.2.3 bouyer void 434 1.1.2.3 bouyer SHArchitecture::hd64461_dump(platid_t &platform) 435 1.1.2.2 bouyer { 436 1.1.2.3 bouyer u_int16_t r16; 437 1.1.2.3 bouyer u_int8_t r8; 438 1.1.2.3 bouyer 439 1.1.2.3 bouyer #define MATCH(p) \ 440 1.1.2.3 bouyer platid_match(&platform, &platid_mask_MACH_##p) 441 1.1.2.3 bouyer 442 1.1.2.3 bouyer DPRINTF((TEXT("<<<HD64461>>>\n"))); 443 1.1.2.3 bouyer if (!MATCH(HP_LX) && 444 1.1.2.3 bouyer !MATCH(HP_JORNADA_6XX) && 445 1.1.2.3 bouyer !MATCH(HITACHI_PERSONA_HPW230JC)) { 446 1.1.2.3 bouyer DPRINTF((TEXT("don't exist."))); 447 1.1.2.3 bouyer return; 448 1.1.2.3 bouyer } 449 1.1.2.3 bouyer 450 1.1.2.3 bouyer #if 0 451 1.1.2.2 bouyer DPRINTF((TEXT("frame buffer test start\n"))); 452 1.1.2.3 bouyer u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 453 1.1.2.3 bouyer 454 1.1.2.3 bouyer for (int i = 0; i < 320 * 240 * 2 / 8; i++) 455 1.1.2.3 bouyer *fb++ = 0xff; 456 1.1.2.3 bouyer DPRINTF((TEXT("frame buffer test end\n"))); 457 1.1.2.3 bouyer #endif 458 1.1.2.3 bouyer // System 459 1.1.2.3 bouyer DPRINTF((TEXT("STBCR (System Control Register)\n"))); 460 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 461 1.1.2.3 bouyer bitdisp(r16); 462 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 463 1.1.2.3 bouyer DBG_BIT_PRINT(r16, CKIO_STBY); 464 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFECKE_IST); 465 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCKE_IST); 466 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFECKE_OST); 467 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCKE_OST); 468 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMIAST); 469 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCDST); 470 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPC0ST); 471 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPC1ST); 472 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFEST); 473 1.1.2.3 bouyer DBG_BIT_PRINT(r16, STM0ST); 474 1.1.2.3 bouyer DBG_BIT_PRINT(r16, STM1ST); 475 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SIRST); 476 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SURTSD); 477 1.1.2.3 bouyer #undef DBG_BIT_PRINT 478 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 479 1.1.2.3 bouyer 480 1.1.2.3 bouyer DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 481 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 482 1.1.2.3 bouyer bitdisp(r16); 483 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 484 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 485 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTA_IR); 486 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTA_TM); 487 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTB_UR); 488 1.1.2.3 bouyer DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 489 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMODE1); 490 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMODE0); 491 1.1.2.3 bouyer #undef DBG_BIT_PRINT 492 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 493 1.1.2.3 bouyer 494 1.1.2.3 bouyer DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 495 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 496 1.1.2.3 bouyer bitdisp(r16); 497 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 498 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPDSTOF); 499 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPDSTIG); 500 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPCSTOF); 501 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPCSTIG); 502 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPBSTOF); 503 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPBSTIG); 504 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPASTOF); 505 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPASTIG); 506 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCDSTIG); 507 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_CS56_EP); 508 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_CMD_EP); 509 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 510 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPDPU); 511 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_A2319_EP); 512 1.1.2.3 bouyer #undef DBG_BIT_PRINT 513 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 514 1.1.2.3 bouyer 515 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 516 1.1.2.3 bouyer 517 1.1.2.3 bouyer // INTC 518 1.1.2.3 bouyer DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 519 1.1.2.3 bouyer r16 = reg_read_2(HD64461_INTCNIRR_REG16); 520 1.1.2.3 bouyer bitdisp(r16); 521 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 522 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC0R); 523 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC1R); 524 1.1.2.3 bouyer DBG_BIT_PRINT(r16, AFER); 525 1.1.2.3 bouyer DBG_BIT_PRINT(r16, GPIOR); 526 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU0R); 527 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU1R); 528 1.1.2.3 bouyer DBG_BIT_PRINT(r16, IRDAR); 529 1.1.2.3 bouyer DBG_BIT_PRINT(r16, UARTR); 530 1.1.2.3 bouyer #undef DBG_BIT_PRINT 531 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 532 1.1.2.3 bouyer 533 1.1.2.3 bouyer DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 534 1.1.2.3 bouyer r16 = reg_read_2(HD64461_INTCNIMR_REG16); 535 1.1.2.3 bouyer bitdisp(r16); 536 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 537 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC0M); 538 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC1M); 539 1.1.2.3 bouyer DBG_BIT_PRINT(r16, AFEM); 540 1.1.2.3 bouyer DBG_BIT_PRINT(r16, GPIOM); 541 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU0M); 542 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU1M); 543 1.1.2.3 bouyer DBG_BIT_PRINT(r16, IRDAM); 544 1.1.2.3 bouyer DBG_BIT_PRINT(r16, UARTM); 545 1.1.2.3 bouyer #undef DBG_BIT_PRINT 546 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 547 1.1.2.3 bouyer 548 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 549 1.1.2.3 bouyer 550 1.1.2.3 bouyer // PCMCIA 551 1.1.2.3 bouyer // PCC0 552 1.1.2.3 bouyer DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 553 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 554 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0ISR_REG8); 555 1.1.2.3 bouyer bitdisp(r8); 556 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 557 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0READY); 558 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0MWP); 559 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VS2); 560 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VS1); 561 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CD2); 562 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CD1); 563 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BVD2); 564 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BVD1); 565 1.1.2.3 bouyer #undef DBG_BIT_PRINT 566 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 567 1.1.2.3 bouyer 568 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 General Control Register\n"))); 569 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0GCR_REG8); 570 1.1.2.3 bouyer bitdisp(r8); 571 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 572 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0DRVE); 573 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PCCR); 574 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PCCT); 575 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VCC0); 576 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0MMOD); 577 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PA25); 578 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PA24); 579 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0REG); 580 1.1.2.3 bouyer #undef DBG_BIT_PRINT 581 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 582 1.1.2.3 bouyer 583 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 584 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 585 1.1.2.3 bouyer bitdisp(r8); 586 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 587 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SCDI); 588 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0IREQ); 589 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SC); 590 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CDC); 591 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0RC); 592 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BW); 593 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BD); 594 1.1.2.3 bouyer #undef DBG_BIT_PRINT 595 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 596 1.1.2.3 bouyer 597 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 598 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 599 1.1.2.3 bouyer bitdisp(r8); 600 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 601 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CRE); 602 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SCE); 603 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CDE); 604 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0RE); 605 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BWE); 606 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BDE); 607 1.1.2.3 bouyer #undef DBG_BIT_PRINT 608 1.1.2.3 bouyer DPRINTF((TEXT("\ninterrupt type: "))); 609 1.1.2.3 bouyer switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 610 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_NONE: 611 1.1.2.3 bouyer DPRINTF((TEXT("none\n"))); 612 1.1.2.3 bouyer break; 613 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 614 1.1.2.3 bouyer DPRINTF((TEXT("level\n"))); 615 1.1.2.3 bouyer break; 616 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 617 1.1.2.3 bouyer DPRINTF((TEXT("falling edge\n"))); 618 1.1.2.3 bouyer break; 619 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_REDGE: 620 1.1.2.3 bouyer DPRINTF((TEXT("rising edge\n"))); 621 1.1.2.3 bouyer break; 622 1.1.2.3 bouyer } 623 1.1.2.3 bouyer 624 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Software Control Register\n"))); 625 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0SCR_REG8); 626 1.1.2.3 bouyer bitdisp(r8); 627 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 628 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VCC1); 629 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SWP); 630 1.1.2.3 bouyer #undef DBG_BIT_PRINT 631 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 632 1.1.2.3 bouyer 633 1.1.2.3 bouyer // PCC1 634 1.1.2.3 bouyer DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 635 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 636 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1ISR_REG8); 637 1.1.2.3 bouyer bitdisp(r8); 638 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 639 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1READY); 640 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1MWP); 641 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VS2); 642 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VS1); 643 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CD2); 644 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CD1); 645 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BVD2); 646 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BVD1); 647 1.1.2.3 bouyer #undef DBG_BIT_PRINT 648 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 649 1.1.2.3 bouyer 650 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 651 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1GCR_REG8); 652 1.1.2.3 bouyer bitdisp(r8); 653 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 654 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1DRVE); 655 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PCCR); 656 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VCC0); 657 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1MMOD); 658 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PA25); 659 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PA24); 660 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1REG); 661 1.1.2.3 bouyer #undef DBG_BIT_PRINT 662 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 663 1.1.2.3 bouyer 664 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 665 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 666 1.1.2.3 bouyer bitdisp(r8); 667 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 668 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1SCDI); 669 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CDC); 670 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RC); 671 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BW); 672 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BD); 673 1.1.2.3 bouyer #undef DBG_BIT_PRINT 674 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 675 1.1.2.3 bouyer 676 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 677 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 678 1.1.2.3 bouyer bitdisp(r8); 679 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 680 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CRE); 681 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CDE); 682 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RE); 683 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BWE); 684 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BDE); 685 1.1.2.3 bouyer #undef DBG_BIT_PRINT 686 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 687 1.1.2.3 bouyer 688 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Software Control Register\n"))); 689 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1SCR_REG8); 690 1.1.2.3 bouyer bitdisp(r8); 691 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 692 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VCC1); 693 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1SWP); 694 1.1.2.3 bouyer #undef DBG_BIT_PRINT 695 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 696 1.1.2.3 bouyer 697 1.1.2.3 bouyer // General Control 698 1.1.2.3 bouyer DPRINTF((TEXT("[General Control]\n"))); 699 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 700 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 701 1.1.2.3 bouyer bitdisp(r8); 702 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 703 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0DEPLUP); 704 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0AEPLUP); 705 1.1.2.3 bouyer #undef DBG_BIT_PRINT 706 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 707 1.1.2.3 bouyer 708 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 709 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 710 1.1.2.3 bouyer bitdisp(r8); 711 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 712 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RST8MA); 713 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RST4MA); 714 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RAS8MA); 715 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RAS4MA); 716 1.1.2.3 bouyer #undef DBG_BIT_PRINT 717 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 718 1.1.2.3 bouyer 719 1.1.2.3 bouyer DPRINTF((TEXT("PC Card General Control Register\n"))); 720 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCPGCR_REG8); 721 1.1.2.3 bouyer bitdisp(r8); 722 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 723 1.1.2.3 bouyer DBG_BIT_PRINT(r8, PSSDIR); 724 1.1.2.3 bouyer DBG_BIT_PRINT(r8, PSSRDWR); 725 1.1.2.3 bouyer #undef DBG_BIT_PRINT 726 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 727 1.1.2.3 bouyer 728 1.1.2.3 bouyer // GPIO 729 1.1.2.3 bouyer #define GPIO_DUMP_REG8(x) \ 730 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 731 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 732 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 733 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 734 1.1.2.3 bouyer #define GPIO_DUMP_REG16(x) \ 735 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 736 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 737 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 738 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 739 1.1.2.3 bouyer 740 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Control Register\n"))); 741 1.1.2.3 bouyer GPIO_DUMP_REG16(C); 742 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Data Register\n"))); 743 1.1.2.3 bouyer GPIO_DUMP_REG8(D); 744 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 745 1.1.2.3 bouyer GPIO_DUMP_REG8(IC); 746 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 747 1.1.2.3 bouyer GPIO_DUMP_REG8(IS); 748 1.1.2.3 bouyer } 749 1.1.2.3 bouyer 750 1.1.2.3 bouyer #ifdef SH7709TEST 751 1.1.2.2 bouyer u_int32_t sh7707_fb_dma_addr; 752 1.1.2.2 bouyer u_int16_t val; 753 1.1.2.2 bouyer int s; 754 1.1.2.2 bouyer 755 1.1.2.2 bouyer s = suspendIntr(); 756 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 757 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 758 1.1.2.2 bouyer sh7707_fb_dma_addr = val; 759 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 760 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 761 1.1.2.2 bouyer sh7707_fb_dma_addr |= (val << 16); 762 1.1.2.2 bouyer resumeIntr(s); 763 1.1.2.2 bouyer 764 1.1.2.2 bouyer DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 765 1.1.2.2 bouyer sh7707_fb_dma_addr)); 766 1.1.2.2 bouyer #endif 767
Indexes created Wed Sep 24 05:09:52 GMT 2025