sh_arch.cpp revision 1.1.2.4
1 1.1.2.4 bouyer /* $NetBSD: sh_arch.cpp,v 1.1.2.4 2001/03/27 15:30:49 bouyer Exp $ */ 2 1.1.2.2 bouyer 3 1.1.2.2 bouyer /*- 4 1.1.2.2 bouyer * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1.2.2 bouyer * All rights reserved. 6 1.1.2.2 bouyer * 7 1.1.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 bouyer * by UCHIYAMA Yasushi. 9 1.1.2.2 bouyer * 10 1.1.2.2 bouyer * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 bouyer * modification, are permitted provided that the following conditions 12 1.1.2.2 bouyer * are met: 13 1.1.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 bouyer * documentation and/or other materials provided with the distribution. 18 1.1.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 bouyer * must display the following acknowledgement: 20 1.1.2.2 bouyer * This product includes software developed by the NetBSD 21 1.1.2.2 bouyer * Foundation, Inc. and its contributors. 22 1.1.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 bouyer * contributors may be used to endorse or promote products derived 24 1.1.2.2 bouyer * from this software without specific prior written permission. 25 1.1.2.2 bouyer * 26 1.1.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 bouyer */ 38 1.1.2.2 bouyer 39 1.1.2.3 bouyer #include <hpcmenu.h> 40 1.1.2.2 bouyer #include <sh3/sh_arch.h> 41 1.1.2.3 bouyer #include <sh3/hd64461.h> 42 1.1.2.2 bouyer #include "scifreg.h" 43 1.1.2.2 bouyer 44 1.1.2.4 bouyer static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); 45 1.1.2.4 bouyer 46 1.1.2.2 bouyer struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 47 1.1.2.2 bouyer { "TMU0", ICU_IPRA_REG16, 12 }, 48 1.1.2.2 bouyer { "TMU1", ICU_IPRA_REG16, 8 }, 49 1.1.2.2 bouyer { "TMU2", ICU_IPRA_REG16, 4 }, 50 1.1.2.2 bouyer { "RTC", ICU_IPRA_REG16, 0 }, 51 1.1.2.2 bouyer { "WDT", ICU_IPRB_REG16, 12 }, 52 1.1.2.2 bouyer { "REF", ICU_IPRB_REG16, 8 }, 53 1.1.2.2 bouyer { "SCI", ICU_IPRB_REG16, 4 }, 54 1.1.2.2 bouyer { "reserve", ICU_IPRB_REG16, 0 }, 55 1.1.2.2 bouyer { "IRQ3", ICU_IPRC_REG16, 12 }, 56 1.1.2.2 bouyer { "IRQ2", ICU_IPRC_REG16, 8 }, 57 1.1.2.2 bouyer { "IRQ1", ICU_IPRC_REG16, 4 }, 58 1.1.2.2 bouyer { "IRQ0", ICU_IPRC_REG16, 0 }, 59 1.1.2.2 bouyer { "PINT0-7", ICU_IPRD_REG16, 12 }, 60 1.1.2.2 bouyer { "PINT8-15", ICU_IPRD_REG16, 8 }, 61 1.1.2.2 bouyer { "IRQ5", ICU_IPRD_REG16, 4 }, 62 1.1.2.2 bouyer { "IRQ4", ICU_IPRD_REG16, 0 }, 63 1.1.2.2 bouyer { "DMAC", ICU_IPRE_REG16, 12 }, 64 1.1.2.2 bouyer { "IrDA", ICU_IPRE_REG16, 8 }, 65 1.1.2.2 bouyer { "SCIF", ICU_IPRE_REG16, 4 }, 66 1.1.2.2 bouyer { "ADC", ICU_IPRE_REG16, 0 }, 67 1.1.2.2 bouyer { 0, 0, 0} /* terminator */ 68 1.1.2.2 bouyer }; 69 1.1.2.2 bouyer 70 1.1.2.2 bouyer BOOL 71 1.1.2.2 bouyer SHArchitecture::init(void) 72 1.1.2.2 bouyer { 73 1.1.2.2 bouyer if (!_mem->init()) { 74 1.1.2.2 bouyer DPRINTF((TEXT("can't initialize memory manager.\n"))); 75 1.1.2.2 bouyer return FALSE; 76 1.1.2.2 bouyer } 77 1.1.2.2 bouyer // set D-RAM information 78 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 79 1.1.2.2 bouyer _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 80 1.1.2.2 bouyer 81 1.1.2.2 bouyer return TRUE; 82 1.1.2.2 bouyer } 83 1.1.2.2 bouyer 84 1.1.2.2 bouyer BOOL 85 1.1.2.2 bouyer SHArchitecture::setupLoader() 86 1.1.2.2 bouyer { 87 1.1.2.2 bouyer vaddr_t v; 88 1.1.2.2 bouyer 89 1.1.2.2 bouyer if (!_mem->getPage(v , _loader_addr)) { 90 1.1.2.2 bouyer DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 91 1.1.2.2 bouyer return FALSE; 92 1.1.2.2 bouyer } 93 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 94 1.1.2.2 bouyer (unsigned)v,(unsigned)_loader_addr)); 95 1.1.2.2 bouyer 96 1.1.2.2 bouyer memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 97 1.1.2.2 bouyer DPRINTF((TEXT("2nd bootloader copy done.\n"))); 98 1.1.2.2 bouyer 99 1.1.2.2 bouyer return TRUE; 100 1.1.2.2 bouyer } 101 1.1.2.2 bouyer 102 1.1.2.2 bouyer void 103 1.1.2.2 bouyer SHArchitecture::jump(paddr_t info, paddr_t pvec) 104 1.1.2.2 bouyer { 105 1.1.2.2 bouyer kaddr_t sp; 106 1.1.2.2 bouyer vaddr_t v; 107 1.1.2.2 bouyer paddr_t p; 108 1.1.2.2 bouyer 109 1.1.2.2 bouyer // stack for bootloader 110 1.1.2.2 bouyer _mem->getPage(v, p); 111 1.1.2.2 bouyer sp = ptokv(p + _mem->getPageSize() / 2); 112 1.1.2.2 bouyer 113 1.1.2.2 bouyer info = ptokv(info); 114 1.1.2.2 bouyer pvec = ptokv(pvec); 115 1.1.2.2 bouyer _loader_addr = ptokv(_loader_addr); 116 1.1.2.2 bouyer DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 117 1.1.2.2 bouyer info, sp)); 118 1.1.2.2 bouyer 119 1.1.2.2 bouyer // Change to privilege-mode. 120 1.1.2.2 bouyer SetKMode(1); 121 1.1.2.2 bouyer 122 1.1.2.2 bouyer // Disable external interrupt. 123 1.1.2.2 bouyer suspendIntr(); 124 1.1.2.2 bouyer 125 1.1.2.2 bouyer // Cache flush(for 2nd bootloader) 126 1.1.2.2 bouyer cache_flush(); 127 1.1.2.2 bouyer 128 1.1.2.2 bouyer // jump to 2nd loader.(run P1) at this time I still use MMU. 129 1.1.2.2 bouyer __asm("mov r6, r15\n" 130 1.1.2.2 bouyer "jmp @r7\n" 131 1.1.2.2 bouyer "nop\n", info, pvec, sp, _loader_addr); 132 1.1.2.2 bouyer // NOTREACHED 133 1.1.2.2 bouyer } 134 1.1.2.2 bouyer 135 1.1.2.2 bouyer // disable external interrupt and save its priority. 136 1.1.2.2 bouyer u_int32_t 137 1.1.2.2 bouyer suspendIntr(void) 138 1.1.2.2 bouyer { 139 1.1.2.2 bouyer u_int32_t sr; 140 1.1.2.2 bouyer __asm("stc sr, r0\n" 141 1.1.2.2 bouyer "mov.l r0, @r4\n" 142 1.1.2.2 bouyer "or r5, r0\n" 143 1.1.2.2 bouyer "ldc r0, sr\n", &sr, 0x000000f0); 144 1.1.2.2 bouyer return sr & 0x000000f0; 145 1.1.2.2 bouyer } 146 1.1.2.2 bouyer 147 1.1.2.2 bouyer // resume external interrupt priority. 148 1.1.2.2 bouyer void 149 1.1.2.2 bouyer resumeIntr(u_int32_t s) 150 1.1.2.2 bouyer { 151 1.1.2.2 bouyer __asm("stc sr, r0\n" 152 1.1.2.2 bouyer "and r5, r0\n" 153 1.1.2.2 bouyer "or r4, r0\n" 154 1.1.2.2 bouyer "ldc r0, sr\n", s, 0xffffff0f); 155 1.1.2.2 bouyer } 156 1.1.2.2 bouyer 157 1.1.2.2 bouyer void 158 1.1.2.2 bouyer SHArchitecture::print_stack_pointer(void) 159 1.1.2.2 bouyer { 160 1.1.2.2 bouyer int sp; 161 1.1.2.2 bouyer __asm("mov.l r15, @r4", &sp); 162 1.1.2.2 bouyer DPRINTF((TEXT("SP 0x%08x\n"), sp)); 163 1.1.2.2 bouyer } 164 1.1.2.2 bouyer 165 1.1.2.2 bouyer void 166 1.1.2.2 bouyer SHArchitecture::systemInfo() 167 1.1.2.2 bouyer { 168 1.1.2.2 bouyer u_int32_t reg; 169 1.1.2.3 bouyer HpcMenuInterface &menu = HpcMenuInterface::Instance(); 170 1.1.2.2 bouyer 171 1.1.2.2 bouyer Architecture::systemInfo(); 172 1.1.2.2 bouyer 173 1.1.2.3 bouyer // check debug level. 174 1.1.2.3 bouyer if (menu._cons_parameter == 0) 175 1.1.2.3 bouyer return; 176 1.1.2.3 bouyer 177 1.1.2.2 bouyer _kmode = SetKMode(1); 178 1.1.2.2 bouyer 179 1.1.2.2 bouyer // Cache 180 1.1.2.2 bouyer reg = VOLATILE_REF(CCR); 181 1.1.2.2 bouyer DPRINTF((TEXT("Cache "))); 182 1.1.2.2 bouyer if (reg & CCR_CE) 183 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 184 1.1.2.2 bouyer reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 185 1.1.2.2 bouyer reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 186 1.1.2.2 bouyer reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 187 1.1.2.2 bouyer else 188 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 189 1.1.2.2 bouyer 190 1.1.2.2 bouyer // MMU 191 1.1.2.2 bouyer reg = VOLATILE_REF(MMUCR); 192 1.1.2.2 bouyer DPRINTF((TEXT("MMU "))); 193 1.1.2.2 bouyer if (reg & MMUCR_AT) 194 1.1.2.2 bouyer DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 195 1.1.2.2 bouyer reg & MMUCR_IX 196 1.1.2.2 bouyer ? TEXT("ASID + VPN") : TEXT("VPN only"), 197 1.1.2.2 bouyer reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 198 1.1.2.2 bouyer else 199 1.1.2.2 bouyer DPRINTF((TEXT("Disabled.\n"))); 200 1.1.2.2 bouyer 201 1.1.2.2 bouyer // Status register 202 1.1.2.2 bouyer reg = 0; 203 1.1.2.2 bouyer __asm("stc sr, r0\n" 204 1.1.2.2 bouyer "mov.l r0, @r4", ®); 205 1.1.2.2 bouyer DPRINTF((TEXT("SR 0x%08x\n"), reg)); 206 1.1.2.2 bouyer 207 1.1.2.3 bouyer // BSC 208 1.1.2.3 bouyer bsc_dump(); 209 1.1.2.3 bouyer 210 1.1.2.2 bouyer // ICU 211 1.1.2.2 bouyer print_stack_pointer(); 212 1.1.2.2 bouyer icu_dump(); 213 1.1.2.2 bouyer 214 1.1.2.4 bouyer // TMU 215 1.1.2.4 bouyer tmu_dump(); 216 1.1.2.4 bouyer 217 1.1.2.3 bouyer // PFC , I/O port 218 1.1.2.3 bouyer pfc_dump(); 219 1.1.2.3 bouyer 220 1.1.2.3 bouyer // SCIF 221 1.1.2.4 bouyer scif_dump(menu._pref.serial_speed); 222 1.1.2.3 bouyer 223 1.1.2.3 bouyer // HD64461 224 1.1.2.3 bouyer platid_t platform; 225 1.1.2.3 bouyer platform.dw.dw0 = menu._pref.platid_hi; 226 1.1.2.3 bouyer platform.dw.dw1 = menu._pref.platid_lo; 227 1.1.2.3 bouyer hd64461_dump(platform); 228 1.1.2.2 bouyer 229 1.1.2.2 bouyer SetKMode(_kmode); 230 1.1.2.2 bouyer } 231 1.1.2.2 bouyer 232 1.1.2.2 bouyer void 233 1.1.2.2 bouyer SHArchitecture::icu_dump(void) 234 1.1.2.2 bouyer { 235 1.1.2.3 bouyer DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 236 1.1.2.2 bouyer print_stack_pointer(); 237 1.1.2.2 bouyer 238 1.1.2.3 bouyer DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 239 1.1.2.3 bouyer DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 240 1.1.2.3 bouyer DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 241 1.1.2.3 bouyer DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 242 1.1.2.3 bouyer DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 243 1.1.2.3 bouyer DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 244 1.1.2.3 bouyer DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 245 1.1.2.3 bouyer DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 246 1.1.2.3 bouyer DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 247 1.1.2.3 bouyer DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 248 1.1.2.3 bouyer DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 249 1.1.2.3 bouyer DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 250 1.1.2.2 bouyer icu_control(); 251 1.1.2.2 bouyer icu_priority(); 252 1.1.2.2 bouyer } 253 1.1.2.2 bouyer 254 1.1.2.2 bouyer void 255 1.1.2.2 bouyer SHArchitecture::icu_priority(void) 256 1.1.2.2 bouyer { 257 1.1.2.2 bouyer struct intr_priority *tab; 258 1.1.2.2 bouyer DPRINTF((TEXT("----interrupt priority----\n"))); 259 1.1.2.2 bouyer for (tab = ipr_table; tab->name; tab++) { 260 1.1.2.2 bouyer DPRINTF((TEXT("%-10S %d\n"), tab->name, 261 1.1.2.3 bouyer (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 262 1.1.2.2 bouyer } 263 1.1.2.2 bouyer DPRINTF((TEXT("--------------------------\n"))); 264 1.1.2.2 bouyer } 265 1.1.2.2 bouyer 266 1.1.2.2 bouyer void 267 1.1.2.2 bouyer SHArchitecture::icu_control(void) 268 1.1.2.2 bouyer { 269 1.1.2.2 bouyer const char *sense_select[] = { 270 1.1.2.2 bouyer "falling edge", 271 1.1.2.2 bouyer "raising edge", 272 1.1.2.2 bouyer "low level", 273 1.1.2.2 bouyer "reserved", 274 1.1.2.2 bouyer }; 275 1.1.2.2 bouyer u_int16_t r; 276 1.1.2.3 bouyer 277 1.1.2.2 bouyer // PINT0-15 278 1.1.2.2 bouyer DPRINTF((TEXT("PINT enable(on |) :"))); 279 1.1.2.3 bouyer bitdisp(reg_read_2(ICU_PINTER_REG16)); 280 1.1.2.2 bouyer DPRINTF((TEXT("PINT detect(high |):"))); 281 1.1.2.3 bouyer bitdisp(reg_read_2(ICU_ICR2_REG16)); 282 1.1.2.2 bouyer // NMI 283 1.1.2.3 bouyer r = reg_read_2(ICU_ICR0_REG16); 284 1.1.2.2 bouyer DPRINTF((TEXT("NMI(%S %S-edge),"), 285 1.1.2.2 bouyer r & ICU_ICR0_NMIL ? "High" : "Low", 286 1.1.2.2 bouyer r & ICU_ICR0_NMIE ? "raising" : "falling")); 287 1.1.2.3 bouyer r = reg_read_2(ICU_ICR1_REG16); 288 1.1.2.2 bouyer DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 289 1.1.2.2 bouyer DPRINTF((TEXT(" SR.BL %S\n"), 290 1.1.2.2 bouyer r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 291 1.1.2.2 bouyer // IRQ0-5 292 1.1.2.3 bouyer DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 293 1.1.2.3 bouyer r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 294 1.1.2.2 bouyer if (r & ICU_ICR1_IRQLVL) { 295 1.1.2.2 bouyer DPRINTF((TEXT("IRLS[0:3] %S\n"), 296 1.1.2.2 bouyer r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 297 1.1.2.2 bouyer } 298 1.1.2.2 bouyer // sense select 299 1.1.2.2 bouyer for (int i = 5; i >= 0; i--) { 300 1.1.2.2 bouyer DPRINTF((TEXT("IRQ[%d] %S\n"), i, 301 1.1.2.2 bouyer sense_select [ 302 1.1.2.2 bouyer (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 303 1.1.2.2 bouyer } 304 1.1.2.2 bouyer } 305 1.1.2.2 bouyer 306 1.1.2.2 bouyer SH_BOOT_FUNC_(7709); 307 1.1.2.2 bouyer SH_BOOT_FUNC_(7709A); 308 1.1.2.2 bouyer 309 1.1.2.2 bouyer // 310 1.1.2.2 bouyer // Debug Functions. 311 1.1.2.2 bouyer // 312 1.1.2.2 bouyer void 313 1.1.2.3 bouyer SHArchitecture::bsc_dump() 314 1.1.2.3 bouyer { 315 1.1.2.3 bouyer DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 316 1.1.2.3 bouyer #define DUMP_BSC_REG(x) \ 317 1.1.2.3 bouyer DPRINTF((TEXT("%-8S"), #x)); \ 318 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 319 1.1.2.3 bouyer DUMP_BSC_REG(BCR1); 320 1.1.2.3 bouyer DUMP_BSC_REG(BCR2); 321 1.1.2.3 bouyer DUMP_BSC_REG(WCR1); 322 1.1.2.3 bouyer DUMP_BSC_REG(WCR2); 323 1.1.2.3 bouyer DUMP_BSC_REG(MCR); 324 1.1.2.3 bouyer DUMP_BSC_REG(DCR); 325 1.1.2.3 bouyer DUMP_BSC_REG(PCR); 326 1.1.2.3 bouyer DUMP_BSC_REG(RTCSR); 327 1.1.2.3 bouyer DUMP_BSC_REG(RTCNT); 328 1.1.2.3 bouyer DUMP_BSC_REG(RTCOR); 329 1.1.2.3 bouyer DUMP_BSC_REG(RFCR); 330 1.1.2.3 bouyer DUMP_BSC_REG(BCR3); 331 1.1.2.3 bouyer #undef DUMP_BSC_REG 332 1.1.2.3 bouyer } 333 1.1.2.3 bouyer 334 1.1.2.3 bouyer void 335 1.1.2.2 bouyer SHArchitecture::scif_dump(int bps) 336 1.1.2.2 bouyer { 337 1.1.2.2 bouyer u_int16_t r16; 338 1.1.2.2 bouyer u_int8_t r8; 339 1.1.2.2 bouyer int n; 340 1.1.2.2 bouyer 341 1.1.2.3 bouyer DPRINTF((TEXT("<<<SCIF>>>\n"))); 342 1.1.2.2 bouyer /* mode */ 343 1.1.2.2 bouyer r8 = SHREG_SCSMR2; 344 1.1.2.2 bouyer n = 1 <<((r8 & SCSMR2_CKS) << 1); 345 1.1.2.2 bouyer DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 346 1.1.2.2 bouyer r8 & SCSMR2_CHR ? 7 : 8, 347 1.1.2.2 bouyer r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 348 1.1.2.2 bouyer r8 & SCSMR2_STOP ? 2 : 1, 349 1.1.2.2 bouyer n)); 350 1.1.2.2 bouyer /* bit rate */ 351 1.1.2.2 bouyer r8 = SHREG_SCBRR2; 352 1.1.2.2 bouyer DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 353 1.1.2.2 bouyer 32 * bps *(r8 + 1) * n)); 354 1.1.2.2 bouyer 355 1.1.2.2 bouyer /* control */ 356 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 357 1.1.2.2 bouyer DPRINTF((TEXT("SCSCR2: "))); 358 1.1.2.2 bouyer r8 = SHREG_SCSCR2; 359 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TIE); 360 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RIE); 361 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TE); 362 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RE); 363 1.1.2.2 bouyer DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 364 1.1.2.2 bouyer #undef DBG_BIT_PRINT 365 1.1.2.2 bouyer 366 1.1.2.2 bouyer /* status */ 367 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 368 1.1.2.2 bouyer r16 = SHREG_SCSSR2; 369 1.1.2.2 bouyer DPRINTF((TEXT("SCSSR2: "))); 370 1.1.2.2 bouyer DBG_BIT_PRINT(r16, ER); 371 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TEND); 372 1.1.2.2 bouyer DBG_BIT_PRINT(r16, TDFE); 373 1.1.2.2 bouyer DBG_BIT_PRINT(r16, BRK); 374 1.1.2.2 bouyer DBG_BIT_PRINT(r16, FER); 375 1.1.2.2 bouyer DBG_BIT_PRINT(r16, PER); 376 1.1.2.2 bouyer DBG_BIT_PRINT(r16, RDF); 377 1.1.2.2 bouyer DBG_BIT_PRINT(r16, DR); 378 1.1.2.2 bouyer #undef DBG_BIT_PRINT 379 1.1.2.2 bouyer 380 1.1.2.2 bouyer /* FIFO control */ 381 1.1.2.2 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 382 1.1.2.2 bouyer r8 = SHREG_SCFCR2; 383 1.1.2.2 bouyer DPRINTF((TEXT("SCFCR2: "))); 384 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG1); 385 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RTRG0); 386 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG1); 387 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TTRG0); 388 1.1.2.2 bouyer DBG_BIT_PRINT(r8, MCE); 389 1.1.2.2 bouyer DBG_BIT_PRINT(r8, TFRST); 390 1.1.2.2 bouyer DBG_BIT_PRINT(r8, RFRST); 391 1.1.2.2 bouyer DBG_BIT_PRINT(r8, LOOP); 392 1.1.2.2 bouyer DPRINTF((TEXT("\n"))); 393 1.1.2.2 bouyer #undef DBG_BIT_PRINT 394 1.1.2.2 bouyer } 395 1.1.2.2 bouyer 396 1.1.2.2 bouyer void 397 1.1.2.3 bouyer SHArchitecture::pfc_dump() 398 1.1.2.3 bouyer { 399 1.1.2.3 bouyer DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 400 1.1.2.3 bouyer DPRINTF((TEXT("[control]\n"))); 401 1.1.2.3 bouyer #define DUMP_PFC_REG(x) \ 402 1.1.2.3 bouyer DPRINTF((TEXT("P%SCR :"), #x)); \ 403 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 404 1.1.2.3 bouyer DUMP_PFC_REG(A); 405 1.1.2.3 bouyer DUMP_PFC_REG(B); 406 1.1.2.3 bouyer DUMP_PFC_REG(C); 407 1.1.2.3 bouyer DUMP_PFC_REG(D); 408 1.1.2.3 bouyer DUMP_PFC_REG(E); 409 1.1.2.3 bouyer DUMP_PFC_REG(F); 410 1.1.2.3 bouyer DUMP_PFC_REG(G); 411 1.1.2.3 bouyer DUMP_PFC_REG(H); 412 1.1.2.3 bouyer DUMP_PFC_REG(J); 413 1.1.2.3 bouyer DUMP_PFC_REG(K); 414 1.1.2.3 bouyer DUMP_PFC_REG(L); 415 1.1.2.3 bouyer #undef DUMP_PFC_REG 416 1.1.2.3 bouyer DPRINTF((TEXT("SCPCR :"))); 417 1.1.2.3 bouyer bitdisp(reg_read_2(SH3_SCPCR_REG16)); 418 1.1.2.3 bouyer DPRINTF((TEXT("\n[data]\n"))); 419 1.1.2.3 bouyer #define DUMP_IOPORT_REG(x) \ 420 1.1.2.3 bouyer DPRINTF((TEXT("P%SDR :"), #x)); \ 421 1.1.2.3 bouyer bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 422 1.1.2.3 bouyer DUMP_IOPORT_REG(A); 423 1.1.2.3 bouyer DUMP_IOPORT_REG(B); 424 1.1.2.3 bouyer DUMP_IOPORT_REG(C); 425 1.1.2.3 bouyer DUMP_IOPORT_REG(D); 426 1.1.2.3 bouyer DUMP_IOPORT_REG(E); 427 1.1.2.3 bouyer DUMP_IOPORT_REG(F); 428 1.1.2.3 bouyer DUMP_IOPORT_REG(G); 429 1.1.2.3 bouyer DUMP_IOPORT_REG(H); 430 1.1.2.3 bouyer DUMP_IOPORT_REG(J); 431 1.1.2.3 bouyer DUMP_IOPORT_REG(K); 432 1.1.2.3 bouyer DUMP_IOPORT_REG(L); 433 1.1.2.3 bouyer #undef DUMP_IOPORT_REG 434 1.1.2.3 bouyer DPRINTF((TEXT("SCPDR :"))); 435 1.1.2.3 bouyer bitdisp(reg_read_1(SH3_SCPDR_REG8)); 436 1.1.2.3 bouyer } 437 1.1.2.3 bouyer 438 1.1.2.3 bouyer void 439 1.1.2.4 bouyer SHArchitecture::tmu_dump() 440 1.1.2.4 bouyer { 441 1.1.2.4 bouyer u_int8_t r8; 442 1.1.2.4 bouyer 443 1.1.2.4 bouyer DPRINTF((TEXT("<<<TMU>>>\n"))); 444 1.1.2.4 bouyer /* Common */ 445 1.1.2.4 bouyer /* TOCR timer output control register */ 446 1.1.2.4 bouyer r8 = reg_read_1(SH3_TOCR_REG8); 447 1.1.2.4 bouyer DPRINTF((TEXT("TCLK = %S\n"), 448 1.1.2.4 bouyer r8 & TOCR_TCOE ? "RTC output" : "input")); 449 1.1.2.4 bouyer /* TSTR */ 450 1.1.2.4 bouyer r8 = reg_read_1(SH3_TSTR_REG8); 451 1.1.2.4 bouyer DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), 452 1.1.2.4 bouyer r8 & TSTR_STR0 ? 'x' : '_', 453 1.1.2.4 bouyer r8 & TSTR_STR1 ? 'x' : '_', 454 1.1.2.4 bouyer r8 & TSTR_STR2 ? 'x' : '_')); 455 1.1.2.4 bouyer 456 1.1.2.4 bouyer #define CHANNEL_DUMP(a, x) \ 457 1.1.2.4 bouyer tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ 458 1.1.2.4 bouyer SH##a##_TCNT##x##_REG, \ 459 1.1.2.4 bouyer SH##a##_TCR##x##_REG16) 460 1.1.2.4 bouyer CHANNEL_DUMP(3, 0); 461 1.1.2.4 bouyer CHANNEL_DUMP(3, 1); 462 1.1.2.4 bouyer CHANNEL_DUMP(3, 2); 463 1.1.2.4 bouyer #undef CHANNEL_DUMP 464 1.1.2.4 bouyer DPRINTF((TEXT("\n"))); 465 1.1.2.4 bouyer } 466 1.1.2.4 bouyer 467 1.1.2.4 bouyer void 468 1.1.2.4 bouyer SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, 469 1.1.2.4 bouyer paddr_t tcr) 470 1.1.2.4 bouyer { 471 1.1.2.4 bouyer u_int32_t r32; 472 1.1.2.4 bouyer u_int16_t r16; 473 1.1.2.4 bouyer 474 1.1.2.4 bouyer DPRINTF((TEXT("TMU#%d:"), unit)); 475 1.1.2.4 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) 476 1.1.2.4 bouyer /* TCR*/ 477 1.1.2.4 bouyer r16 = reg_read_2(tcr); 478 1.1.2.4 bouyer DBG_BIT_PRINT(r16, UNF); 479 1.1.2.4 bouyer DBG_BIT_PRINT(r16, UNIE); 480 1.1.2.4 bouyer DBG_BIT_PRINT(r16, CKEG1); 481 1.1.2.4 bouyer DBG_BIT_PRINT(r16, CKEG0); 482 1.1.2.4 bouyer DBG_BIT_PRINT(r16, TPSC2); 483 1.1.2.4 bouyer DBG_BIT_PRINT(r16, TPSC1); 484 1.1.2.4 bouyer DBG_BIT_PRINT(r16, TPSC0); 485 1.1.2.4 bouyer /* channel 2 has input capture. */ 486 1.1.2.4 bouyer if (unit == 2) { 487 1.1.2.4 bouyer DBG_BIT_PRINT(r16, ICPF); 488 1.1.2.4 bouyer DBG_BIT_PRINT(r16, ICPE1); 489 1.1.2.4 bouyer DBG_BIT_PRINT(r16, ICPE0); 490 1.1.2.4 bouyer } 491 1.1.2.4 bouyer #undef DBG_BIT_PRINT 492 1.1.2.4 bouyer /* TCNT0 timer counter */ 493 1.1.2.4 bouyer r32 = reg_read_4(tcnt); 494 1.1.2.4 bouyer DPRINTF((TEXT("\ncnt=0x%08x"), r32)); 495 1.1.2.4 bouyer /* TCOR0 timer constant register */ 496 1.1.2.4 bouyer r32 = reg_read_4(tcor); 497 1.1.2.4 bouyer DPRINTF((TEXT(" constant=0x%04x"), r32)); 498 1.1.2.4 bouyer 499 1.1.2.4 bouyer if (unit == 2) 500 1.1.2.4 bouyer DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); 501 1.1.2.4 bouyer else 502 1.1.2.4 bouyer DPRINTF((TEXT("\n"))); 503 1.1.2.4 bouyer } 504 1.1.2.4 bouyer 505 1.1.2.4 bouyer void 506 1.1.2.3 bouyer SHArchitecture::hd64461_dump(platid_t &platform) 507 1.1.2.2 bouyer { 508 1.1.2.3 bouyer u_int16_t r16; 509 1.1.2.3 bouyer u_int8_t r8; 510 1.1.2.3 bouyer 511 1.1.2.3 bouyer #define MATCH(p) \ 512 1.1.2.3 bouyer platid_match(&platform, &platid_mask_MACH_##p) 513 1.1.2.3 bouyer 514 1.1.2.3 bouyer DPRINTF((TEXT("<<<HD64461>>>\n"))); 515 1.1.2.3 bouyer if (!MATCH(HP_LX) && 516 1.1.2.3 bouyer !MATCH(HP_JORNADA_6XX) && 517 1.1.2.3 bouyer !MATCH(HITACHI_PERSONA_HPW230JC)) { 518 1.1.2.3 bouyer DPRINTF((TEXT("don't exist."))); 519 1.1.2.3 bouyer return; 520 1.1.2.3 bouyer } 521 1.1.2.3 bouyer 522 1.1.2.3 bouyer #if 0 523 1.1.2.2 bouyer DPRINTF((TEXT("frame buffer test start\n"))); 524 1.1.2.3 bouyer u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 525 1.1.2.3 bouyer 526 1.1.2.3 bouyer for (int i = 0; i < 320 * 240 * 2 / 8; i++) 527 1.1.2.3 bouyer *fb++ = 0xff; 528 1.1.2.3 bouyer DPRINTF((TEXT("frame buffer test end\n"))); 529 1.1.2.3 bouyer #endif 530 1.1.2.3 bouyer // System 531 1.1.2.3 bouyer DPRINTF((TEXT("STBCR (System Control Register)\n"))); 532 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 533 1.1.2.3 bouyer bitdisp(r16); 534 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 535 1.1.2.3 bouyer DBG_BIT_PRINT(r16, CKIO_STBY); 536 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFECKE_IST); 537 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCKE_IST); 538 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFECKE_OST); 539 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCKE_OST); 540 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMIAST); 541 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCDST); 542 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPC0ST); 543 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPC1ST); 544 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SAFEST); 545 1.1.2.3 bouyer DBG_BIT_PRINT(r16, STM0ST); 546 1.1.2.3 bouyer DBG_BIT_PRINT(r16, STM1ST); 547 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SIRST); 548 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SURTSD); 549 1.1.2.3 bouyer #undef DBG_BIT_PRINT 550 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 551 1.1.2.3 bouyer 552 1.1.2.3 bouyer DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 553 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 554 1.1.2.3 bouyer bitdisp(r16); 555 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 556 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 557 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTA_IR); 558 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTA_TM); 559 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPTB_UR); 560 1.1.2.3 bouyer DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 561 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMODE1); 562 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SMODE0); 563 1.1.2.3 bouyer #undef DBG_BIT_PRINT 564 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 565 1.1.2.3 bouyer 566 1.1.2.3 bouyer DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 567 1.1.2.3 bouyer r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 568 1.1.2.3 bouyer bitdisp(r16); 569 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 570 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPDSTOF); 571 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPDSTIG); 572 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPCSTOF); 573 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPCSTIG); 574 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPBSTOF); 575 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPBSTIG); 576 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPASTOF); 577 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SPASTIG); 578 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SLCDSTIG); 579 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_CS56_EP); 580 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_CMD_EP); 581 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 582 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPDPU); 583 1.1.2.3 bouyer DBG_BIT_PRINT(r16, SCPU_A2319_EP); 584 1.1.2.3 bouyer #undef DBG_BIT_PRINT 585 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 586 1.1.2.3 bouyer 587 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 588 1.1.2.3 bouyer 589 1.1.2.3 bouyer // INTC 590 1.1.2.3 bouyer DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 591 1.1.2.3 bouyer r16 = reg_read_2(HD64461_INTCNIRR_REG16); 592 1.1.2.3 bouyer bitdisp(r16); 593 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 594 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC0R); 595 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC1R); 596 1.1.2.3 bouyer DBG_BIT_PRINT(r16, AFER); 597 1.1.2.3 bouyer DBG_BIT_PRINT(r16, GPIOR); 598 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU0R); 599 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU1R); 600 1.1.2.3 bouyer DBG_BIT_PRINT(r16, IRDAR); 601 1.1.2.3 bouyer DBG_BIT_PRINT(r16, UARTR); 602 1.1.2.3 bouyer #undef DBG_BIT_PRINT 603 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 604 1.1.2.3 bouyer 605 1.1.2.3 bouyer DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 606 1.1.2.3 bouyer r16 = reg_read_2(HD64461_INTCNIMR_REG16); 607 1.1.2.3 bouyer bitdisp(r16); 608 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 609 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC0M); 610 1.1.2.3 bouyer DBG_BIT_PRINT(r16, PCC1M); 611 1.1.2.3 bouyer DBG_BIT_PRINT(r16, AFEM); 612 1.1.2.3 bouyer DBG_BIT_PRINT(r16, GPIOM); 613 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU0M); 614 1.1.2.3 bouyer DBG_BIT_PRINT(r16, TMU1M); 615 1.1.2.3 bouyer DBG_BIT_PRINT(r16, IRDAM); 616 1.1.2.3 bouyer DBG_BIT_PRINT(r16, UARTM); 617 1.1.2.3 bouyer #undef DBG_BIT_PRINT 618 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 619 1.1.2.3 bouyer 620 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 621 1.1.2.3 bouyer 622 1.1.2.3 bouyer // PCMCIA 623 1.1.2.3 bouyer // PCC0 624 1.1.2.3 bouyer DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 625 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 626 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0ISR_REG8); 627 1.1.2.3 bouyer bitdisp(r8); 628 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 629 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0READY); 630 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0MWP); 631 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VS2); 632 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VS1); 633 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CD2); 634 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CD1); 635 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BVD2); 636 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BVD1); 637 1.1.2.3 bouyer #undef DBG_BIT_PRINT 638 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 639 1.1.2.3 bouyer 640 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 General Control Register\n"))); 641 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0GCR_REG8); 642 1.1.2.3 bouyer bitdisp(r8); 643 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 644 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0DRVE); 645 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PCCR); 646 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PCCT); 647 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VCC0); 648 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0MMOD); 649 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PA25); 650 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0PA24); 651 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0REG); 652 1.1.2.3 bouyer #undef DBG_BIT_PRINT 653 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 654 1.1.2.3 bouyer 655 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 656 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 657 1.1.2.3 bouyer bitdisp(r8); 658 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 659 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SCDI); 660 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0IREQ); 661 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SC); 662 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CDC); 663 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0RC); 664 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BW); 665 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BD); 666 1.1.2.3 bouyer #undef DBG_BIT_PRINT 667 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 668 1.1.2.3 bouyer 669 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 670 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 671 1.1.2.3 bouyer bitdisp(r8); 672 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 673 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CRE); 674 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SCE); 675 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0CDE); 676 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0RE); 677 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BWE); 678 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0BDE); 679 1.1.2.3 bouyer #undef DBG_BIT_PRINT 680 1.1.2.3 bouyer DPRINTF((TEXT("\ninterrupt type: "))); 681 1.1.2.3 bouyer switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 682 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_NONE: 683 1.1.2.3 bouyer DPRINTF((TEXT("none\n"))); 684 1.1.2.3 bouyer break; 685 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 686 1.1.2.3 bouyer DPRINTF((TEXT("level\n"))); 687 1.1.2.3 bouyer break; 688 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 689 1.1.2.3 bouyer DPRINTF((TEXT("falling edge\n"))); 690 1.1.2.3 bouyer break; 691 1.1.2.3 bouyer case HD64461_PCC0CSCIER_P0IREQE_REDGE: 692 1.1.2.3 bouyer DPRINTF((TEXT("rising edge\n"))); 693 1.1.2.3 bouyer break; 694 1.1.2.3 bouyer } 695 1.1.2.3 bouyer 696 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Software Control Register\n"))); 697 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC0SCR_REG8); 698 1.1.2.3 bouyer bitdisp(r8); 699 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 700 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0VCC1); 701 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0SWP); 702 1.1.2.3 bouyer #undef DBG_BIT_PRINT 703 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 704 1.1.2.3 bouyer 705 1.1.2.3 bouyer // PCC1 706 1.1.2.3 bouyer DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 707 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 708 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1ISR_REG8); 709 1.1.2.3 bouyer bitdisp(r8); 710 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 711 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1READY); 712 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1MWP); 713 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VS2); 714 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VS1); 715 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CD2); 716 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CD1); 717 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BVD2); 718 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BVD1); 719 1.1.2.3 bouyer #undef DBG_BIT_PRINT 720 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 721 1.1.2.3 bouyer 722 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 723 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1GCR_REG8); 724 1.1.2.3 bouyer bitdisp(r8); 725 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 726 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1DRVE); 727 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PCCR); 728 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VCC0); 729 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1MMOD); 730 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PA25); 731 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1PA24); 732 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1REG); 733 1.1.2.3 bouyer #undef DBG_BIT_PRINT 734 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 735 1.1.2.3 bouyer 736 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 737 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 738 1.1.2.3 bouyer bitdisp(r8); 739 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 740 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1SCDI); 741 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CDC); 742 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RC); 743 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BW); 744 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BD); 745 1.1.2.3 bouyer #undef DBG_BIT_PRINT 746 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 747 1.1.2.3 bouyer 748 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 749 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 750 1.1.2.3 bouyer bitdisp(r8); 751 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 752 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CRE); 753 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1CDE); 754 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RE); 755 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BWE); 756 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1BDE); 757 1.1.2.3 bouyer #undef DBG_BIT_PRINT 758 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 759 1.1.2.3 bouyer 760 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Software Control Register\n"))); 761 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCC1SCR_REG8); 762 1.1.2.3 bouyer bitdisp(r8); 763 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 764 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1VCC1); 765 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1SWP); 766 1.1.2.3 bouyer #undef DBG_BIT_PRINT 767 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 768 1.1.2.3 bouyer 769 1.1.2.3 bouyer // General Control 770 1.1.2.3 bouyer DPRINTF((TEXT("[General Control]\n"))); 771 1.1.2.3 bouyer DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 772 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 773 1.1.2.3 bouyer bitdisp(r8); 774 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 775 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0DEPLUP); 776 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P0AEPLUP); 777 1.1.2.3 bouyer #undef DBG_BIT_PRINT 778 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 779 1.1.2.3 bouyer 780 1.1.2.3 bouyer DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 781 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 782 1.1.2.3 bouyer bitdisp(r8); 783 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 784 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RST8MA); 785 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RST4MA); 786 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RAS8MA); 787 1.1.2.3 bouyer DBG_BIT_PRINT(r8, P1RAS4MA); 788 1.1.2.3 bouyer #undef DBG_BIT_PRINT 789 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 790 1.1.2.3 bouyer 791 1.1.2.3 bouyer DPRINTF((TEXT("PC Card General Control Register\n"))); 792 1.1.2.3 bouyer r8 = reg_read_1(HD64461_PCCPGCR_REG8); 793 1.1.2.3 bouyer bitdisp(r8); 794 1.1.2.3 bouyer #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 795 1.1.2.3 bouyer DBG_BIT_PRINT(r8, PSSDIR); 796 1.1.2.3 bouyer DBG_BIT_PRINT(r8, PSSRDWR); 797 1.1.2.3 bouyer #undef DBG_BIT_PRINT 798 1.1.2.3 bouyer DPRINTF((TEXT("\n"))); 799 1.1.2.3 bouyer 800 1.1.2.3 bouyer // GPIO 801 1.1.2.3 bouyer #define GPIO_DUMP_REG8(x) \ 802 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 803 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 804 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 805 1.1.2.3 bouyer bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 806 1.1.2.3 bouyer #define GPIO_DUMP_REG16(x) \ 807 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 808 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 809 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 810 1.1.2.3 bouyer bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 811 1.1.2.3 bouyer 812 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Control Register\n"))); 813 1.1.2.3 bouyer GPIO_DUMP_REG16(C); 814 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Data Register\n"))); 815 1.1.2.3 bouyer GPIO_DUMP_REG8(D); 816 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 817 1.1.2.3 bouyer GPIO_DUMP_REG8(IC); 818 1.1.2.3 bouyer DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 819 1.1.2.3 bouyer GPIO_DUMP_REG8(IS); 820 1.1.2.3 bouyer } 821 1.1.2.3 bouyer 822 1.1.2.3 bouyer #ifdef SH7709TEST 823 1.1.2.2 bouyer u_int32_t sh7707_fb_dma_addr; 824 1.1.2.2 bouyer u_int16_t val; 825 1.1.2.2 bouyer int s; 826 1.1.2.2 bouyer 827 1.1.2.2 bouyer s = suspendIntr(); 828 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 829 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 830 1.1.2.2 bouyer sh7707_fb_dma_addr = val; 831 1.1.2.2 bouyer VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 832 1.1.2.2 bouyer val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 833 1.1.2.2 bouyer sh7707_fb_dma_addr |= (val << 16); 834 1.1.2.2 bouyer resumeIntr(s); 835 1.1.2.2 bouyer 836 1.1.2.2 bouyer DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 837 1.1.2.2 bouyer sh7707_fb_dma_addr)); 838 1.1.2.2 bouyer #endif 839
Indexes created Thu Sep 25 16:09:42 GMT 2025