sh_arch.cpp revision 1.2
1 /* $NetBSD: sh_arch.cpp,v 1.2 2001/02/21 16:01:54 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcmenu.h> 40 #include <sh3/sh_arch.h> 41 #include <sh3/hd64461.h> 42 #include "scifreg.h" 43 44 struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 45 { "TMU0", ICU_IPRA_REG16, 12 }, 46 { "TMU1", ICU_IPRA_REG16, 8 }, 47 { "TMU2", ICU_IPRA_REG16, 4 }, 48 { "RTC", ICU_IPRA_REG16, 0 }, 49 { "WDT", ICU_IPRB_REG16, 12 }, 50 { "REF", ICU_IPRB_REG16, 8 }, 51 { "SCI", ICU_IPRB_REG16, 4 }, 52 { "reserve", ICU_IPRB_REG16, 0 }, 53 { "IRQ3", ICU_IPRC_REG16, 12 }, 54 { "IRQ2", ICU_IPRC_REG16, 8 }, 55 { "IRQ1", ICU_IPRC_REG16, 4 }, 56 { "IRQ0", ICU_IPRC_REG16, 0 }, 57 { "PINT0-7", ICU_IPRD_REG16, 12 }, 58 { "PINT8-15", ICU_IPRD_REG16, 8 }, 59 { "IRQ5", ICU_IPRD_REG16, 4 }, 60 { "IRQ4", ICU_IPRD_REG16, 0 }, 61 { "DMAC", ICU_IPRE_REG16, 12 }, 62 { "IrDA", ICU_IPRE_REG16, 8 }, 63 { "SCIF", ICU_IPRE_REG16, 4 }, 64 { "ADC", ICU_IPRE_REG16, 0 }, 65 { 0, 0, 0} /* terminator */ 66 }; 67 68 BOOL 69 SHArchitecture::init(void) 70 { 71 if (!_mem->init()) { 72 DPRINTF((TEXT("can't initialize memory manager.\n"))); 73 return FALSE; 74 } 75 // set D-RAM information 76 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 77 _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 78 79 return TRUE; 80 } 81 82 BOOL 83 SHArchitecture::setupLoader() 84 { 85 vaddr_t v; 86 87 if (!_mem->getPage(v , _loader_addr)) { 88 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 89 return FALSE; 90 } 91 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 92 (unsigned)v,(unsigned)_loader_addr)); 93 94 memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 95 DPRINTF((TEXT("2nd bootloader copy done.\n"))); 96 97 return TRUE; 98 } 99 100 void 101 SHArchitecture::jump(paddr_t info, paddr_t pvec) 102 { 103 kaddr_t sp; 104 vaddr_t v; 105 paddr_t p; 106 107 // stack for bootloader 108 _mem->getPage(v, p); 109 sp = ptokv(p + _mem->getPageSize() / 2); 110 111 info = ptokv(info); 112 pvec = ptokv(pvec); 113 _loader_addr = ptokv(_loader_addr); 114 DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 115 info, sp)); 116 117 // Change to privilege-mode. 118 SetKMode(1); 119 120 // Disable external interrupt. 121 suspendIntr(); 122 123 // Cache flush(for 2nd bootloader) 124 cache_flush(); 125 126 // jump to 2nd loader.(run P1) at this time I still use MMU. 127 __asm("mov r6, r15\n" 128 "jmp @r7\n" 129 "nop\n", info, pvec, sp, _loader_addr); 130 // NOTREACHED 131 } 132 133 // disable external interrupt and save its priority. 134 u_int32_t 135 suspendIntr(void) 136 { 137 u_int32_t sr; 138 __asm("stc sr, r0\n" 139 "mov.l r0, @r4\n" 140 "or r5, r0\n" 141 "ldc r0, sr\n", &sr, 0x000000f0); 142 return sr & 0x000000f0; 143 } 144 145 // resume external interrupt priority. 146 void 147 resumeIntr(u_int32_t s) 148 { 149 __asm("stc sr, r0\n" 150 "and r5, r0\n" 151 "or r4, r0\n" 152 "ldc r0, sr\n", s, 0xffffff0f); 153 } 154 155 void 156 SHArchitecture::print_stack_pointer(void) 157 { 158 int sp; 159 __asm("mov.l r15, @r4", &sp); 160 DPRINTF((TEXT("SP 0x%08x\n"), sp)); 161 } 162 163 void 164 SHArchitecture::systemInfo() 165 { 166 u_int32_t reg; 167 168 Architecture::systemInfo(); 169 170 _kmode = SetKMode(1); 171 172 // Cache 173 reg = VOLATILE_REF(CCR); 174 DPRINTF((TEXT("Cache "))); 175 if (reg & CCR_CE) 176 DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 177 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 178 reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 179 reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 180 else 181 DPRINTF((TEXT("Disabled.\n"))); 182 183 // MMU 184 reg = VOLATILE_REF(MMUCR); 185 DPRINTF((TEXT("MMU "))); 186 if (reg & MMUCR_AT) 187 DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 188 reg & MMUCR_IX 189 ? TEXT("ASID + VPN") : TEXT("VPN only"), 190 reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 191 else 192 DPRINTF((TEXT("Disabled.\n"))); 193 194 // Status register 195 reg = 0; 196 __asm("stc sr, r0\n" 197 "mov.l r0, @r4", ®); 198 DPRINTF((TEXT("SR 0x%08x\n"), reg)); 199 200 // BSC 201 bsc_dump(); 202 203 // ICU 204 print_stack_pointer(); 205 icu_dump(); 206 207 // PFC , I/O port 208 pfc_dump(); 209 210 // SCIF 211 scif_dump(19200); 212 213 // HD64461 214 platid_t platform; 215 HpcMenuInterface &menu = HpcMenuInterface::Instance(); 216 platform.dw.dw0 = menu._pref.platid_hi; 217 platform.dw.dw1 = menu._pref.platid_lo; 218 hd64461_dump(platform); 219 220 SetKMode(_kmode); 221 } 222 223 void 224 SHArchitecture::icu_dump(void) 225 { 226 DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 227 print_stack_pointer(); 228 229 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 230 DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 231 DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 232 DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 233 DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 234 DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 235 DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 236 DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 237 DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 238 DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 239 DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 240 DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 241 icu_control(); 242 icu_priority(); 243 } 244 245 void 246 SHArchitecture::icu_priority(void) 247 { 248 struct intr_priority *tab; 249 DPRINTF((TEXT("----interrupt priority----\n"))); 250 for (tab = ipr_table; tab->name; tab++) { 251 DPRINTF((TEXT("%-10S %d\n"), tab->name, 252 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 253 } 254 DPRINTF((TEXT("--------------------------\n"))); 255 } 256 257 void 258 SHArchitecture::icu_control(void) 259 { 260 const char *sense_select[] = { 261 "falling edge", 262 "raising edge", 263 "low level", 264 "reserved", 265 }; 266 u_int16_t r; 267 268 // PINT0-15 269 DPRINTF((TEXT("PINT enable(on |) :"))); 270 bitdisp(reg_read_2(ICU_PINTER_REG16)); 271 DPRINTF((TEXT("PINT detect(high |):"))); 272 bitdisp(reg_read_2(ICU_ICR2_REG16)); 273 // NMI 274 r = reg_read_2(ICU_ICR0_REG16); 275 DPRINTF((TEXT("NMI(%S %S-edge),"), 276 r & ICU_ICR0_NMIL ? "High" : "Low", 277 r & ICU_ICR0_NMIE ? "raising" : "falling")); 278 r = reg_read_2(ICU_ICR1_REG16); 279 DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 280 DPRINTF((TEXT(" SR.BL %S\n"), 281 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 282 // IRQ0-5 283 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 284 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 285 if (r & ICU_ICR1_IRQLVL) { 286 DPRINTF((TEXT("IRLS[0:3] %S\n"), 287 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 288 } 289 // sense select 290 for (int i = 5; i >= 0; i--) { 291 DPRINTF((TEXT("IRQ[%d] %S\n"), i, 292 sense_select [ 293 (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 294 } 295 } 296 297 SH_BOOT_FUNC_(7709); 298 SH_BOOT_FUNC_(7709A); 299 300 // 301 // Debug Functions. 302 // 303 void 304 SHArchitecture::bsc_dump() 305 { 306 DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 307 #define DUMP_BSC_REG(x) \ 308 DPRINTF((TEXT("%-8S"), #x)); \ 309 bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 310 DUMP_BSC_REG(BCR1); 311 DUMP_BSC_REG(BCR2); 312 DUMP_BSC_REG(WCR1); 313 DUMP_BSC_REG(WCR2); 314 DUMP_BSC_REG(MCR); 315 DUMP_BSC_REG(DCR); 316 DUMP_BSC_REG(PCR); 317 DUMP_BSC_REG(RTCSR); 318 DUMP_BSC_REG(RTCNT); 319 DUMP_BSC_REG(RTCOR); 320 DUMP_BSC_REG(RFCR); 321 DUMP_BSC_REG(BCR3); 322 #undef DUMP_BSC_REG 323 } 324 325 void 326 SHArchitecture::scif_dump(int bps) 327 { 328 u_int16_t r16; 329 u_int8_t r8; 330 int n; 331 332 DPRINTF((TEXT("<<<SCIF>>>\n"))); 333 /* mode */ 334 r8 = SHREG_SCSMR2; 335 n = 1 <<((r8 & SCSMR2_CKS) << 1); 336 DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 337 r8 & SCSMR2_CHR ? 7 : 8, 338 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 339 r8 & SCSMR2_STOP ? 2 : 1, 340 n)); 341 /* bit rate */ 342 r8 = SHREG_SCBRR2; 343 DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 344 32 * bps *(r8 + 1) * n)); 345 346 /* control */ 347 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 348 DPRINTF((TEXT("SCSCR2: "))); 349 r8 = SHREG_SCSCR2; 350 DBG_BIT_PRINT(r8, TIE); 351 DBG_BIT_PRINT(r8, RIE); 352 DBG_BIT_PRINT(r8, TE); 353 DBG_BIT_PRINT(r8, RE); 354 DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 355 #undef DBG_BIT_PRINT 356 357 /* status */ 358 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 359 r16 = SHREG_SCSSR2; 360 DPRINTF((TEXT("SCSSR2: "))); 361 DBG_BIT_PRINT(r16, ER); 362 DBG_BIT_PRINT(r16, TEND); 363 DBG_BIT_PRINT(r16, TDFE); 364 DBG_BIT_PRINT(r16, BRK); 365 DBG_BIT_PRINT(r16, FER); 366 DBG_BIT_PRINT(r16, PER); 367 DBG_BIT_PRINT(r16, RDF); 368 DBG_BIT_PRINT(r16, DR); 369 #undef DBG_BIT_PRINT 370 371 /* FIFO control */ 372 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 373 r8 = SHREG_SCFCR2; 374 DPRINTF((TEXT("SCFCR2: "))); 375 DBG_BIT_PRINT(r8, RTRG1); 376 DBG_BIT_PRINT(r8, RTRG0); 377 DBG_BIT_PRINT(r8, TTRG1); 378 DBG_BIT_PRINT(r8, TTRG0); 379 DBG_BIT_PRINT(r8, MCE); 380 DBG_BIT_PRINT(r8, TFRST); 381 DBG_BIT_PRINT(r8, RFRST); 382 DBG_BIT_PRINT(r8, LOOP); 383 DPRINTF((TEXT("\n"))); 384 #undef DBG_BIT_PRINT 385 } 386 387 void 388 SHArchitecture::pfc_dump() 389 { 390 DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 391 DPRINTF((TEXT("[control]\n"))); 392 #define DUMP_PFC_REG(x) \ 393 DPRINTF((TEXT("P%SCR :"), #x)); \ 394 bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 395 DUMP_PFC_REG(A); 396 DUMP_PFC_REG(B); 397 DUMP_PFC_REG(C); 398 DUMP_PFC_REG(D); 399 DUMP_PFC_REG(E); 400 DUMP_PFC_REG(F); 401 DUMP_PFC_REG(G); 402 DUMP_PFC_REG(H); 403 DUMP_PFC_REG(J); 404 DUMP_PFC_REG(K); 405 DUMP_PFC_REG(L); 406 #undef DUMP_PFC_REG 407 DPRINTF((TEXT("SCPCR :"))); 408 bitdisp(reg_read_2(SH3_SCPCR_REG16)); 409 DPRINTF((TEXT("\n[data]\n"))); 410 #define DUMP_IOPORT_REG(x) \ 411 DPRINTF((TEXT("P%SDR :"), #x)); \ 412 bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 413 DUMP_IOPORT_REG(A); 414 DUMP_IOPORT_REG(B); 415 DUMP_IOPORT_REG(C); 416 DUMP_IOPORT_REG(D); 417 DUMP_IOPORT_REG(E); 418 DUMP_IOPORT_REG(F); 419 DUMP_IOPORT_REG(G); 420 DUMP_IOPORT_REG(H); 421 DUMP_IOPORT_REG(J); 422 DUMP_IOPORT_REG(K); 423 DUMP_IOPORT_REG(L); 424 #undef DUMP_IOPORT_REG 425 DPRINTF((TEXT("SCPDR :"))); 426 bitdisp(reg_read_1(SH3_SCPDR_REG8)); 427 } 428 429 void 430 SHArchitecture::hd64461_dump(platid_t &platform) 431 { 432 u_int16_t r16; 433 u_int8_t r8; 434 435 #define MATCH(p) \ 436 platid_match(&platform, &platid_mask_MACH_##p) 437 438 DPRINTF((TEXT("<<<HD64461>>>\n"))); 439 if (!MATCH(HP_LX) && 440 !MATCH(HP_JORNADA_6XX) && 441 !MATCH(HITACHI_PERSONA_HPW230JC)) { 442 DPRINTF((TEXT("don't exist."))); 443 return; 444 } 445 446 #if 0 447 DPRINTF((TEXT("frame buffer test start\n"))); 448 u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 449 450 for (int i = 0; i < 320 * 240 * 2 / 8; i++) 451 *fb++ = 0xff; 452 DPRINTF((TEXT("frame buffer test end\n"))); 453 #endif 454 // System 455 DPRINTF((TEXT("STBCR (System Control Register)\n"))); 456 r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 457 bitdisp(r16); 458 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 459 DBG_BIT_PRINT(r16, CKIO_STBY); 460 DBG_BIT_PRINT(r16, SAFECKE_IST); 461 DBG_BIT_PRINT(r16, SLCKE_IST); 462 DBG_BIT_PRINT(r16, SAFECKE_OST); 463 DBG_BIT_PRINT(r16, SLCKE_OST); 464 DBG_BIT_PRINT(r16, SMIAST); 465 DBG_BIT_PRINT(r16, SLCDST); 466 DBG_BIT_PRINT(r16, SPC0ST); 467 DBG_BIT_PRINT(r16, SPC1ST); 468 DBG_BIT_PRINT(r16, SAFEST); 469 DBG_BIT_PRINT(r16, STM0ST); 470 DBG_BIT_PRINT(r16, STM1ST); 471 DBG_BIT_PRINT(r16, SIRST); 472 DBG_BIT_PRINT(r16, SURTSD); 473 #undef DBG_BIT_PRINT 474 DPRINTF((TEXT("\n"))); 475 476 DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 477 r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 478 bitdisp(r16); 479 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 480 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 481 DBG_BIT_PRINT(r16, SPTA_IR); 482 DBG_BIT_PRINT(r16, SPTA_TM); 483 DBG_BIT_PRINT(r16, SPTB_UR); 484 DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 485 DBG_BIT_PRINT(r16, SMODE1); 486 DBG_BIT_PRINT(r16, SMODE0); 487 #undef DBG_BIT_PRINT 488 DPRINTF((TEXT("\n"))); 489 490 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 491 r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 492 bitdisp(r16); 493 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 494 DBG_BIT_PRINT(r16, SPDSTOF); 495 DBG_BIT_PRINT(r16, SPDSTIG); 496 DBG_BIT_PRINT(r16, SPCSTOF); 497 DBG_BIT_PRINT(r16, SPCSTIG); 498 DBG_BIT_PRINT(r16, SPBSTOF); 499 DBG_BIT_PRINT(r16, SPBSTIG); 500 DBG_BIT_PRINT(r16, SPASTOF); 501 DBG_BIT_PRINT(r16, SPASTIG); 502 DBG_BIT_PRINT(r16, SLCDSTIG); 503 DBG_BIT_PRINT(r16, SCPU_CS56_EP); 504 DBG_BIT_PRINT(r16, SCPU_CMD_EP); 505 DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 506 DBG_BIT_PRINT(r16, SCPDPU); 507 DBG_BIT_PRINT(r16, SCPU_A2319_EP); 508 #undef DBG_BIT_PRINT 509 DPRINTF((TEXT("\n"))); 510 511 DPRINTF((TEXT("\n"))); 512 513 // INTC 514 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 515 r16 = reg_read_2(HD64461_INTCNIRR_REG16); 516 bitdisp(r16); 517 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 518 DBG_BIT_PRINT(r16, PCC0R); 519 DBG_BIT_PRINT(r16, PCC1R); 520 DBG_BIT_PRINT(r16, AFER); 521 DBG_BIT_PRINT(r16, GPIOR); 522 DBG_BIT_PRINT(r16, TMU0R); 523 DBG_BIT_PRINT(r16, TMU1R); 524 DBG_BIT_PRINT(r16, IRDAR); 525 DBG_BIT_PRINT(r16, UARTR); 526 #undef DBG_BIT_PRINT 527 DPRINTF((TEXT("\n"))); 528 529 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 530 r16 = reg_read_2(HD64461_INTCNIMR_REG16); 531 bitdisp(r16); 532 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 533 DBG_BIT_PRINT(r16, PCC0M); 534 DBG_BIT_PRINT(r16, PCC1M); 535 DBG_BIT_PRINT(r16, AFEM); 536 DBG_BIT_PRINT(r16, GPIOM); 537 DBG_BIT_PRINT(r16, TMU0M); 538 DBG_BIT_PRINT(r16, TMU1M); 539 DBG_BIT_PRINT(r16, IRDAM); 540 DBG_BIT_PRINT(r16, UARTM); 541 #undef DBG_BIT_PRINT 542 DPRINTF((TEXT("\n"))); 543 544 DPRINTF((TEXT("\n"))); 545 546 // PCMCIA 547 // PCC0 548 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 549 DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 550 r8 = reg_read_1(HD64461_PCC0ISR_REG8); 551 bitdisp(r8); 552 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 553 DBG_BIT_PRINT(r8, P0READY); 554 DBG_BIT_PRINT(r8, P0MWP); 555 DBG_BIT_PRINT(r8, P0VS2); 556 DBG_BIT_PRINT(r8, P0VS1); 557 DBG_BIT_PRINT(r8, P0CD2); 558 DBG_BIT_PRINT(r8, P0CD1); 559 DBG_BIT_PRINT(r8, P0BVD2); 560 DBG_BIT_PRINT(r8, P0BVD1); 561 #undef DBG_BIT_PRINT 562 DPRINTF((TEXT("\n"))); 563 564 DPRINTF((TEXT("PCC0 General Control Register\n"))); 565 r8 = reg_read_1(HD64461_PCC0GCR_REG8); 566 bitdisp(r8); 567 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 568 DBG_BIT_PRINT(r8, P0DRVE); 569 DBG_BIT_PRINT(r8, P0PCCR); 570 DBG_BIT_PRINT(r8, P0PCCT); 571 DBG_BIT_PRINT(r8, P0VCC0); 572 DBG_BIT_PRINT(r8, P0MMOD); 573 DBG_BIT_PRINT(r8, P0PA25); 574 DBG_BIT_PRINT(r8, P0PA24); 575 DBG_BIT_PRINT(r8, P0REG); 576 #undef DBG_BIT_PRINT 577 DPRINTF((TEXT("\n"))); 578 579 DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 580 r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 581 bitdisp(r8); 582 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 583 DBG_BIT_PRINT(r8, P0SCDI); 584 DBG_BIT_PRINT(r8, P0IREQ); 585 DBG_BIT_PRINT(r8, P0SC); 586 DBG_BIT_PRINT(r8, P0CDC); 587 DBG_BIT_PRINT(r8, P0RC); 588 DBG_BIT_PRINT(r8, P0BW); 589 DBG_BIT_PRINT(r8, P0BD); 590 #undef DBG_BIT_PRINT 591 DPRINTF((TEXT("\n"))); 592 593 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 594 r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 595 bitdisp(r8); 596 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 597 DBG_BIT_PRINT(r8, P0CRE); 598 DBG_BIT_PRINT(r8, P0SCE); 599 DBG_BIT_PRINT(r8, P0CDE); 600 DBG_BIT_PRINT(r8, P0RE); 601 DBG_BIT_PRINT(r8, P0BWE); 602 DBG_BIT_PRINT(r8, P0BDE); 603 #undef DBG_BIT_PRINT 604 DPRINTF((TEXT("\ninterrupt type: "))); 605 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 606 case HD64461_PCC0CSCIER_P0IREQE_NONE: 607 DPRINTF((TEXT("none\n"))); 608 break; 609 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 610 DPRINTF((TEXT("level\n"))); 611 break; 612 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 613 DPRINTF((TEXT("falling edge\n"))); 614 break; 615 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 616 DPRINTF((TEXT("rising edge\n"))); 617 break; 618 } 619 620 DPRINTF((TEXT("PCC0 Software Control Register\n"))); 621 r8 = reg_read_1(HD64461_PCC0SCR_REG8); 622 bitdisp(r8); 623 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 624 DBG_BIT_PRINT(r8, P0VCC1); 625 DBG_BIT_PRINT(r8, P0SWP); 626 #undef DBG_BIT_PRINT 627 DPRINTF((TEXT("\n"))); 628 629 // PCC1 630 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 631 DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 632 r8 = reg_read_1(HD64461_PCC1ISR_REG8); 633 bitdisp(r8); 634 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 635 DBG_BIT_PRINT(r8, P1READY); 636 DBG_BIT_PRINT(r8, P1MWP); 637 DBG_BIT_PRINT(r8, P1VS2); 638 DBG_BIT_PRINT(r8, P1VS1); 639 DBG_BIT_PRINT(r8, P1CD2); 640 DBG_BIT_PRINT(r8, P1CD1); 641 DBG_BIT_PRINT(r8, P1BVD2); 642 DBG_BIT_PRINT(r8, P1BVD1); 643 #undef DBG_BIT_PRINT 644 DPRINTF((TEXT("\n"))); 645 646 DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 647 r8 = reg_read_1(HD64461_PCC1GCR_REG8); 648 bitdisp(r8); 649 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 650 DBG_BIT_PRINT(r8, P1DRVE); 651 DBG_BIT_PRINT(r8, P1PCCR); 652 DBG_BIT_PRINT(r8, P1VCC0); 653 DBG_BIT_PRINT(r8, P1MMOD); 654 DBG_BIT_PRINT(r8, P1PA25); 655 DBG_BIT_PRINT(r8, P1PA24); 656 DBG_BIT_PRINT(r8, P1REG); 657 #undef DBG_BIT_PRINT 658 DPRINTF((TEXT("\n"))); 659 660 DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 661 r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 662 bitdisp(r8); 663 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 664 DBG_BIT_PRINT(r8, P1SCDI); 665 DBG_BIT_PRINT(r8, P1CDC); 666 DBG_BIT_PRINT(r8, P1RC); 667 DBG_BIT_PRINT(r8, P1BW); 668 DBG_BIT_PRINT(r8, P1BD); 669 #undef DBG_BIT_PRINT 670 DPRINTF((TEXT("\n"))); 671 672 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 673 r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 674 bitdisp(r8); 675 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 676 DBG_BIT_PRINT(r8, P1CRE); 677 DBG_BIT_PRINT(r8, P1CDE); 678 DBG_BIT_PRINT(r8, P1RE); 679 DBG_BIT_PRINT(r8, P1BWE); 680 DBG_BIT_PRINT(r8, P1BDE); 681 #undef DBG_BIT_PRINT 682 DPRINTF((TEXT("\n"))); 683 684 DPRINTF((TEXT("PCC1 Software Control Register\n"))); 685 r8 = reg_read_1(HD64461_PCC1SCR_REG8); 686 bitdisp(r8); 687 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 688 DBG_BIT_PRINT(r8, P1VCC1); 689 DBG_BIT_PRINT(r8, P1SWP); 690 #undef DBG_BIT_PRINT 691 DPRINTF((TEXT("\n"))); 692 693 // General Control 694 DPRINTF((TEXT("[General Control]\n"))); 695 DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 696 r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 697 bitdisp(r8); 698 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 699 DBG_BIT_PRINT(r8, P0DEPLUP); 700 DBG_BIT_PRINT(r8, P0AEPLUP); 701 #undef DBG_BIT_PRINT 702 DPRINTF((TEXT("\n"))); 703 704 DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 705 r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 706 bitdisp(r8); 707 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 708 DBG_BIT_PRINT(r8, P1RST8MA); 709 DBG_BIT_PRINT(r8, P1RST4MA); 710 DBG_BIT_PRINT(r8, P1RAS8MA); 711 DBG_BIT_PRINT(r8, P1RAS4MA); 712 #undef DBG_BIT_PRINT 713 DPRINTF((TEXT("\n"))); 714 715 DPRINTF((TEXT("PC Card General Control Register\n"))); 716 r8 = reg_read_1(HD64461_PCCPGCR_REG8); 717 bitdisp(r8); 718 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 719 DBG_BIT_PRINT(r8, PSSDIR); 720 DBG_BIT_PRINT(r8, PSSRDWR); 721 #undef DBG_BIT_PRINT 722 DPRINTF((TEXT("\n"))); 723 724 // GPIO 725 #define GPIO_DUMP_REG8(x) \ 726 bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 727 bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 728 bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 729 bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 730 #define GPIO_DUMP_REG16(x) \ 731 bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 732 bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 733 bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 734 bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 735 736 DPRINTF((TEXT("GPIO Port Control Register\n"))); 737 GPIO_DUMP_REG16(C); 738 DPRINTF((TEXT("GPIO Port Data Register\n"))); 739 GPIO_DUMP_REG8(D); 740 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 741 GPIO_DUMP_REG8(IC); 742 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 743 GPIO_DUMP_REG8(IS); 744 } 745 746 #ifdef SH7709TEST 747 u_int32_t sh7707_fb_dma_addr; 748 u_int16_t val; 749 int s; 750 751 s = suspendIntr(); 752 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 753 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 754 sh7707_fb_dma_addr = val; 755 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 756 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 757 sh7707_fb_dma_addr |= (val << 16); 758 resumeIntr(s); 759 760 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 761 sh7707_fb_dma_addr)); 762 #endif 763
Indexes created Sun Sep 21 20:09:37 GMT 2025