sh_arch.cpp revision 1.3
1 /* $NetBSD: sh_arch.cpp,v 1.3 2001/03/02 18:26:38 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcmenu.h> 40 #include <sh3/sh_arch.h> 41 #include <sh3/hd64461.h> 42 #include "scifreg.h" 43 44 struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 45 { "TMU0", ICU_IPRA_REG16, 12 }, 46 { "TMU1", ICU_IPRA_REG16, 8 }, 47 { "TMU2", ICU_IPRA_REG16, 4 }, 48 { "RTC", ICU_IPRA_REG16, 0 }, 49 { "WDT", ICU_IPRB_REG16, 12 }, 50 { "REF", ICU_IPRB_REG16, 8 }, 51 { "SCI", ICU_IPRB_REG16, 4 }, 52 { "reserve", ICU_IPRB_REG16, 0 }, 53 { "IRQ3", ICU_IPRC_REG16, 12 }, 54 { "IRQ2", ICU_IPRC_REG16, 8 }, 55 { "IRQ1", ICU_IPRC_REG16, 4 }, 56 { "IRQ0", ICU_IPRC_REG16, 0 }, 57 { "PINT0-7", ICU_IPRD_REG16, 12 }, 58 { "PINT8-15", ICU_IPRD_REG16, 8 }, 59 { "IRQ5", ICU_IPRD_REG16, 4 }, 60 { "IRQ4", ICU_IPRD_REG16, 0 }, 61 { "DMAC", ICU_IPRE_REG16, 12 }, 62 { "IrDA", ICU_IPRE_REG16, 8 }, 63 { "SCIF", ICU_IPRE_REG16, 4 }, 64 { "ADC", ICU_IPRE_REG16, 0 }, 65 { 0, 0, 0} /* terminator */ 66 }; 67 68 BOOL 69 SHArchitecture::init(void) 70 { 71 if (!_mem->init()) { 72 DPRINTF((TEXT("can't initialize memory manager.\n"))); 73 return FALSE; 74 } 75 // set D-RAM information 76 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 77 _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 78 79 return TRUE; 80 } 81 82 BOOL 83 SHArchitecture::setupLoader() 84 { 85 vaddr_t v; 86 87 if (!_mem->getPage(v , _loader_addr)) { 88 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 89 return FALSE; 90 } 91 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 92 (unsigned)v,(unsigned)_loader_addr)); 93 94 memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 95 DPRINTF((TEXT("2nd bootloader copy done.\n"))); 96 97 return TRUE; 98 } 99 100 void 101 SHArchitecture::jump(paddr_t info, paddr_t pvec) 102 { 103 kaddr_t sp; 104 vaddr_t v; 105 paddr_t p; 106 107 // stack for bootloader 108 _mem->getPage(v, p); 109 sp = ptokv(p + _mem->getPageSize() / 2); 110 111 info = ptokv(info); 112 pvec = ptokv(pvec); 113 _loader_addr = ptokv(_loader_addr); 114 DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 115 info, sp)); 116 117 // Change to privilege-mode. 118 SetKMode(1); 119 120 // Disable external interrupt. 121 suspendIntr(); 122 123 // Cache flush(for 2nd bootloader) 124 cache_flush(); 125 126 // jump to 2nd loader.(run P1) at this time I still use MMU. 127 __asm("mov r6, r15\n" 128 "jmp @r7\n" 129 "nop\n", info, pvec, sp, _loader_addr); 130 // NOTREACHED 131 } 132 133 // disable external interrupt and save its priority. 134 u_int32_t 135 suspendIntr(void) 136 { 137 u_int32_t sr; 138 __asm("stc sr, r0\n" 139 "mov.l r0, @r4\n" 140 "or r5, r0\n" 141 "ldc r0, sr\n", &sr, 0x000000f0); 142 return sr & 0x000000f0; 143 } 144 145 // resume external interrupt priority. 146 void 147 resumeIntr(u_int32_t s) 148 { 149 __asm("stc sr, r0\n" 150 "and r5, r0\n" 151 "or r4, r0\n" 152 "ldc r0, sr\n", s, 0xffffff0f); 153 } 154 155 void 156 SHArchitecture::print_stack_pointer(void) 157 { 158 int sp; 159 __asm("mov.l r15, @r4", &sp); 160 DPRINTF((TEXT("SP 0x%08x\n"), sp)); 161 } 162 163 void 164 SHArchitecture::systemInfo() 165 { 166 u_int32_t reg; 167 HpcMenuInterface &menu = HpcMenuInterface::Instance(); 168 169 Architecture::systemInfo(); 170 171 // check debug level. 172 if (menu._cons_parameter == 0) 173 return; 174 175 _kmode = SetKMode(1); 176 177 // Cache 178 reg = VOLATILE_REF(CCR); 179 DPRINTF((TEXT("Cache "))); 180 if (reg & CCR_CE) 181 DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 182 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 183 reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 184 reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 185 else 186 DPRINTF((TEXT("Disabled.\n"))); 187 188 // MMU 189 reg = VOLATILE_REF(MMUCR); 190 DPRINTF((TEXT("MMU "))); 191 if (reg & MMUCR_AT) 192 DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 193 reg & MMUCR_IX 194 ? TEXT("ASID + VPN") : TEXT("VPN only"), 195 reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 196 else 197 DPRINTF((TEXT("Disabled.\n"))); 198 199 // Status register 200 reg = 0; 201 __asm("stc sr, r0\n" 202 "mov.l r0, @r4", ®); 203 DPRINTF((TEXT("SR 0x%08x\n"), reg)); 204 205 // BSC 206 bsc_dump(); 207 208 // ICU 209 print_stack_pointer(); 210 icu_dump(); 211 212 // PFC , I/O port 213 pfc_dump(); 214 215 // SCIF 216 scif_dump(19200); 217 218 // HD64461 219 platid_t platform; 220 platform.dw.dw0 = menu._pref.platid_hi; 221 platform.dw.dw1 = menu._pref.platid_lo; 222 hd64461_dump(platform); 223 224 SetKMode(_kmode); 225 } 226 227 void 228 SHArchitecture::icu_dump(void) 229 { 230 DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 231 print_stack_pointer(); 232 233 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 234 DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 235 DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 236 DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 237 DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 238 DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 239 DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 240 DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 241 DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 242 DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 243 DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 244 DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 245 icu_control(); 246 icu_priority(); 247 } 248 249 void 250 SHArchitecture::icu_priority(void) 251 { 252 struct intr_priority *tab; 253 DPRINTF((TEXT("----interrupt priority----\n"))); 254 for (tab = ipr_table; tab->name; tab++) { 255 DPRINTF((TEXT("%-10S %d\n"), tab->name, 256 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 257 } 258 DPRINTF((TEXT("--------------------------\n"))); 259 } 260 261 void 262 SHArchitecture::icu_control(void) 263 { 264 const char *sense_select[] = { 265 "falling edge", 266 "raising edge", 267 "low level", 268 "reserved", 269 }; 270 u_int16_t r; 271 272 // PINT0-15 273 DPRINTF((TEXT("PINT enable(on |) :"))); 274 bitdisp(reg_read_2(ICU_PINTER_REG16)); 275 DPRINTF((TEXT("PINT detect(high |):"))); 276 bitdisp(reg_read_2(ICU_ICR2_REG16)); 277 // NMI 278 r = reg_read_2(ICU_ICR0_REG16); 279 DPRINTF((TEXT("NMI(%S %S-edge),"), 280 r & ICU_ICR0_NMIL ? "High" : "Low", 281 r & ICU_ICR0_NMIE ? "raising" : "falling")); 282 r = reg_read_2(ICU_ICR1_REG16); 283 DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 284 DPRINTF((TEXT(" SR.BL %S\n"), 285 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 286 // IRQ0-5 287 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 288 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 289 if (r & ICU_ICR1_IRQLVL) { 290 DPRINTF((TEXT("IRLS[0:3] %S\n"), 291 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 292 } 293 // sense select 294 for (int i = 5; i >= 0; i--) { 295 DPRINTF((TEXT("IRQ[%d] %S\n"), i, 296 sense_select [ 297 (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 298 } 299 } 300 301 SH_BOOT_FUNC_(7709); 302 SH_BOOT_FUNC_(7709A); 303 304 // 305 // Debug Functions. 306 // 307 void 308 SHArchitecture::bsc_dump() 309 { 310 DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 311 #define DUMP_BSC_REG(x) \ 312 DPRINTF((TEXT("%-8S"), #x)); \ 313 bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 314 DUMP_BSC_REG(BCR1); 315 DUMP_BSC_REG(BCR2); 316 DUMP_BSC_REG(WCR1); 317 DUMP_BSC_REG(WCR2); 318 DUMP_BSC_REG(MCR); 319 DUMP_BSC_REG(DCR); 320 DUMP_BSC_REG(PCR); 321 DUMP_BSC_REG(RTCSR); 322 DUMP_BSC_REG(RTCNT); 323 DUMP_BSC_REG(RTCOR); 324 DUMP_BSC_REG(RFCR); 325 DUMP_BSC_REG(BCR3); 326 #undef DUMP_BSC_REG 327 } 328 329 void 330 SHArchitecture::scif_dump(int bps) 331 { 332 u_int16_t r16; 333 u_int8_t r8; 334 int n; 335 336 DPRINTF((TEXT("<<<SCIF>>>\n"))); 337 /* mode */ 338 r8 = SHREG_SCSMR2; 339 n = 1 <<((r8 & SCSMR2_CKS) << 1); 340 DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 341 r8 & SCSMR2_CHR ? 7 : 8, 342 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 343 r8 & SCSMR2_STOP ? 2 : 1, 344 n)); 345 /* bit rate */ 346 r8 = SHREG_SCBRR2; 347 DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 348 32 * bps *(r8 + 1) * n)); 349 350 /* control */ 351 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 352 DPRINTF((TEXT("SCSCR2: "))); 353 r8 = SHREG_SCSCR2; 354 DBG_BIT_PRINT(r8, TIE); 355 DBG_BIT_PRINT(r8, RIE); 356 DBG_BIT_PRINT(r8, TE); 357 DBG_BIT_PRINT(r8, RE); 358 DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 359 #undef DBG_BIT_PRINT 360 361 /* status */ 362 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 363 r16 = SHREG_SCSSR2; 364 DPRINTF((TEXT("SCSSR2: "))); 365 DBG_BIT_PRINT(r16, ER); 366 DBG_BIT_PRINT(r16, TEND); 367 DBG_BIT_PRINT(r16, TDFE); 368 DBG_BIT_PRINT(r16, BRK); 369 DBG_BIT_PRINT(r16, FER); 370 DBG_BIT_PRINT(r16, PER); 371 DBG_BIT_PRINT(r16, RDF); 372 DBG_BIT_PRINT(r16, DR); 373 #undef DBG_BIT_PRINT 374 375 /* FIFO control */ 376 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 377 r8 = SHREG_SCFCR2; 378 DPRINTF((TEXT("SCFCR2: "))); 379 DBG_BIT_PRINT(r8, RTRG1); 380 DBG_BIT_PRINT(r8, RTRG0); 381 DBG_BIT_PRINT(r8, TTRG1); 382 DBG_BIT_PRINT(r8, TTRG0); 383 DBG_BIT_PRINT(r8, MCE); 384 DBG_BIT_PRINT(r8, TFRST); 385 DBG_BIT_PRINT(r8, RFRST); 386 DBG_BIT_PRINT(r8, LOOP); 387 DPRINTF((TEXT("\n"))); 388 #undef DBG_BIT_PRINT 389 } 390 391 void 392 SHArchitecture::pfc_dump() 393 { 394 DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 395 DPRINTF((TEXT("[control]\n"))); 396 #define DUMP_PFC_REG(x) \ 397 DPRINTF((TEXT("P%SCR :"), #x)); \ 398 bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 399 DUMP_PFC_REG(A); 400 DUMP_PFC_REG(B); 401 DUMP_PFC_REG(C); 402 DUMP_PFC_REG(D); 403 DUMP_PFC_REG(E); 404 DUMP_PFC_REG(F); 405 DUMP_PFC_REG(G); 406 DUMP_PFC_REG(H); 407 DUMP_PFC_REG(J); 408 DUMP_PFC_REG(K); 409 DUMP_PFC_REG(L); 410 #undef DUMP_PFC_REG 411 DPRINTF((TEXT("SCPCR :"))); 412 bitdisp(reg_read_2(SH3_SCPCR_REG16)); 413 DPRINTF((TEXT("\n[data]\n"))); 414 #define DUMP_IOPORT_REG(x) \ 415 DPRINTF((TEXT("P%SDR :"), #x)); \ 416 bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 417 DUMP_IOPORT_REG(A); 418 DUMP_IOPORT_REG(B); 419 DUMP_IOPORT_REG(C); 420 DUMP_IOPORT_REG(D); 421 DUMP_IOPORT_REG(E); 422 DUMP_IOPORT_REG(F); 423 DUMP_IOPORT_REG(G); 424 DUMP_IOPORT_REG(H); 425 DUMP_IOPORT_REG(J); 426 DUMP_IOPORT_REG(K); 427 DUMP_IOPORT_REG(L); 428 #undef DUMP_IOPORT_REG 429 DPRINTF((TEXT("SCPDR :"))); 430 bitdisp(reg_read_1(SH3_SCPDR_REG8)); 431 } 432 433 void 434 SHArchitecture::hd64461_dump(platid_t &platform) 435 { 436 u_int16_t r16; 437 u_int8_t r8; 438 439 #define MATCH(p) \ 440 platid_match(&platform, &platid_mask_MACH_##p) 441 442 DPRINTF((TEXT("<<<HD64461>>>\n"))); 443 if (!MATCH(HP_LX) && 444 !MATCH(HP_JORNADA_6XX) && 445 !MATCH(HITACHI_PERSONA_HPW230JC)) { 446 DPRINTF((TEXT("don't exist."))); 447 return; 448 } 449 450 #if 0 451 DPRINTF((TEXT("frame buffer test start\n"))); 452 u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 453 454 for (int i = 0; i < 320 * 240 * 2 / 8; i++) 455 *fb++ = 0xff; 456 DPRINTF((TEXT("frame buffer test end\n"))); 457 #endif 458 // System 459 DPRINTF((TEXT("STBCR (System Control Register)\n"))); 460 r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 461 bitdisp(r16); 462 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 463 DBG_BIT_PRINT(r16, CKIO_STBY); 464 DBG_BIT_PRINT(r16, SAFECKE_IST); 465 DBG_BIT_PRINT(r16, SLCKE_IST); 466 DBG_BIT_PRINT(r16, SAFECKE_OST); 467 DBG_BIT_PRINT(r16, SLCKE_OST); 468 DBG_BIT_PRINT(r16, SMIAST); 469 DBG_BIT_PRINT(r16, SLCDST); 470 DBG_BIT_PRINT(r16, SPC0ST); 471 DBG_BIT_PRINT(r16, SPC1ST); 472 DBG_BIT_PRINT(r16, SAFEST); 473 DBG_BIT_PRINT(r16, STM0ST); 474 DBG_BIT_PRINT(r16, STM1ST); 475 DBG_BIT_PRINT(r16, SIRST); 476 DBG_BIT_PRINT(r16, SURTSD); 477 #undef DBG_BIT_PRINT 478 DPRINTF((TEXT("\n"))); 479 480 DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 481 r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 482 bitdisp(r16); 483 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 484 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 485 DBG_BIT_PRINT(r16, SPTA_IR); 486 DBG_BIT_PRINT(r16, SPTA_TM); 487 DBG_BIT_PRINT(r16, SPTB_UR); 488 DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 489 DBG_BIT_PRINT(r16, SMODE1); 490 DBG_BIT_PRINT(r16, SMODE0); 491 #undef DBG_BIT_PRINT 492 DPRINTF((TEXT("\n"))); 493 494 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 495 r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 496 bitdisp(r16); 497 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 498 DBG_BIT_PRINT(r16, SPDSTOF); 499 DBG_BIT_PRINT(r16, SPDSTIG); 500 DBG_BIT_PRINT(r16, SPCSTOF); 501 DBG_BIT_PRINT(r16, SPCSTIG); 502 DBG_BIT_PRINT(r16, SPBSTOF); 503 DBG_BIT_PRINT(r16, SPBSTIG); 504 DBG_BIT_PRINT(r16, SPASTOF); 505 DBG_BIT_PRINT(r16, SPASTIG); 506 DBG_BIT_PRINT(r16, SLCDSTIG); 507 DBG_BIT_PRINT(r16, SCPU_CS56_EP); 508 DBG_BIT_PRINT(r16, SCPU_CMD_EP); 509 DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 510 DBG_BIT_PRINT(r16, SCPDPU); 511 DBG_BIT_PRINT(r16, SCPU_A2319_EP); 512 #undef DBG_BIT_PRINT 513 DPRINTF((TEXT("\n"))); 514 515 DPRINTF((TEXT("\n"))); 516 517 // INTC 518 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 519 r16 = reg_read_2(HD64461_INTCNIRR_REG16); 520 bitdisp(r16); 521 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 522 DBG_BIT_PRINT(r16, PCC0R); 523 DBG_BIT_PRINT(r16, PCC1R); 524 DBG_BIT_PRINT(r16, AFER); 525 DBG_BIT_PRINT(r16, GPIOR); 526 DBG_BIT_PRINT(r16, TMU0R); 527 DBG_BIT_PRINT(r16, TMU1R); 528 DBG_BIT_PRINT(r16, IRDAR); 529 DBG_BIT_PRINT(r16, UARTR); 530 #undef DBG_BIT_PRINT 531 DPRINTF((TEXT("\n"))); 532 533 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 534 r16 = reg_read_2(HD64461_INTCNIMR_REG16); 535 bitdisp(r16); 536 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 537 DBG_BIT_PRINT(r16, PCC0M); 538 DBG_BIT_PRINT(r16, PCC1M); 539 DBG_BIT_PRINT(r16, AFEM); 540 DBG_BIT_PRINT(r16, GPIOM); 541 DBG_BIT_PRINT(r16, TMU0M); 542 DBG_BIT_PRINT(r16, TMU1M); 543 DBG_BIT_PRINT(r16, IRDAM); 544 DBG_BIT_PRINT(r16, UARTM); 545 #undef DBG_BIT_PRINT 546 DPRINTF((TEXT("\n"))); 547 548 DPRINTF((TEXT("\n"))); 549 550 // PCMCIA 551 // PCC0 552 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 553 DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 554 r8 = reg_read_1(HD64461_PCC0ISR_REG8); 555 bitdisp(r8); 556 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 557 DBG_BIT_PRINT(r8, P0READY); 558 DBG_BIT_PRINT(r8, P0MWP); 559 DBG_BIT_PRINT(r8, P0VS2); 560 DBG_BIT_PRINT(r8, P0VS1); 561 DBG_BIT_PRINT(r8, P0CD2); 562 DBG_BIT_PRINT(r8, P0CD1); 563 DBG_BIT_PRINT(r8, P0BVD2); 564 DBG_BIT_PRINT(r8, P0BVD1); 565 #undef DBG_BIT_PRINT 566 DPRINTF((TEXT("\n"))); 567 568 DPRINTF((TEXT("PCC0 General Control Register\n"))); 569 r8 = reg_read_1(HD64461_PCC0GCR_REG8); 570 bitdisp(r8); 571 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 572 DBG_BIT_PRINT(r8, P0DRVE); 573 DBG_BIT_PRINT(r8, P0PCCR); 574 DBG_BIT_PRINT(r8, P0PCCT); 575 DBG_BIT_PRINT(r8, P0VCC0); 576 DBG_BIT_PRINT(r8, P0MMOD); 577 DBG_BIT_PRINT(r8, P0PA25); 578 DBG_BIT_PRINT(r8, P0PA24); 579 DBG_BIT_PRINT(r8, P0REG); 580 #undef DBG_BIT_PRINT 581 DPRINTF((TEXT("\n"))); 582 583 DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 584 r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 585 bitdisp(r8); 586 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 587 DBG_BIT_PRINT(r8, P0SCDI); 588 DBG_BIT_PRINT(r8, P0IREQ); 589 DBG_BIT_PRINT(r8, P0SC); 590 DBG_BIT_PRINT(r8, P0CDC); 591 DBG_BIT_PRINT(r8, P0RC); 592 DBG_BIT_PRINT(r8, P0BW); 593 DBG_BIT_PRINT(r8, P0BD); 594 #undef DBG_BIT_PRINT 595 DPRINTF((TEXT("\n"))); 596 597 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 598 r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 599 bitdisp(r8); 600 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 601 DBG_BIT_PRINT(r8, P0CRE); 602 DBG_BIT_PRINT(r8, P0SCE); 603 DBG_BIT_PRINT(r8, P0CDE); 604 DBG_BIT_PRINT(r8, P0RE); 605 DBG_BIT_PRINT(r8, P0BWE); 606 DBG_BIT_PRINT(r8, P0BDE); 607 #undef DBG_BIT_PRINT 608 DPRINTF((TEXT("\ninterrupt type: "))); 609 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 610 case HD64461_PCC0CSCIER_P0IREQE_NONE: 611 DPRINTF((TEXT("none\n"))); 612 break; 613 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 614 DPRINTF((TEXT("level\n"))); 615 break; 616 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 617 DPRINTF((TEXT("falling edge\n"))); 618 break; 619 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 620 DPRINTF((TEXT("rising edge\n"))); 621 break; 622 } 623 624 DPRINTF((TEXT("PCC0 Software Control Register\n"))); 625 r8 = reg_read_1(HD64461_PCC0SCR_REG8); 626 bitdisp(r8); 627 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 628 DBG_BIT_PRINT(r8, P0VCC1); 629 DBG_BIT_PRINT(r8, P0SWP); 630 #undef DBG_BIT_PRINT 631 DPRINTF((TEXT("\n"))); 632 633 // PCC1 634 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 635 DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 636 r8 = reg_read_1(HD64461_PCC1ISR_REG8); 637 bitdisp(r8); 638 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 639 DBG_BIT_PRINT(r8, P1READY); 640 DBG_BIT_PRINT(r8, P1MWP); 641 DBG_BIT_PRINT(r8, P1VS2); 642 DBG_BIT_PRINT(r8, P1VS1); 643 DBG_BIT_PRINT(r8, P1CD2); 644 DBG_BIT_PRINT(r8, P1CD1); 645 DBG_BIT_PRINT(r8, P1BVD2); 646 DBG_BIT_PRINT(r8, P1BVD1); 647 #undef DBG_BIT_PRINT 648 DPRINTF((TEXT("\n"))); 649 650 DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 651 r8 = reg_read_1(HD64461_PCC1GCR_REG8); 652 bitdisp(r8); 653 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 654 DBG_BIT_PRINT(r8, P1DRVE); 655 DBG_BIT_PRINT(r8, P1PCCR); 656 DBG_BIT_PRINT(r8, P1VCC0); 657 DBG_BIT_PRINT(r8, P1MMOD); 658 DBG_BIT_PRINT(r8, P1PA25); 659 DBG_BIT_PRINT(r8, P1PA24); 660 DBG_BIT_PRINT(r8, P1REG); 661 #undef DBG_BIT_PRINT 662 DPRINTF((TEXT("\n"))); 663 664 DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 665 r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 666 bitdisp(r8); 667 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 668 DBG_BIT_PRINT(r8, P1SCDI); 669 DBG_BIT_PRINT(r8, P1CDC); 670 DBG_BIT_PRINT(r8, P1RC); 671 DBG_BIT_PRINT(r8, P1BW); 672 DBG_BIT_PRINT(r8, P1BD); 673 #undef DBG_BIT_PRINT 674 DPRINTF((TEXT("\n"))); 675 676 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 677 r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 678 bitdisp(r8); 679 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 680 DBG_BIT_PRINT(r8, P1CRE); 681 DBG_BIT_PRINT(r8, P1CDE); 682 DBG_BIT_PRINT(r8, P1RE); 683 DBG_BIT_PRINT(r8, P1BWE); 684 DBG_BIT_PRINT(r8, P1BDE); 685 #undef DBG_BIT_PRINT 686 DPRINTF((TEXT("\n"))); 687 688 DPRINTF((TEXT("PCC1 Software Control Register\n"))); 689 r8 = reg_read_1(HD64461_PCC1SCR_REG8); 690 bitdisp(r8); 691 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 692 DBG_BIT_PRINT(r8, P1VCC1); 693 DBG_BIT_PRINT(r8, P1SWP); 694 #undef DBG_BIT_PRINT 695 DPRINTF((TEXT("\n"))); 696 697 // General Control 698 DPRINTF((TEXT("[General Control]\n"))); 699 DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 700 r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 701 bitdisp(r8); 702 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 703 DBG_BIT_PRINT(r8, P0DEPLUP); 704 DBG_BIT_PRINT(r8, P0AEPLUP); 705 #undef DBG_BIT_PRINT 706 DPRINTF((TEXT("\n"))); 707 708 DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 709 r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 710 bitdisp(r8); 711 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 712 DBG_BIT_PRINT(r8, P1RST8MA); 713 DBG_BIT_PRINT(r8, P1RST4MA); 714 DBG_BIT_PRINT(r8, P1RAS8MA); 715 DBG_BIT_PRINT(r8, P1RAS4MA); 716 #undef DBG_BIT_PRINT 717 DPRINTF((TEXT("\n"))); 718 719 DPRINTF((TEXT("PC Card General Control Register\n"))); 720 r8 = reg_read_1(HD64461_PCCPGCR_REG8); 721 bitdisp(r8); 722 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 723 DBG_BIT_PRINT(r8, PSSDIR); 724 DBG_BIT_PRINT(r8, PSSRDWR); 725 #undef DBG_BIT_PRINT 726 DPRINTF((TEXT("\n"))); 727 728 // GPIO 729 #define GPIO_DUMP_REG8(x) \ 730 bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 731 bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 732 bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 733 bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 734 #define GPIO_DUMP_REG16(x) \ 735 bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 736 bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 737 bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 738 bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 739 740 DPRINTF((TEXT("GPIO Port Control Register\n"))); 741 GPIO_DUMP_REG16(C); 742 DPRINTF((TEXT("GPIO Port Data Register\n"))); 743 GPIO_DUMP_REG8(D); 744 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 745 GPIO_DUMP_REG8(IC); 746 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 747 GPIO_DUMP_REG8(IS); 748 } 749 750 #ifdef SH7709TEST 751 u_int32_t sh7707_fb_dma_addr; 752 u_int16_t val; 753 int s; 754 755 s = suspendIntr(); 756 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 757 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 758 sh7707_fb_dma_addr = val; 759 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 760 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 761 sh7707_fb_dma_addr |= (val << 16); 762 resumeIntr(s); 763 764 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 765 sh7707_fb_dma_addr)); 766 #endif 767
Indexes created Tue Sep 23 07:09:52 GMT 2025