sh_arch.cpp revision 1.4
1 /* $NetBSD: sh_arch.cpp,v 1.4 2001/03/22 18:27:51 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcmenu.h> 40 #include <sh3/sh_arch.h> 41 #include <sh3/hd64461.h> 42 #include "scifreg.h" 43 44 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); 45 46 struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 47 { "TMU0", ICU_IPRA_REG16, 12 }, 48 { "TMU1", ICU_IPRA_REG16, 8 }, 49 { "TMU2", ICU_IPRA_REG16, 4 }, 50 { "RTC", ICU_IPRA_REG16, 0 }, 51 { "WDT", ICU_IPRB_REG16, 12 }, 52 { "REF", ICU_IPRB_REG16, 8 }, 53 { "SCI", ICU_IPRB_REG16, 4 }, 54 { "reserve", ICU_IPRB_REG16, 0 }, 55 { "IRQ3", ICU_IPRC_REG16, 12 }, 56 { "IRQ2", ICU_IPRC_REG16, 8 }, 57 { "IRQ1", ICU_IPRC_REG16, 4 }, 58 { "IRQ0", ICU_IPRC_REG16, 0 }, 59 { "PINT0-7", ICU_IPRD_REG16, 12 }, 60 { "PINT8-15", ICU_IPRD_REG16, 8 }, 61 { "IRQ5", ICU_IPRD_REG16, 4 }, 62 { "IRQ4", ICU_IPRD_REG16, 0 }, 63 { "DMAC", ICU_IPRE_REG16, 12 }, 64 { "IrDA", ICU_IPRE_REG16, 8 }, 65 { "SCIF", ICU_IPRE_REG16, 4 }, 66 { "ADC", ICU_IPRE_REG16, 0 }, 67 { 0, 0, 0} /* terminator */ 68 }; 69 70 BOOL 71 SHArchitecture::init(void) 72 { 73 if (!_mem->init()) { 74 DPRINTF((TEXT("can't initialize memory manager.\n"))); 75 return FALSE; 76 } 77 // set D-RAM information 78 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 79 _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 80 81 return TRUE; 82 } 83 84 BOOL 85 SHArchitecture::setupLoader() 86 { 87 vaddr_t v; 88 89 if (!_mem->getPage(v , _loader_addr)) { 90 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 91 return FALSE; 92 } 93 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 94 (unsigned)v,(unsigned)_loader_addr)); 95 96 memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 97 DPRINTF((TEXT("2nd bootloader copy done.\n"))); 98 99 return TRUE; 100 } 101 102 void 103 SHArchitecture::jump(paddr_t info, paddr_t pvec) 104 { 105 kaddr_t sp; 106 vaddr_t v; 107 paddr_t p; 108 109 // stack for bootloader 110 _mem->getPage(v, p); 111 sp = ptokv(p + _mem->getPageSize() / 2); 112 113 info = ptokv(info); 114 pvec = ptokv(pvec); 115 _loader_addr = ptokv(_loader_addr); 116 DPRINTF((TEXT("BootArgs 0x%08x Stack 0x%08x\nBooting kernel...\n"), 117 info, sp)); 118 119 // Change to privilege-mode. 120 SetKMode(1); 121 122 // Disable external interrupt. 123 suspendIntr(); 124 125 // Cache flush(for 2nd bootloader) 126 cache_flush(); 127 128 // jump to 2nd loader.(run P1) at this time I still use MMU. 129 __asm("mov r6, r15\n" 130 "jmp @r7\n" 131 "nop\n", info, pvec, sp, _loader_addr); 132 // NOTREACHED 133 } 134 135 // disable external interrupt and save its priority. 136 u_int32_t 137 suspendIntr(void) 138 { 139 u_int32_t sr; 140 __asm("stc sr, r0\n" 141 "mov.l r0, @r4\n" 142 "or r5, r0\n" 143 "ldc r0, sr\n", &sr, 0x000000f0); 144 return sr & 0x000000f0; 145 } 146 147 // resume external interrupt priority. 148 void 149 resumeIntr(u_int32_t s) 150 { 151 __asm("stc sr, r0\n" 152 "and r5, r0\n" 153 "or r4, r0\n" 154 "ldc r0, sr\n", s, 0xffffff0f); 155 } 156 157 void 158 SHArchitecture::print_stack_pointer(void) 159 { 160 int sp; 161 __asm("mov.l r15, @r4", &sp); 162 DPRINTF((TEXT("SP 0x%08x\n"), sp)); 163 } 164 165 void 166 SHArchitecture::systemInfo() 167 { 168 u_int32_t reg; 169 HpcMenuInterface &menu = HpcMenuInterface::Instance(); 170 171 Architecture::systemInfo(); 172 173 // check debug level. 174 if (menu._cons_parameter == 0) 175 return; 176 177 _kmode = SetKMode(1); 178 179 // Cache 180 reg = VOLATILE_REF(CCR); 181 DPRINTF((TEXT("Cache "))); 182 if (reg & CCR_CE) 183 DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 184 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 185 reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 186 reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 187 else 188 DPRINTF((TEXT("Disabled.\n"))); 189 190 // MMU 191 reg = VOLATILE_REF(MMUCR); 192 DPRINTF((TEXT("MMU "))); 193 if (reg & MMUCR_AT) 194 DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 195 reg & MMUCR_IX 196 ? TEXT("ASID + VPN") : TEXT("VPN only"), 197 reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 198 else 199 DPRINTF((TEXT("Disabled.\n"))); 200 201 // Status register 202 reg = 0; 203 __asm("stc sr, r0\n" 204 "mov.l r0, @r4", ®); 205 DPRINTF((TEXT("SR 0x%08x\n"), reg)); 206 207 // BSC 208 bsc_dump(); 209 210 // ICU 211 print_stack_pointer(); 212 icu_dump(); 213 214 // TMU 215 tmu_dump(); 216 217 // PFC , I/O port 218 pfc_dump(); 219 220 // SCIF 221 scif_dump(19200); 222 223 // HD64461 224 platid_t platform; 225 platform.dw.dw0 = menu._pref.platid_hi; 226 platform.dw.dw1 = menu._pref.platid_lo; 227 hd64461_dump(platform); 228 229 SetKMode(_kmode); 230 } 231 232 void 233 SHArchitecture::icu_dump(void) 234 { 235 DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 236 print_stack_pointer(); 237 238 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 239 DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 240 DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 241 DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 242 DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 243 DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 244 DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 245 DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 246 DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 247 DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 248 DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 249 DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 250 icu_control(); 251 icu_priority(); 252 } 253 254 void 255 SHArchitecture::icu_priority(void) 256 { 257 struct intr_priority *tab; 258 DPRINTF((TEXT("----interrupt priority----\n"))); 259 for (tab = ipr_table; tab->name; tab++) { 260 DPRINTF((TEXT("%-10S %d\n"), tab->name, 261 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 262 } 263 DPRINTF((TEXT("--------------------------\n"))); 264 } 265 266 void 267 SHArchitecture::icu_control(void) 268 { 269 const char *sense_select[] = { 270 "falling edge", 271 "raising edge", 272 "low level", 273 "reserved", 274 }; 275 u_int16_t r; 276 277 // PINT0-15 278 DPRINTF((TEXT("PINT enable(on |) :"))); 279 bitdisp(reg_read_2(ICU_PINTER_REG16)); 280 DPRINTF((TEXT("PINT detect(high |):"))); 281 bitdisp(reg_read_2(ICU_ICR2_REG16)); 282 // NMI 283 r = reg_read_2(ICU_ICR0_REG16); 284 DPRINTF((TEXT("NMI(%S %S-edge),"), 285 r & ICU_ICR0_NMIL ? "High" : "Low", 286 r & ICU_ICR0_NMIE ? "raising" : "falling")); 287 r = reg_read_2(ICU_ICR1_REG16); 288 DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 289 DPRINTF((TEXT(" SR.BL %S\n"), 290 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 291 // IRQ0-5 292 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 293 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 294 if (r & ICU_ICR1_IRQLVL) { 295 DPRINTF((TEXT("IRLS[0:3] %S\n"), 296 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 297 } 298 // sense select 299 for (int i = 5; i >= 0; i--) { 300 DPRINTF((TEXT("IRQ[%d] %S\n"), i, 301 sense_select [ 302 (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 303 } 304 } 305 306 SH_BOOT_FUNC_(7709); 307 SH_BOOT_FUNC_(7709A); 308 309 // 310 // Debug Functions. 311 // 312 void 313 SHArchitecture::bsc_dump() 314 { 315 DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 316 #define DUMP_BSC_REG(x) \ 317 DPRINTF((TEXT("%-8S"), #x)); \ 318 bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 319 DUMP_BSC_REG(BCR1); 320 DUMP_BSC_REG(BCR2); 321 DUMP_BSC_REG(WCR1); 322 DUMP_BSC_REG(WCR2); 323 DUMP_BSC_REG(MCR); 324 DUMP_BSC_REG(DCR); 325 DUMP_BSC_REG(PCR); 326 DUMP_BSC_REG(RTCSR); 327 DUMP_BSC_REG(RTCNT); 328 DUMP_BSC_REG(RTCOR); 329 DUMP_BSC_REG(RFCR); 330 DUMP_BSC_REG(BCR3); 331 #undef DUMP_BSC_REG 332 } 333 334 void 335 SHArchitecture::scif_dump(int bps) 336 { 337 u_int16_t r16; 338 u_int8_t r8; 339 int n; 340 341 DPRINTF((TEXT("<<<SCIF>>>\n"))); 342 /* mode */ 343 r8 = SHREG_SCSMR2; 344 n = 1 <<((r8 & SCSMR2_CKS) << 1); 345 DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 346 r8 & SCSMR2_CHR ? 7 : 8, 347 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 348 r8 & SCSMR2_STOP ? 2 : 1, 349 n)); 350 /* bit rate */ 351 r8 = SHREG_SCBRR2; 352 DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 353 32 * bps *(r8 + 1) * n)); 354 355 /* control */ 356 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 357 DPRINTF((TEXT("SCSCR2: "))); 358 r8 = SHREG_SCSCR2; 359 DBG_BIT_PRINT(r8, TIE); 360 DBG_BIT_PRINT(r8, RIE); 361 DBG_BIT_PRINT(r8, TE); 362 DBG_BIT_PRINT(r8, RE); 363 DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 364 #undef DBG_BIT_PRINT 365 366 /* status */ 367 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 368 r16 = SHREG_SCSSR2; 369 DPRINTF((TEXT("SCSSR2: "))); 370 DBG_BIT_PRINT(r16, ER); 371 DBG_BIT_PRINT(r16, TEND); 372 DBG_BIT_PRINT(r16, TDFE); 373 DBG_BIT_PRINT(r16, BRK); 374 DBG_BIT_PRINT(r16, FER); 375 DBG_BIT_PRINT(r16, PER); 376 DBG_BIT_PRINT(r16, RDF); 377 DBG_BIT_PRINT(r16, DR); 378 #undef DBG_BIT_PRINT 379 380 /* FIFO control */ 381 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 382 r8 = SHREG_SCFCR2; 383 DPRINTF((TEXT("SCFCR2: "))); 384 DBG_BIT_PRINT(r8, RTRG1); 385 DBG_BIT_PRINT(r8, RTRG0); 386 DBG_BIT_PRINT(r8, TTRG1); 387 DBG_BIT_PRINT(r8, TTRG0); 388 DBG_BIT_PRINT(r8, MCE); 389 DBG_BIT_PRINT(r8, TFRST); 390 DBG_BIT_PRINT(r8, RFRST); 391 DBG_BIT_PRINT(r8, LOOP); 392 DPRINTF((TEXT("\n"))); 393 #undef DBG_BIT_PRINT 394 } 395 396 void 397 SHArchitecture::pfc_dump() 398 { 399 DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 400 DPRINTF((TEXT("[control]\n"))); 401 #define DUMP_PFC_REG(x) \ 402 DPRINTF((TEXT("P%SCR :"), #x)); \ 403 bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 404 DUMP_PFC_REG(A); 405 DUMP_PFC_REG(B); 406 DUMP_PFC_REG(C); 407 DUMP_PFC_REG(D); 408 DUMP_PFC_REG(E); 409 DUMP_PFC_REG(F); 410 DUMP_PFC_REG(G); 411 DUMP_PFC_REG(H); 412 DUMP_PFC_REG(J); 413 DUMP_PFC_REG(K); 414 DUMP_PFC_REG(L); 415 #undef DUMP_PFC_REG 416 DPRINTF((TEXT("SCPCR :"))); 417 bitdisp(reg_read_2(SH3_SCPCR_REG16)); 418 DPRINTF((TEXT("\n[data]\n"))); 419 #define DUMP_IOPORT_REG(x) \ 420 DPRINTF((TEXT("P%SDR :"), #x)); \ 421 bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 422 DUMP_IOPORT_REG(A); 423 DUMP_IOPORT_REG(B); 424 DUMP_IOPORT_REG(C); 425 DUMP_IOPORT_REG(D); 426 DUMP_IOPORT_REG(E); 427 DUMP_IOPORT_REG(F); 428 DUMP_IOPORT_REG(G); 429 DUMP_IOPORT_REG(H); 430 DUMP_IOPORT_REG(J); 431 DUMP_IOPORT_REG(K); 432 DUMP_IOPORT_REG(L); 433 #undef DUMP_IOPORT_REG 434 DPRINTF((TEXT("SCPDR :"))); 435 bitdisp(reg_read_1(SH3_SCPDR_REG8)); 436 } 437 438 void 439 SHArchitecture::tmu_dump() 440 { 441 u_int8_t r8; 442 443 DPRINTF((TEXT("<<<TMU>>>\n"))); 444 /* Common */ 445 /* TOCR timer output control register */ 446 r8 = reg_read_1(SH3_TOCR_REG8); 447 DPRINTF((TEXT("TCLK = %S\n"), 448 r8 & TOCR_TCOE ? "RTC output" : "input")); 449 /* TSTR */ 450 r8 = reg_read_1(SH3_TSTR_REG8); 451 DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), 452 r8 & TSTR_STR0 ? 'x' : '_', 453 r8 & TSTR_STR1 ? 'x' : '_', 454 r8 & TSTR_STR2 ? 'x' : '_')); 455 456 #define CHANNEL_DUMP(a, x) \ 457 tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ 458 SH##a##_TCNT##x##_REG, \ 459 SH##a##_TCR##x##_REG16) 460 CHANNEL_DUMP(3, 0); 461 CHANNEL_DUMP(3, 1); 462 CHANNEL_DUMP(3, 2); 463 #undef CHANNEL_DUMP 464 DPRINTF((TEXT("\n"))); 465 } 466 467 void 468 SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, 469 paddr_t tcr) 470 { 471 u_int32_t r32; 472 u_int16_t r16; 473 474 DPRINTF((TEXT("TMU#%d:"), unit)); 475 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) 476 /* TCR*/ 477 r16 = reg_read_2(tcr); 478 DBG_BIT_PRINT(r16, UNF); 479 DBG_BIT_PRINT(r16, UNIE); 480 DBG_BIT_PRINT(r16, CKEG1); 481 DBG_BIT_PRINT(r16, CKEG0); 482 DBG_BIT_PRINT(r16, TPSC2); 483 DBG_BIT_PRINT(r16, TPSC1); 484 DBG_BIT_PRINT(r16, TPSC0); 485 /* channel 2 has input capture. */ 486 if (unit == 2) { 487 DBG_BIT_PRINT(r16, ICPF); 488 DBG_BIT_PRINT(r16, ICPE1); 489 DBG_BIT_PRINT(r16, ICPE0); 490 } 491 #undef DBG_BIT_PRINT 492 /* TCNT0 timer counter */ 493 r32 = reg_read_4(tcnt); 494 DPRINTF((TEXT("\ncnt=0x%08x"), r32)); 495 /* TCOR0 timer constant register */ 496 r32 = reg_read_4(tcor); 497 DPRINTF((TEXT(" constant=0x%04x"), r32)); 498 499 if (unit == 2) 500 DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); 501 else 502 DPRINTF((TEXT("\n"))); 503 } 504 505 void 506 SHArchitecture::hd64461_dump(platid_t &platform) 507 { 508 u_int16_t r16; 509 u_int8_t r8; 510 511 #define MATCH(p) \ 512 platid_match(&platform, &platid_mask_MACH_##p) 513 514 DPRINTF((TEXT("<<<HD64461>>>\n"))); 515 if (!MATCH(HP_LX) && 516 !MATCH(HP_JORNADA_6XX) && 517 !MATCH(HITACHI_PERSONA_HPW230JC)) { 518 DPRINTF((TEXT("don't exist."))); 519 return; 520 } 521 522 #if 0 523 DPRINTF((TEXT("frame buffer test start\n"))); 524 u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 525 526 for (int i = 0; i < 320 * 240 * 2 / 8; i++) 527 *fb++ = 0xff; 528 DPRINTF((TEXT("frame buffer test end\n"))); 529 #endif 530 // System 531 DPRINTF((TEXT("STBCR (System Control Register)\n"))); 532 r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 533 bitdisp(r16); 534 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 535 DBG_BIT_PRINT(r16, CKIO_STBY); 536 DBG_BIT_PRINT(r16, SAFECKE_IST); 537 DBG_BIT_PRINT(r16, SLCKE_IST); 538 DBG_BIT_PRINT(r16, SAFECKE_OST); 539 DBG_BIT_PRINT(r16, SLCKE_OST); 540 DBG_BIT_PRINT(r16, SMIAST); 541 DBG_BIT_PRINT(r16, SLCDST); 542 DBG_BIT_PRINT(r16, SPC0ST); 543 DBG_BIT_PRINT(r16, SPC1ST); 544 DBG_BIT_PRINT(r16, SAFEST); 545 DBG_BIT_PRINT(r16, STM0ST); 546 DBG_BIT_PRINT(r16, STM1ST); 547 DBG_BIT_PRINT(r16, SIRST); 548 DBG_BIT_PRINT(r16, SURTSD); 549 #undef DBG_BIT_PRINT 550 DPRINTF((TEXT("\n"))); 551 552 DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 553 r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 554 bitdisp(r16); 555 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 556 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 557 DBG_BIT_PRINT(r16, SPTA_IR); 558 DBG_BIT_PRINT(r16, SPTA_TM); 559 DBG_BIT_PRINT(r16, SPTB_UR); 560 DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 561 DBG_BIT_PRINT(r16, SMODE1); 562 DBG_BIT_PRINT(r16, SMODE0); 563 #undef DBG_BIT_PRINT 564 DPRINTF((TEXT("\n"))); 565 566 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 567 r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 568 bitdisp(r16); 569 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 570 DBG_BIT_PRINT(r16, SPDSTOF); 571 DBG_BIT_PRINT(r16, SPDSTIG); 572 DBG_BIT_PRINT(r16, SPCSTOF); 573 DBG_BIT_PRINT(r16, SPCSTIG); 574 DBG_BIT_PRINT(r16, SPBSTOF); 575 DBG_BIT_PRINT(r16, SPBSTIG); 576 DBG_BIT_PRINT(r16, SPASTOF); 577 DBG_BIT_PRINT(r16, SPASTIG); 578 DBG_BIT_PRINT(r16, SLCDSTIG); 579 DBG_BIT_PRINT(r16, SCPU_CS56_EP); 580 DBG_BIT_PRINT(r16, SCPU_CMD_EP); 581 DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 582 DBG_BIT_PRINT(r16, SCPDPU); 583 DBG_BIT_PRINT(r16, SCPU_A2319_EP); 584 #undef DBG_BIT_PRINT 585 DPRINTF((TEXT("\n"))); 586 587 DPRINTF((TEXT("\n"))); 588 589 // INTC 590 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 591 r16 = reg_read_2(HD64461_INTCNIRR_REG16); 592 bitdisp(r16); 593 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 594 DBG_BIT_PRINT(r16, PCC0R); 595 DBG_BIT_PRINT(r16, PCC1R); 596 DBG_BIT_PRINT(r16, AFER); 597 DBG_BIT_PRINT(r16, GPIOR); 598 DBG_BIT_PRINT(r16, TMU0R); 599 DBG_BIT_PRINT(r16, TMU1R); 600 DBG_BIT_PRINT(r16, IRDAR); 601 DBG_BIT_PRINT(r16, UARTR); 602 #undef DBG_BIT_PRINT 603 DPRINTF((TEXT("\n"))); 604 605 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 606 r16 = reg_read_2(HD64461_INTCNIMR_REG16); 607 bitdisp(r16); 608 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 609 DBG_BIT_PRINT(r16, PCC0M); 610 DBG_BIT_PRINT(r16, PCC1M); 611 DBG_BIT_PRINT(r16, AFEM); 612 DBG_BIT_PRINT(r16, GPIOM); 613 DBG_BIT_PRINT(r16, TMU0M); 614 DBG_BIT_PRINT(r16, TMU1M); 615 DBG_BIT_PRINT(r16, IRDAM); 616 DBG_BIT_PRINT(r16, UARTM); 617 #undef DBG_BIT_PRINT 618 DPRINTF((TEXT("\n"))); 619 620 DPRINTF((TEXT("\n"))); 621 622 // PCMCIA 623 // PCC0 624 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 625 DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 626 r8 = reg_read_1(HD64461_PCC0ISR_REG8); 627 bitdisp(r8); 628 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 629 DBG_BIT_PRINT(r8, P0READY); 630 DBG_BIT_PRINT(r8, P0MWP); 631 DBG_BIT_PRINT(r8, P0VS2); 632 DBG_BIT_PRINT(r8, P0VS1); 633 DBG_BIT_PRINT(r8, P0CD2); 634 DBG_BIT_PRINT(r8, P0CD1); 635 DBG_BIT_PRINT(r8, P0BVD2); 636 DBG_BIT_PRINT(r8, P0BVD1); 637 #undef DBG_BIT_PRINT 638 DPRINTF((TEXT("\n"))); 639 640 DPRINTF((TEXT("PCC0 General Control Register\n"))); 641 r8 = reg_read_1(HD64461_PCC0GCR_REG8); 642 bitdisp(r8); 643 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 644 DBG_BIT_PRINT(r8, P0DRVE); 645 DBG_BIT_PRINT(r8, P0PCCR); 646 DBG_BIT_PRINT(r8, P0PCCT); 647 DBG_BIT_PRINT(r8, P0VCC0); 648 DBG_BIT_PRINT(r8, P0MMOD); 649 DBG_BIT_PRINT(r8, P0PA25); 650 DBG_BIT_PRINT(r8, P0PA24); 651 DBG_BIT_PRINT(r8, P0REG); 652 #undef DBG_BIT_PRINT 653 DPRINTF((TEXT("\n"))); 654 655 DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 656 r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 657 bitdisp(r8); 658 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 659 DBG_BIT_PRINT(r8, P0SCDI); 660 DBG_BIT_PRINT(r8, P0IREQ); 661 DBG_BIT_PRINT(r8, P0SC); 662 DBG_BIT_PRINT(r8, P0CDC); 663 DBG_BIT_PRINT(r8, P0RC); 664 DBG_BIT_PRINT(r8, P0BW); 665 DBG_BIT_PRINT(r8, P0BD); 666 #undef DBG_BIT_PRINT 667 DPRINTF((TEXT("\n"))); 668 669 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 670 r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 671 bitdisp(r8); 672 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 673 DBG_BIT_PRINT(r8, P0CRE); 674 DBG_BIT_PRINT(r8, P0SCE); 675 DBG_BIT_PRINT(r8, P0CDE); 676 DBG_BIT_PRINT(r8, P0RE); 677 DBG_BIT_PRINT(r8, P0BWE); 678 DBG_BIT_PRINT(r8, P0BDE); 679 #undef DBG_BIT_PRINT 680 DPRINTF((TEXT("\ninterrupt type: "))); 681 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 682 case HD64461_PCC0CSCIER_P0IREQE_NONE: 683 DPRINTF((TEXT("none\n"))); 684 break; 685 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 686 DPRINTF((TEXT("level\n"))); 687 break; 688 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 689 DPRINTF((TEXT("falling edge\n"))); 690 break; 691 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 692 DPRINTF((TEXT("rising edge\n"))); 693 break; 694 } 695 696 DPRINTF((TEXT("PCC0 Software Control Register\n"))); 697 r8 = reg_read_1(HD64461_PCC0SCR_REG8); 698 bitdisp(r8); 699 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 700 DBG_BIT_PRINT(r8, P0VCC1); 701 DBG_BIT_PRINT(r8, P0SWP); 702 #undef DBG_BIT_PRINT 703 DPRINTF((TEXT("\n"))); 704 705 // PCC1 706 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 707 DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 708 r8 = reg_read_1(HD64461_PCC1ISR_REG8); 709 bitdisp(r8); 710 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 711 DBG_BIT_PRINT(r8, P1READY); 712 DBG_BIT_PRINT(r8, P1MWP); 713 DBG_BIT_PRINT(r8, P1VS2); 714 DBG_BIT_PRINT(r8, P1VS1); 715 DBG_BIT_PRINT(r8, P1CD2); 716 DBG_BIT_PRINT(r8, P1CD1); 717 DBG_BIT_PRINT(r8, P1BVD2); 718 DBG_BIT_PRINT(r8, P1BVD1); 719 #undef DBG_BIT_PRINT 720 DPRINTF((TEXT("\n"))); 721 722 DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 723 r8 = reg_read_1(HD64461_PCC1GCR_REG8); 724 bitdisp(r8); 725 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 726 DBG_BIT_PRINT(r8, P1DRVE); 727 DBG_BIT_PRINT(r8, P1PCCR); 728 DBG_BIT_PRINT(r8, P1VCC0); 729 DBG_BIT_PRINT(r8, P1MMOD); 730 DBG_BIT_PRINT(r8, P1PA25); 731 DBG_BIT_PRINT(r8, P1PA24); 732 DBG_BIT_PRINT(r8, P1REG); 733 #undef DBG_BIT_PRINT 734 DPRINTF((TEXT("\n"))); 735 736 DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 737 r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 738 bitdisp(r8); 739 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 740 DBG_BIT_PRINT(r8, P1SCDI); 741 DBG_BIT_PRINT(r8, P1CDC); 742 DBG_BIT_PRINT(r8, P1RC); 743 DBG_BIT_PRINT(r8, P1BW); 744 DBG_BIT_PRINT(r8, P1BD); 745 #undef DBG_BIT_PRINT 746 DPRINTF((TEXT("\n"))); 747 748 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 749 r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 750 bitdisp(r8); 751 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 752 DBG_BIT_PRINT(r8, P1CRE); 753 DBG_BIT_PRINT(r8, P1CDE); 754 DBG_BIT_PRINT(r8, P1RE); 755 DBG_BIT_PRINT(r8, P1BWE); 756 DBG_BIT_PRINT(r8, P1BDE); 757 #undef DBG_BIT_PRINT 758 DPRINTF((TEXT("\n"))); 759 760 DPRINTF((TEXT("PCC1 Software Control Register\n"))); 761 r8 = reg_read_1(HD64461_PCC1SCR_REG8); 762 bitdisp(r8); 763 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 764 DBG_BIT_PRINT(r8, P1VCC1); 765 DBG_BIT_PRINT(r8, P1SWP); 766 #undef DBG_BIT_PRINT 767 DPRINTF((TEXT("\n"))); 768 769 // General Control 770 DPRINTF((TEXT("[General Control]\n"))); 771 DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 772 r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 773 bitdisp(r8); 774 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 775 DBG_BIT_PRINT(r8, P0DEPLUP); 776 DBG_BIT_PRINT(r8, P0AEPLUP); 777 #undef DBG_BIT_PRINT 778 DPRINTF((TEXT("\n"))); 779 780 DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 781 r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 782 bitdisp(r8); 783 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 784 DBG_BIT_PRINT(r8, P1RST8MA); 785 DBG_BIT_PRINT(r8, P1RST4MA); 786 DBG_BIT_PRINT(r8, P1RAS8MA); 787 DBG_BIT_PRINT(r8, P1RAS4MA); 788 #undef DBG_BIT_PRINT 789 DPRINTF((TEXT("\n"))); 790 791 DPRINTF((TEXT("PC Card General Control Register\n"))); 792 r8 = reg_read_1(HD64461_PCCPGCR_REG8); 793 bitdisp(r8); 794 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 795 DBG_BIT_PRINT(r8, PSSDIR); 796 DBG_BIT_PRINT(r8, PSSRDWR); 797 #undef DBG_BIT_PRINT 798 DPRINTF((TEXT("\n"))); 799 800 // GPIO 801 #define GPIO_DUMP_REG8(x) \ 802 bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 803 bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 804 bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 805 bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 806 #define GPIO_DUMP_REG16(x) \ 807 bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 808 bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 809 bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 810 bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 811 812 DPRINTF((TEXT("GPIO Port Control Register\n"))); 813 GPIO_DUMP_REG16(C); 814 DPRINTF((TEXT("GPIO Port Data Register\n"))); 815 GPIO_DUMP_REG8(D); 816 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 817 GPIO_DUMP_REG8(IC); 818 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 819 GPIO_DUMP_REG8(IS); 820 } 821 822 #ifdef SH7709TEST 823 u_int32_t sh7707_fb_dma_addr; 824 u_int16_t val; 825 int s; 826 827 s = suspendIntr(); 828 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 829 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 830 sh7707_fb_dma_addr = val; 831 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 832 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 833 sh7707_fb_dma_addr |= (val << 16); 834 resumeIntr(s); 835 836 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 837 sh7707_fb_dma_addr)); 838 #endif 839
Indexes created Tue Sep 23 14:10:03 GMT 2025