sh_arch.cpp revision 1.7.2.1
1 /* $NetBSD: sh_arch.cpp,v 1.7.2.1 2002/02/11 20:08:00 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <hpcboot.h> 40 #include <hpcmenu.h> 41 #include <sh3/sh_arch.h> 42 #include <sh3/hd64461.h> 43 #include <sh3/hd64465.h> 44 #include "scifreg.h" 45 46 static void __tmu_channel_info(int, paddr_t, paddr_t, paddr_t); 47 48 struct SHArchitecture::intr_priority SHArchitecture::ipr_table[] = { 49 { "TMU0", ICU_IPRA_REG16, 12 }, 50 { "TMU1", ICU_IPRA_REG16, 8 }, 51 { "TMU2", ICU_IPRA_REG16, 4 }, 52 { "RTC", ICU_IPRA_REG16, 0 }, 53 { "WDT", ICU_IPRB_REG16, 12 }, 54 { "REF", ICU_IPRB_REG16, 8 }, 55 { "SCI", ICU_IPRB_REG16, 4 }, 56 { "reserve", ICU_IPRB_REG16, 0 }, 57 { "IRQ3", ICU_IPRC_REG16, 12 }, 58 { "IRQ2", ICU_IPRC_REG16, 8 }, 59 { "IRQ1", ICU_IPRC_REG16, 4 }, 60 { "IRQ0", ICU_IPRC_REG16, 0 }, 61 { "PINT0-7", ICU_IPRD_REG16, 12 }, 62 { "PINT8-15", ICU_IPRD_REG16, 8 }, 63 { "IRQ5", ICU_IPRD_REG16, 4 }, 64 { "IRQ4", ICU_IPRD_REG16, 0 }, 65 { "DMAC", ICU_IPRE_REG16, 12 }, 66 { "IrDA", ICU_IPRE_REG16, 8 }, 67 { "SCIF", ICU_IPRE_REG16, 4 }, 68 { "ADC", ICU_IPRE_REG16, 0 }, 69 { 0, 0, 0} /* terminator */ 70 }; 71 72 BOOL 73 SHArchitecture::init(void) 74 { 75 76 if (!_mem->init()) { 77 DPRINTF((TEXT("can't initialize memory manager.\n"))); 78 return FALSE; 79 } 80 // set D-RAM information 81 DPRINTF((TEXT("Memory Bank:\n"))); 82 _mem->loadBank(DRAM_BANK0_START, DRAM_BANK_SIZE); 83 _mem->loadBank(DRAM_BANK1_START, DRAM_BANK_SIZE); 84 85 return TRUE; 86 } 87 88 BOOL 89 SHArchitecture::setupLoader() 90 { 91 vaddr_t v; 92 93 if (!_mem->getPage(v , _loader_addr)) { 94 DPRINTF((TEXT("can't get page for 2nd loader.\n"))); 95 return FALSE; 96 } 97 DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"), 98 (unsigned)v,(unsigned)_loader_addr)); 99 100 memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize()); 101 102 return TRUE; 103 } 104 105 void 106 SHArchitecture::jump(paddr_t info, paddr_t pvec) 107 { 108 kaddr_t sp; 109 vaddr_t v; 110 paddr_t p; 111 112 // stack for bootloader 113 _mem->getPage(v, p); 114 sp = ptokv(p + _mem->getPageSize() / 2); 115 116 info = ptokv(info); 117 pvec = ptokv(pvec); 118 _loader_addr = ptokv(_loader_addr); 119 DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"), 120 info, sp)); 121 122 // Change to privilege-mode. 123 SetKMode(1); 124 125 // Cache flush(for 2nd bootloader) 126 // 127 // SH4 uses WinCE CacheSync(). this routine may causes TLB 128 // exception. so calls before suspendIntr(). 129 // 130 cache_flush(); 131 132 // Disable external interrupt. 133 suspendIntr(); 134 135 // jump to 2nd loader.(run P1) at this time I still use MMU. 136 __asm( 137 "mov r6, r15\n" 138 "jmp @r7\n" 139 "nop \n", info, pvec, sp, _loader_addr); 140 // NOTREACHED 141 } 142 143 // disable external interrupt and save its priority. 144 u_int32_t 145 suspendIntr(void) 146 { 147 u_int32_t sr; 148 149 __asm( 150 "stc sr, r0\n" 151 "mov.l r0, @r4\n" 152 "or r5, r0\n" 153 "ldc r0, sr\n", &sr, 0x000000f0); 154 return sr & 0x000000f0; 155 } 156 157 // resume external interrupt priority. 158 void 159 resumeIntr(u_int32_t s) 160 { 161 162 __asm("stc sr, r0\n" 163 "and r5, r0\n" 164 "or r4, r0\n" 165 "ldc r0, sr\n", s, 0xffffff0f); 166 } 167 168 void 169 SHArchitecture::print_stack_pointer(void) 170 { 171 int sp; 172 173 __asm("mov.l r15, @r4", &sp); 174 DPRINTF((TEXT("SP 0x%08x\n"), sp)); 175 } 176 177 void 178 SHArchitecture::systemInfo() 179 { 180 u_int32_t reg; 181 HpcMenuInterface &menu = HpcMenuInterface::Instance(); 182 183 Architecture::systemInfo(); 184 185 // check debug level. 186 if (menu._cons_parameter == 0) 187 return; 188 189 _kmode = SetKMode(1); 190 191 // Cache 192 reg = VOLATILE_REF(CCR); 193 DPRINTF((TEXT("Cache "))); 194 if (reg & CCR_CE) 195 DPRINTF((TEXT("Enabled. %s-mode, P0/U0/P3 Write-%s, P1 Write-%s\n"), 196 reg & CCR_RA ? TEXT("RAM") : TEXT("normal"), 197 reg & CCR_WT ? TEXT("Through") : TEXT("Back"), 198 reg & CCR_CB ? TEXT("Back") : TEXT("Through"))); 199 else 200 DPRINTF((TEXT("Disabled.\n"))); 201 202 // MMU 203 reg = VOLATILE_REF(MMUCR); 204 DPRINTF((TEXT("MMU "))); 205 if (reg & MMUCR_AT) 206 DPRINTF((TEXT("Enabled. %s index-mode, %s virtual storage mode\n"), 207 reg & MMUCR_IX 208 ? TEXT("ASID + VPN") : TEXT("VPN only"), 209 reg & MMUCR_SV ? TEXT("single") : TEXT("multiple"))); 210 else 211 DPRINTF((TEXT("Disabled.\n"))); 212 213 // Status register 214 reg = 0; 215 __asm("stc sr, r0\n" 216 "mov.l r0, @r4", ®); 217 DPRINTF((TEXT("SR 0x%08x\n"), reg)); 218 219 // BSC 220 bsc_dump(); 221 222 // ICU 223 print_stack_pointer(); 224 icu_dump(); 225 226 // TMU 227 tmu_dump(); 228 229 // PFC , I/O port 230 pfc_dump(); 231 232 // SCIF 233 scif_dump(HPC_PREFERENCE.serial_speed); 234 235 // HD64461 236 platid_t platform; 237 platform.dw.dw0 = menu._pref.platid_hi; 238 platform.dw.dw1 = menu._pref.platid_lo; 239 hd64461_dump(platform); 240 241 SetKMode(_kmode); 242 } 243 244 void 245 SHArchitecture::icu_dump(void) 246 { 247 248 DPRINTF((TEXT("<<<Interrupt Controller>>>\n"))); 249 print_stack_pointer(); 250 251 DPRINTF((TEXT("ICR0 0x%08x\n"), reg_read_2(ICU_ICR0_REG16))); 252 DPRINTF((TEXT("ICR1 0x%08x\n"), reg_read_2(ICU_ICR1_REG16))); 253 DPRINTF((TEXT("ICR2 0x%08x\n"), reg_read_2(ICU_ICR2_REG16))); 254 DPRINTF((TEXT("PINTER 0x%08x\n"), reg_read_2(ICU_PINTER_REG16))); 255 DPRINTF((TEXT("IPRA 0x%08x\n"), reg_read_2(ICU_IPRA_REG16))); 256 DPRINTF((TEXT("IPRB 0x%08x\n"), reg_read_2(ICU_IPRB_REG16))); 257 DPRINTF((TEXT("IPRC 0x%08x\n"), reg_read_2(ICU_IPRC_REG16))); 258 DPRINTF((TEXT("IPRD 0x%08x\n"), reg_read_2(ICU_IPRD_REG16))); 259 DPRINTF((TEXT("IPRE 0x%08x\n"), reg_read_2(ICU_IPRE_REG16))); 260 DPRINTF((TEXT("IRR0 0x%08x\n"), reg_read_1(ICU_IRR0_REG8))); 261 DPRINTF((TEXT("IRR1 0x%08x\n"), reg_read_1(ICU_IRR1_REG8))); 262 DPRINTF((TEXT("IRR2 0x%08x\n"), reg_read_1(ICU_IRR2_REG8))); 263 icu_control(); 264 icu_priority(); 265 } 266 267 void 268 SHArchitecture::icu_priority(void) 269 { 270 struct intr_priority *tab; 271 272 DPRINTF((TEXT("----interrupt priority----\n"))); 273 for (tab = ipr_table; tab->name; tab++) { 274 DPRINTF((TEXT("%-10S %d\n"), tab->name, 275 (reg_read_2(tab->reg) >> tab->shift) & ICU_IPR_MASK)); 276 } 277 DPRINTF((TEXT("--------------------------\n"))); 278 } 279 280 void 281 SHArchitecture::icu_control(void) 282 { 283 const char *sense_select[] = { 284 "falling edge", 285 "raising edge", 286 "low level", 287 "reserved", 288 }; 289 u_int16_t r; 290 291 // PINT0-15 292 DPRINTF((TEXT("PINT enable(on |) :"))); 293 bitdisp(reg_read_2(ICU_PINTER_REG16)); 294 DPRINTF((TEXT("PINT detect(high |):"))); 295 bitdisp(reg_read_2(ICU_ICR2_REG16)); 296 // NMI 297 r = reg_read_2(ICU_ICR0_REG16); 298 DPRINTF((TEXT("NMI(%S %S-edge),"), 299 r & ICU_ICR0_NMIL ? "High" : "Low", 300 r & ICU_ICR0_NMIE ? "raising" : "falling")); 301 r = reg_read_2(ICU_ICR1_REG16); 302 DPRINTF((TEXT(" %S maskable,"), r & ICU_ICR1_MAI ? "" : "never")); 303 DPRINTF((TEXT(" SR.BL %S\n"), 304 r & ICU_ICR1_BLMSK ? "ignored" : "maskable")); 305 // IRQ0-5 306 DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"), 307 r & ICU_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]")); 308 if (r & ICU_ICR1_IRQLVL) { 309 DPRINTF((TEXT("IRLS[0:3] %S\n"), 310 r & ICU_ICR1_IRLSEN ? "enabled" : "disabled")); 311 } 312 // sense select 313 for (int i = 5; i >= 0; i--) { 314 DPRINTF((TEXT("IRQ[%d] %S\n"), i, 315 sense_select [ 316 (r >>(i * 2)) & ICU_SENSE_SELECT_MASK])); 317 } 318 } 319 320 SH_BOOT_FUNC_(7709); 321 SH_BOOT_FUNC_(7709A); 322 SH_BOOT_FUNC_(7750); 323 324 // 325 // Debug Functions. 326 // 327 void 328 SHArchitecture::bsc_dump() 329 { 330 331 DPRINTF((TEXT("<<<Bus State Controller>>>\n"))); 332 #define DUMP_BSC_REG(x) \ 333 DPRINTF((TEXT("%-8S"), #x)); \ 334 bitdisp(reg_read_2(SH3_BSC_##x##_REG)) 335 DUMP_BSC_REG(BCR1); 336 DUMP_BSC_REG(BCR2); 337 DUMP_BSC_REG(WCR1); 338 DUMP_BSC_REG(WCR2); 339 DUMP_BSC_REG(MCR); 340 DUMP_BSC_REG(DCR); 341 DUMP_BSC_REG(PCR); 342 DUMP_BSC_REG(RTCSR); 343 DUMP_BSC_REG(RTCNT); 344 DUMP_BSC_REG(RTCOR); 345 DUMP_BSC_REG(RFCR); 346 DUMP_BSC_REG(BCR3); 347 #undef DUMP_BSC_REG 348 } 349 350 void 351 SHArchitecture::scif_dump(int bps) 352 { 353 u_int16_t r16; 354 #ifdef SH4 355 u_int16_t r8; 356 #else 357 u_int8_t r8; 358 #endif 359 int n; 360 361 DPRINTF((TEXT("<<<SCIF>>>\n"))); 362 /* mode */ 363 r8 = SHREG_SCSMR2; 364 n = 1 <<((r8 & SCSMR2_CKS) << 1); 365 DPRINTF((TEXT("mode: %dbit %S-parity %d stop bit clock PCLOCK/%d\n"), 366 r8 & SCSMR2_CHR ? 7 : 8, 367 r8 & SCSMR2_PE ? r8 & SCSMR2_OE ? "odd" : "even" : "non", 368 r8 & SCSMR2_STOP ? 2 : 1, 369 n)); 370 /* bit rate */ 371 r8 = SHREG_SCBRR2; 372 DPRINTF((TEXT("SCBRR=%d(%dbps) estimated PCLOCK %dHz\n"), r8, bps, 373 32 * bps *(r8 + 1) * n)); 374 375 /* control */ 376 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSCR2_##m, #m) 377 DPRINTF((TEXT("SCSCR2: "))); 378 r8 = SHREG_SCSCR2; 379 DBG_BIT_PRINT(r8, TIE); 380 DBG_BIT_PRINT(r8, RIE); 381 DBG_BIT_PRINT(r8, TE); 382 DBG_BIT_PRINT(r8, RE); 383 DPRINTF((TEXT("CKE=%d\n"), r8 & SCSCR2_CKE)); 384 #undef DBG_BIT_PRINT 385 386 /* status */ 387 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCSSR2_##m, #m) 388 r16 = SHREG_SCSSR2; 389 DPRINTF((TEXT("SCSSR2: "))); 390 DBG_BIT_PRINT(r16, ER); 391 DBG_BIT_PRINT(r16, TEND); 392 DBG_BIT_PRINT(r16, TDFE); 393 DBG_BIT_PRINT(r16, BRK); 394 DBG_BIT_PRINT(r16, FER); 395 DBG_BIT_PRINT(r16, PER); 396 DBG_BIT_PRINT(r16, RDF); 397 DBG_BIT_PRINT(r16, DR); 398 #undef DBG_BIT_PRINT 399 400 /* FIFO control */ 401 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, SCFCR2_##m, #m) 402 r8 = SHREG_SCFCR2; 403 DPRINTF((TEXT("SCFCR2: "))); 404 DBG_BIT_PRINT(r8, RTRG1); 405 DBG_BIT_PRINT(r8, RTRG0); 406 DBG_BIT_PRINT(r8, TTRG1); 407 DBG_BIT_PRINT(r8, TTRG0); 408 DBG_BIT_PRINT(r8, MCE); 409 DBG_BIT_PRINT(r8, TFRST); 410 DBG_BIT_PRINT(r8, RFRST); 411 DBG_BIT_PRINT(r8, LOOP); 412 DPRINTF((TEXT("\n"))); 413 #undef DBG_BIT_PRINT 414 } 415 416 void 417 SHArchitecture::pfc_dump() 418 { 419 DPRINTF((TEXT("<<<Pin Function Controller>>>\n"))); 420 DPRINTF((TEXT("[control]\n"))); 421 #define DUMP_PFC_REG(x) \ 422 DPRINTF((TEXT("P%SCR :"), #x)); \ 423 bitdisp(reg_read_2(SH3_P##x##CR_REG16)) 424 DUMP_PFC_REG(A); 425 DUMP_PFC_REG(B); 426 DUMP_PFC_REG(C); 427 DUMP_PFC_REG(D); 428 DUMP_PFC_REG(E); 429 DUMP_PFC_REG(F); 430 DUMP_PFC_REG(G); 431 DUMP_PFC_REG(H); 432 DUMP_PFC_REG(J); 433 DUMP_PFC_REG(K); 434 DUMP_PFC_REG(L); 435 #undef DUMP_PFC_REG 436 DPRINTF((TEXT("SCPCR :"))); 437 bitdisp(reg_read_2(SH3_SCPCR_REG16)); 438 DPRINTF((TEXT("\n[data]\n"))); 439 #define DUMP_IOPORT_REG(x) \ 440 DPRINTF((TEXT("P%SDR :"), #x)); \ 441 bitdisp(reg_read_1(SH3_P##x##DR_REG8)) 442 DUMP_IOPORT_REG(A); 443 DUMP_IOPORT_REG(B); 444 DUMP_IOPORT_REG(C); 445 DUMP_IOPORT_REG(D); 446 DUMP_IOPORT_REG(E); 447 DUMP_IOPORT_REG(F); 448 DUMP_IOPORT_REG(G); 449 DUMP_IOPORT_REG(H); 450 DUMP_IOPORT_REG(J); 451 DUMP_IOPORT_REG(K); 452 DUMP_IOPORT_REG(L); 453 #undef DUMP_IOPORT_REG 454 DPRINTF((TEXT("SCPDR :"))); 455 bitdisp(reg_read_1(SH3_SCPDR_REG8)); 456 } 457 458 void 459 SHArchitecture::tmu_dump() 460 { 461 u_int8_t r8; 462 463 DPRINTF((TEXT("<<<TMU>>>\n"))); 464 /* Common */ 465 /* TOCR timer output control register */ 466 r8 = reg_read_1(SH3_TOCR_REG8); 467 DPRINTF((TEXT("TCLK = %S\n"), 468 r8 & TOCR_TCOE ? "RTC output" : "input")); 469 /* TSTR */ 470 r8 = reg_read_1(SH3_TSTR_REG8); 471 DPRINTF((TEXT("Timer start(#0:2) [%c][%c][%c]\n"), 472 r8 & TSTR_STR0 ? 'x' : '_', 473 r8 & TSTR_STR1 ? 'x' : '_', 474 r8 & TSTR_STR2 ? 'x' : '_')); 475 476 #define CHANNEL_DUMP(a, x) \ 477 tmu_channel_dump(x, SH##a##_TCOR##x##_REG, \ 478 SH##a##_TCNT##x##_REG, \ 479 SH##a##_TCR##x##_REG16) 480 CHANNEL_DUMP(3, 0); 481 CHANNEL_DUMP(3, 1); 482 CHANNEL_DUMP(3, 2); 483 #undef CHANNEL_DUMP 484 DPRINTF((TEXT("\n"))); 485 } 486 487 void 488 SHArchitecture::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt, 489 paddr_t tcr) 490 { 491 u_int32_t r32; 492 u_int16_t r16; 493 494 DPRINTF((TEXT("TMU#%d:"), unit)); 495 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, TCR_##m, #m) 496 /* TCR*/ 497 r16 = reg_read_2(tcr); 498 DBG_BIT_PRINT(r16, UNF); 499 DBG_BIT_PRINT(r16, UNIE); 500 DBG_BIT_PRINT(r16, CKEG1); 501 DBG_BIT_PRINT(r16, CKEG0); 502 DBG_BIT_PRINT(r16, TPSC2); 503 DBG_BIT_PRINT(r16, TPSC1); 504 DBG_BIT_PRINT(r16, TPSC0); 505 /* channel 2 has input capture. */ 506 if (unit == 2) { 507 DBG_BIT_PRINT(r16, ICPF); 508 DBG_BIT_PRINT(r16, ICPE1); 509 DBG_BIT_PRINT(r16, ICPE0); 510 } 511 #undef DBG_BIT_PRINT 512 /* TCNT0 timer counter */ 513 r32 = reg_read_4(tcnt); 514 DPRINTF((TEXT("\ncnt=0x%08x"), r32)); 515 /* TCOR0 timer constant register */ 516 r32 = reg_read_4(tcor); 517 DPRINTF((TEXT(" constant=0x%04x"), r32)); 518 519 if (unit == 2) 520 DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2_REG)); 521 else 522 DPRINTF((TEXT("\n"))); 523 } 524 525 void 526 SHArchitecture::hd64461_dump(platid_t &platform) 527 { 528 u_int16_t r16; 529 u_int8_t r8; 530 531 #define MATCH(p) \ 532 platid_match(&platform, &platid_mask_MACH_##p) 533 534 DPRINTF((TEXT("<<<HD64461>>>\n"))); 535 if (!MATCH(HP_LX) && 536 !MATCH(HP_JORNADA_6XX) && 537 !MATCH(HITACHI_PERSONA_HPW230JC)) { 538 DPRINTF((TEXT("don't exist."))); 539 return; 540 } 541 542 #if 0 543 DPRINTF((TEXT("frame buffer test start\n"))); 544 u_int8_t *fb = reinterpret_cast<u_int8_t *>(HD64461_FBBASE); 545 546 for (int i = 0; i < 320 * 240 * 2 / 8; i++) 547 *fb++ = 0xff; 548 DPRINTF((TEXT("frame buffer test end\n"))); 549 #endif 550 // System 551 DPRINTF((TEXT("STBCR (System Control Register)\n"))); 552 r16 = reg_read_2(HD64461_SYSSTBCR_REG16); 553 bitdisp(r16); 554 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m) 555 DBG_BIT_PRINT(r16, CKIO_STBY); 556 DBG_BIT_PRINT(r16, SAFECKE_IST); 557 DBG_BIT_PRINT(r16, SLCKE_IST); 558 DBG_BIT_PRINT(r16, SAFECKE_OST); 559 DBG_BIT_PRINT(r16, SLCKE_OST); 560 DBG_BIT_PRINT(r16, SMIAST); 561 DBG_BIT_PRINT(r16, SLCDST); 562 DBG_BIT_PRINT(r16, SPC0ST); 563 DBG_BIT_PRINT(r16, SPC1ST); 564 DBG_BIT_PRINT(r16, SAFEST); 565 DBG_BIT_PRINT(r16, STM0ST); 566 DBG_BIT_PRINT(r16, STM1ST); 567 DBG_BIT_PRINT(r16, SIRST); 568 DBG_BIT_PRINT(r16, SURTSD); 569 #undef DBG_BIT_PRINT 570 DPRINTF((TEXT("\n"))); 571 572 DPRINTF((TEXT("SYSCR (System Configuration Register)\n"))); 573 r16 = reg_read_2(HD64461_SYSSYSCR_REG16); 574 bitdisp(r16); 575 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m) 576 DBG_BIT_PRINT(r16, SCPU_BUS_IGAT); 577 DBG_BIT_PRINT(r16, SPTA_IR); 578 DBG_BIT_PRINT(r16, SPTA_TM); 579 DBG_BIT_PRINT(r16, SPTB_UR); 580 DBG_BIT_PRINT(r16, WAIT_CTL_SEL); 581 DBG_BIT_PRINT(r16, SMODE1); 582 DBG_BIT_PRINT(r16, SMODE0); 583 #undef DBG_BIT_PRINT 584 DPRINTF((TEXT("\n"))); 585 586 DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n"))); 587 r16 = reg_read_2(HD64461_SYSSCPUCR_REG16); 588 bitdisp(r16); 589 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m) 590 DBG_BIT_PRINT(r16, SPDSTOF); 591 DBG_BIT_PRINT(r16, SPDSTIG); 592 DBG_BIT_PRINT(r16, SPCSTOF); 593 DBG_BIT_PRINT(r16, SPCSTIG); 594 DBG_BIT_PRINT(r16, SPBSTOF); 595 DBG_BIT_PRINT(r16, SPBSTIG); 596 DBG_BIT_PRINT(r16, SPASTOF); 597 DBG_BIT_PRINT(r16, SPASTIG); 598 DBG_BIT_PRINT(r16, SLCDSTIG); 599 DBG_BIT_PRINT(r16, SCPU_CS56_EP); 600 DBG_BIT_PRINT(r16, SCPU_CMD_EP); 601 DBG_BIT_PRINT(r16, SCPU_ADDR_EP); 602 DBG_BIT_PRINT(r16, SCPDPU); 603 DBG_BIT_PRINT(r16, SCPU_A2319_EP); 604 #undef DBG_BIT_PRINT 605 DPRINTF((TEXT("\n"))); 606 607 DPRINTF((TEXT("\n"))); 608 609 // INTC 610 DPRINTF((TEXT("NIRR (Interrupt Request Register)\n"))); 611 r16 = reg_read_2(HD64461_INTCNIRR_REG16); 612 bitdisp(r16); 613 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m) 614 DBG_BIT_PRINT(r16, PCC0R); 615 DBG_BIT_PRINT(r16, PCC1R); 616 DBG_BIT_PRINT(r16, AFER); 617 DBG_BIT_PRINT(r16, GPIOR); 618 DBG_BIT_PRINT(r16, TMU0R); 619 DBG_BIT_PRINT(r16, TMU1R); 620 DBG_BIT_PRINT(r16, IRDAR); 621 DBG_BIT_PRINT(r16, UARTR); 622 #undef DBG_BIT_PRINT 623 DPRINTF((TEXT("\n"))); 624 625 DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n"))); 626 r16 = reg_read_2(HD64461_INTCNIMR_REG16); 627 bitdisp(r16); 628 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m) 629 DBG_BIT_PRINT(r16, PCC0M); 630 DBG_BIT_PRINT(r16, PCC1M); 631 DBG_BIT_PRINT(r16, AFEM); 632 DBG_BIT_PRINT(r16, GPIOM); 633 DBG_BIT_PRINT(r16, TMU0M); 634 DBG_BIT_PRINT(r16, TMU1M); 635 DBG_BIT_PRINT(r16, IRDAM); 636 DBG_BIT_PRINT(r16, UARTM); 637 #undef DBG_BIT_PRINT 638 DPRINTF((TEXT("\n"))); 639 640 DPRINTF((TEXT("\n"))); 641 642 // PCMCIA 643 // PCC0 644 DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n"))); 645 DPRINTF((TEXT("PCC0 Interface Status Register\n"))); 646 r8 = reg_read_1(HD64461_PCC0ISR_REG8); 647 bitdisp(r8); 648 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m) 649 DBG_BIT_PRINT(r8, P0READY); 650 DBG_BIT_PRINT(r8, P0MWP); 651 DBG_BIT_PRINT(r8, P0VS2); 652 DBG_BIT_PRINT(r8, P0VS1); 653 DBG_BIT_PRINT(r8, P0CD2); 654 DBG_BIT_PRINT(r8, P0CD1); 655 DBG_BIT_PRINT(r8, P0BVD2); 656 DBG_BIT_PRINT(r8, P0BVD1); 657 #undef DBG_BIT_PRINT 658 DPRINTF((TEXT("\n"))); 659 660 DPRINTF((TEXT("PCC0 General Control Register\n"))); 661 r8 = reg_read_1(HD64461_PCC0GCR_REG8); 662 bitdisp(r8); 663 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m) 664 DBG_BIT_PRINT(r8, P0DRVE); 665 DBG_BIT_PRINT(r8, P0PCCR); 666 DBG_BIT_PRINT(r8, P0PCCT); 667 DBG_BIT_PRINT(r8, P0VCC0); 668 DBG_BIT_PRINT(r8, P0MMOD); 669 DBG_BIT_PRINT(r8, P0PA25); 670 DBG_BIT_PRINT(r8, P0PA24); 671 DBG_BIT_PRINT(r8, P0REG); 672 #undef DBG_BIT_PRINT 673 DPRINTF((TEXT("\n"))); 674 675 DPRINTF((TEXT("PCC0 Card Status Change Register\n"))); 676 r8 = reg_read_1(HD64461_PCC0CSCR_REG8); 677 bitdisp(r8); 678 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m) 679 DBG_BIT_PRINT(r8, P0SCDI); 680 DBG_BIT_PRINT(r8, P0IREQ); 681 DBG_BIT_PRINT(r8, P0SC); 682 DBG_BIT_PRINT(r8, P0CDC); 683 DBG_BIT_PRINT(r8, P0RC); 684 DBG_BIT_PRINT(r8, P0BW); 685 DBG_BIT_PRINT(r8, P0BD); 686 #undef DBG_BIT_PRINT 687 DPRINTF((TEXT("\n"))); 688 689 DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n"))); 690 r8 = reg_read_1(HD64461_PCC0CSCIER_REG8); 691 bitdisp(r8); 692 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m) 693 DBG_BIT_PRINT(r8, P0CRE); 694 DBG_BIT_PRINT(r8, P0SCE); 695 DBG_BIT_PRINT(r8, P0CDE); 696 DBG_BIT_PRINT(r8, P0RE); 697 DBG_BIT_PRINT(r8, P0BWE); 698 DBG_BIT_PRINT(r8, P0BDE); 699 #undef DBG_BIT_PRINT 700 DPRINTF((TEXT("\ninterrupt type: "))); 701 switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) { 702 case HD64461_PCC0CSCIER_P0IREQE_NONE: 703 DPRINTF((TEXT("none\n"))); 704 break; 705 case HD64461_PCC0CSCIER_P0IREQE_LEVEL: 706 DPRINTF((TEXT("level\n"))); 707 break; 708 case HD64461_PCC0CSCIER_P0IREQE_FEDGE: 709 DPRINTF((TEXT("falling edge\n"))); 710 break; 711 case HD64461_PCC0CSCIER_P0IREQE_REDGE: 712 DPRINTF((TEXT("rising edge\n"))); 713 break; 714 } 715 716 DPRINTF((TEXT("PCC0 Software Control Register\n"))); 717 r8 = reg_read_1(HD64461_PCC0SCR_REG8); 718 bitdisp(r8); 719 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m) 720 DBG_BIT_PRINT(r8, P0VCC1); 721 DBG_BIT_PRINT(r8, P0SWP); 722 #undef DBG_BIT_PRINT 723 DPRINTF((TEXT("\n"))); 724 725 // PCC1 726 DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n"))); 727 DPRINTF((TEXT("PCC1 Interface Status Register\n"))); 728 r8 = reg_read_1(HD64461_PCC1ISR_REG8); 729 bitdisp(r8); 730 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m) 731 DBG_BIT_PRINT(r8, P1READY); 732 DBG_BIT_PRINT(r8, P1MWP); 733 DBG_BIT_PRINT(r8, P1VS2); 734 DBG_BIT_PRINT(r8, P1VS1); 735 DBG_BIT_PRINT(r8, P1CD2); 736 DBG_BIT_PRINT(r8, P1CD1); 737 DBG_BIT_PRINT(r8, P1BVD2); 738 DBG_BIT_PRINT(r8, P1BVD1); 739 #undef DBG_BIT_PRINT 740 DPRINTF((TEXT("\n"))); 741 742 DPRINTF((TEXT("PCC1 General Contorol Register\n"))); 743 r8 = reg_read_1(HD64461_PCC1GCR_REG8); 744 bitdisp(r8); 745 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m) 746 DBG_BIT_PRINT(r8, P1DRVE); 747 DBG_BIT_PRINT(r8, P1PCCR); 748 DBG_BIT_PRINT(r8, P1VCC0); 749 DBG_BIT_PRINT(r8, P1MMOD); 750 DBG_BIT_PRINT(r8, P1PA25); 751 DBG_BIT_PRINT(r8, P1PA24); 752 DBG_BIT_PRINT(r8, P1REG); 753 #undef DBG_BIT_PRINT 754 DPRINTF((TEXT("\n"))); 755 756 DPRINTF((TEXT("PCC1 Card Status Change Register\n"))); 757 r8 = reg_read_1(HD64461_PCC1CSCR_REG8); 758 bitdisp(r8); 759 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m) 760 DBG_BIT_PRINT(r8, P1SCDI); 761 DBG_BIT_PRINT(r8, P1CDC); 762 DBG_BIT_PRINT(r8, P1RC); 763 DBG_BIT_PRINT(r8, P1BW); 764 DBG_BIT_PRINT(r8, P1BD); 765 #undef DBG_BIT_PRINT 766 DPRINTF((TEXT("\n"))); 767 768 DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n"))); 769 r8 = reg_read_1(HD64461_PCC1CSCIER_REG8); 770 bitdisp(r8); 771 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m) 772 DBG_BIT_PRINT(r8, P1CRE); 773 DBG_BIT_PRINT(r8, P1CDE); 774 DBG_BIT_PRINT(r8, P1RE); 775 DBG_BIT_PRINT(r8, P1BWE); 776 DBG_BIT_PRINT(r8, P1BDE); 777 #undef DBG_BIT_PRINT 778 DPRINTF((TEXT("\n"))); 779 780 DPRINTF((TEXT("PCC1 Software Control Register\n"))); 781 r8 = reg_read_1(HD64461_PCC1SCR_REG8); 782 bitdisp(r8); 783 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m) 784 DBG_BIT_PRINT(r8, P1VCC1); 785 DBG_BIT_PRINT(r8, P1SWP); 786 #undef DBG_BIT_PRINT 787 DPRINTF((TEXT("\n"))); 788 789 // General Control 790 DPRINTF((TEXT("[General Control]\n"))); 791 DPRINTF((TEXT("PCC0 Output pins Control Register\n"))); 792 r8 = reg_read_1(HD64461_PCCP0OCR_REG8); 793 bitdisp(r8); 794 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m) 795 DBG_BIT_PRINT(r8, P0DEPLUP); 796 DBG_BIT_PRINT(r8, P0AEPLUP); 797 #undef DBG_BIT_PRINT 798 DPRINTF((TEXT("\n"))); 799 800 DPRINTF((TEXT("PCC1 Output pins Control Register\n"))); 801 r8 = reg_read_1(HD64461_PCCP1OCR_REG8); 802 bitdisp(r8); 803 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m) 804 DBG_BIT_PRINT(r8, P1RST8MA); 805 DBG_BIT_PRINT(r8, P1RST4MA); 806 DBG_BIT_PRINT(r8, P1RAS8MA); 807 DBG_BIT_PRINT(r8, P1RAS4MA); 808 #undef DBG_BIT_PRINT 809 DPRINTF((TEXT("\n"))); 810 811 DPRINTF((TEXT("PC Card General Control Register\n"))); 812 r8 = reg_read_1(HD64461_PCCPGCR_REG8); 813 bitdisp(r8); 814 #define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m) 815 DBG_BIT_PRINT(r8, PSSDIR); 816 DBG_BIT_PRINT(r8, PSSRDWR); 817 #undef DBG_BIT_PRINT 818 DPRINTF((TEXT("\n"))); 819 820 // GPIO 821 #define GPIO_DUMP_REG8(x) \ 822 bitdisp(reg_read_1(HD64461_GPA##x##R_REG16)); \ 823 bitdisp(reg_read_1(HD64461_GPB##x##R_REG16)); \ 824 bitdisp(reg_read_1(HD64461_GPC##x##R_REG16)); \ 825 bitdisp(reg_read_1(HD64461_GPD##x##R_REG16)) 826 #define GPIO_DUMP_REG16(x) \ 827 bitdisp(reg_read_2(HD64461_GPA##x##R_REG16)); \ 828 bitdisp(reg_read_2(HD64461_GPB##x##R_REG16)); \ 829 bitdisp(reg_read_2(HD64461_GPC##x##R_REG16)); \ 830 bitdisp(reg_read_2(HD64461_GPD##x##R_REG16)) 831 832 DPRINTF((TEXT("GPIO Port Control Register\n"))); 833 GPIO_DUMP_REG16(C); 834 DPRINTF((TEXT("GPIO Port Data Register\n"))); 835 GPIO_DUMP_REG8(D); 836 DPRINTF((TEXT("GPIO Port Interrupt Control Register\n"))); 837 GPIO_DUMP_REG8(IC); 838 DPRINTF((TEXT("GPIO Port Interrupt Status Register\n"))); 839 GPIO_DUMP_REG8(IS); 840 } 841 842 #ifdef SH7709TEST 843 u_int32_t sh7707_fb_dma_addr; 844 u_int16_t val; 845 int s; 846 847 s = suspendIntr(); 848 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR0; 849 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 850 sh7707_fb_dma_addr = val; 851 VOLATILE_REF16(SH7707_LCDAR_REG16) = SH7707_LCDAR_LCDDMR1; 852 val = VOLATILE_REF16(SH7707_LCDDMR_REG16); 853 sh7707_fb_dma_addr |= (val << 16); 854 resumeIntr(s); 855 856 DPRINTF((TEXT("SH7707 frame buffer dma address: 0x%08x\n"), 857 sh7707_fb_dma_addr)); 858 #endif 859
Indexes created Tue Sep 23 22:09:46 GMT 2025