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sh_arch.cpp revision 1.7.8.2 
      1 /*	$NetBSD: sh_arch.cpp,v 1.7.8.2 2002/02/28 04:09:46 nathanw Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #include <hpcboot.h>
     40 #include <hpcmenu.h>
     41 #include <sh3/sh_arch.h>
     42 
     43 SH_BOOT_FUNC_(7709);
     44 SH_BOOT_FUNC_(7709A);
     45 SH_BOOT_FUNC_(7750);
     46 
     47 static int _cpu_type;
     48 
     49 int
     50 SHArchitecture::cpu_type()
     51 {
     52 	if (_cpu_type == 0) {
     53 		SYSTEM_INFO si;
     54 		GetSystemInfo(&si);
     55 		_cpu_type = si.wProcessorLevel;
     56 	}
     57 
     58 	return _cpu_type;
     59 }
     60 
     61 BOOL
     62 SHArchitecture::init()
     63 {
     64 
     65 	if (!_mem->init()) {
     66 		DPRINTF((TEXT("can't initialize memory manager.\n")));
     67 		return FALSE;
     68 	}
     69 	// D-RAM information
     70 	DPRINTF((TEXT("Memory Bank:\n")));
     71 
     72 	return TRUE;
     73 }
     74 
     75 void
     76 SHArchitecture::systemInfo()
     77 {
     78 
     79 	// Windows CE common infomation.
     80 	super::systemInfo();
     81 
     82 	// CPU specific.
     83 	_dev->dump(HPC_MENU._cons_parameter);
     84 }
     85 
     86 BOOL
     87 SHArchitecture::setupLoader()
     88 {
     89 	vaddr_t v;
     90 
     91 	if (!_mem->getPage(v , _loader_addr)) {
     92 		DPRINTF((TEXT("can't get page for 2nd loader.\n")));
     93 		return FALSE;
     94 	}
     95 	_loader_addr = ptokv(_loader_addr);
     96 
     97 	DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"),
     98 	    (unsigned)v,(unsigned)_loader_addr));
     99 
    100 	memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize());
    101 
    102 	return TRUE;
    103 }
    104 
    105 void
    106 SHArchitecture::jump(paddr_t info, paddr_t pvec)
    107 {
    108 	kaddr_t sp;
    109 	vaddr_t v;
    110 	paddr_t p;
    111 
    112 	// stack for bootloader
    113 	_mem->getPage(v, p);
    114 	sp = ptokv(p + _mem->getPageSize() / 2);
    115 
    116 	info = ptokv(info);
    117 	pvec = ptokv(pvec);
    118 
    119 	DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"),
    120 	    info, sp));
    121 
    122 	// Change to privilege-mode.
    123 	SetKMode(1);
    124 
    125 	// Cache flush(for 2nd bootloader)
    126 	//
    127 	// SH4 uses WinCE CacheSync(). this routine may causes TLB
    128 	// exception. so calls before suspendIntr().
    129 	//
    130 	cache_flush();
    131 
    132 	// Disable external interrupt.
    133 	suspendIntr();
    134 
    135 	// jump to 2nd loader.(run P1) at this time I still use MMU.
    136 	__asm(
    137 	    "mov	r6, r15\n"
    138 	    "jmp	@r7\n"
    139 	    "nop	\n", info, pvec, sp, _loader_addr);
    140 	// NOTREACHED
    141 }
    142 
    143 // disable external interrupt and save its priority.
    144 u_int32_t
    145 suspendIntr()
    146 {
    147 	u_int32_t sr;
    148 
    149 	__asm(
    150 	    "stc	sr, r0\n"
    151 	    "mov.l	r0, @r4\n"
    152 	    "or		r5, r0\n"
    153 	    "ldc	r0, sr\n", &sr, 0x000000f0);
    154 	return sr & 0x000000f0;
    155 }
    156 
    157 // resume external interrupt priority.
    158 void
    159 resumeIntr(u_int32_t s)
    160 {
    161 
    162 	__asm(
    163 	    "stc	sr, r0\n"
    164 	    "and	r5, r0\n"
    165 	    "or		r4, r0\n"
    166 	    "ldc	r0, sr\n", s, 0xffffff0f);
    167 }
    168