sh_arch.h revision 1.10.2.2
1 1.10.2.2 uwe /* -*-C++-*- $NetBSD: sh_arch.h,v 1.10.2.2 2006/03/05 04:05:40 uwe Exp $ */ 2 1.10.2.2 uwe 3 1.10.2.2 uwe /*- 4 1.10.2.2 uwe * Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc. 5 1.10.2.2 uwe * All rights reserved. 6 1.10.2.2 uwe * 7 1.10.2.2 uwe * This code is derived from software contributed to The NetBSD Foundation 8 1.10.2.2 uwe * by UCHIYAMA Yasushi. 9 1.10.2.2 uwe * 10 1.10.2.2 uwe * Redistribution and use in source and binary forms, with or without 11 1.10.2.2 uwe * modification, are permitted provided that the following conditions 12 1.10.2.2 uwe * are met: 13 1.10.2.2 uwe * 1. Redistributions of source code must retain the above copyright 14 1.10.2.2 uwe * notice, this list of conditions and the following disclaimer. 15 1.10.2.2 uwe * 2. Redistributions in binary form must reproduce the above copyright 16 1.10.2.2 uwe * notice, this list of conditions and the following disclaimer in the 17 1.10.2.2 uwe * documentation and/or other materials provided with the distribution. 18 1.10.2.2 uwe * 3. All advertising materials mentioning features or use of this software 19 1.10.2.2 uwe * must display the following acknowledgement: 20 1.10.2.2 uwe * This product includes software developed by the NetBSD 21 1.10.2.2 uwe * Foundation, Inc. and its contributors. 22 1.10.2.2 uwe * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.10.2.2 uwe * contributors may be used to endorse or promote products derived 24 1.10.2.2 uwe * from this software without specific prior written permission. 25 1.10.2.2 uwe * 26 1.10.2.2 uwe * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.10.2.2 uwe * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.10.2.2 uwe * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.10.2.2 uwe * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.10.2.2 uwe * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.10.2.2 uwe * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.10.2.2 uwe * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.10.2.2 uwe * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.10.2.2 uwe * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.10.2.2 uwe * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.10.2.2 uwe * POSSIBILITY OF SUCH DAMAGE. 37 1.10.2.2 uwe */ 38 1.10.2.2 uwe 39 1.10.2.2 uwe #ifndef _HPCBOOT_SH_ARCH_H_ 40 1.10.2.2 uwe #define _HPCBOOT_SH_ARCH_H_ 41 1.10.2.2 uwe 42 1.10.2.2 uwe #include <arch.h> 43 1.10.2.2 uwe #include <memory.h> // loadBank 44 1.10.2.2 uwe #include <console.h> // DPRINTF 45 1.10.2.2 uwe 46 1.10.2.2 uwe #include <sh3/dev/sh_dev.h> 47 1.10.2.2 uwe 48 1.10.2.2 uwe // CPU specific macro 49 1.10.2.2 uwe #include <sh3/cpu/sh3.h> 50 1.10.2.2 uwe #include <sh3/cpu/sh4.h> 51 1.10.2.2 uwe 52 1.10.2.2 uwe class SHArchitecture : public Architecture { 53 1.10.2.2 uwe protected: 54 1.10.2.2 uwe typedef void(*boot_func_t)(struct BootArgs *, struct PageTag *); 55 1.10.2.2 uwe SHdev *_dev; 56 1.10.2.2 uwe 57 1.10.2.2 uwe private: 58 1.10.2.2 uwe typedef Architecture super; 59 1.10.2.2 uwe boot_func_t _boot_func; 60 1.10.2.2 uwe 61 1.10.2.2 uwe protected: 62 1.10.2.2 uwe // should be created as actual product insntnce. not public. 63 1.10.2.2 uwe SHArchitecture(Console *&cons, MemoryManager *&mem, boot_func_t bootfunc) 64 1.10.2.2 uwe : _boot_func(bootfunc), Architecture(cons, mem) { 65 1.10.2.2 uwe // NO-OP 66 1.10.2.2 uwe } 67 1.10.2.2 uwe virtual ~SHArchitecture(void) { /* NO-OP */ } 68 1.10.2.2 uwe virtual void cache_flush(void) = 0; 69 1.10.2.2 uwe 70 1.10.2.2 uwe public: 71 1.10.2.2 uwe virtual BOOL init(void); 72 1.10.2.2 uwe virtual BOOL setupLoader(void); 73 1.10.2.2 uwe virtual void systemInfo(void); 74 1.10.2.2 uwe virtual void jump(kaddr_t info, kaddr_t pvce); 75 1.10.2.2 uwe 76 1.10.2.2 uwe // returns host machines CPU type. 3 for SH3. 4 for SH4 77 1.10.2.2 uwe static int cpu_type(void); 78 1.10.2.2 uwe }; 79 1.10.2.2 uwe 80 1.10.2.2 uwe // 81 1.10.2.2 uwe // SH product. setup cache flush routine and 2nd-bootloader. 82 1.10.2.2 uwe // 83 1.10.2.2 uwe 84 1.10.2.2 uwe // 85 1.10.2.2 uwe // SH3 series. 86 1.10.2.2 uwe /// 87 1.10.2.2 uwe #define SH_(x) \ 88 1.10.2.2 uwe class SH ## x : public SHArchitecture { \ 89 1.10.2.2 uwe private: \ 90 1.10.2.2 uwe typedef SHArchitecture super; \ 91 1.10.2.2 uwe public: \ 92 1.10.2.2 uwe SH ## x(Console *&cons, MemoryManager *&mem, boot_func_t bootfunc)\ 93 1.10.2.2 uwe : SHArchitecture(cons, mem, bootfunc) { \ 94 1.10.2.2 uwe DPRINTF((TEXT("CPU: SH") TEXT(#x) TEXT("\n"))); \ 95 1.10.2.2 uwe _dev = new SH3dev; \ 96 1.10.2.2 uwe } \ 97 1.10.2.2 uwe ~SH ## x(void) { \ 98 1.10.2.2 uwe delete _dev; \ 99 1.10.2.2 uwe } \ 100 1.10.2.2 uwe \ 101 1.10.2.2 uwe virtual BOOL init(void) { \ 102 1.10.2.2 uwe int sz; \ 103 1.10.2.2 uwe \ 104 1.10.2.2 uwe if (!super::init()) \ 105 1.10.2.2 uwe return FALSE; \ 106 1.10.2.2 uwe /* SH7709, SH7709A split AREA3 to two area. */ \ 107 1.10.2.2 uwe sz = SH_AREA_SIZE / 2; \ 108 1.10.2.2 uwe _mem->loadBank(SH_AREA3_START, sz); \ 109 1.10.2.2 uwe _mem->loadBank(SH_AREA3_START + sz , sz); \ 110 1.10.2.2 uwe return TRUE; \ 111 1.10.2.2 uwe } \ 112 1.10.2.2 uwe \ 113 1.10.2.2 uwe virtual void cache_flush(void) { \ 114 1.10.2.2 uwe SH ## x ## _CACHE_FLUSH(); \ 115 1.10.2.2 uwe } \ 116 1.10.2.2 uwe \ 117 1.10.2.2 uwe static void boot_func(struct BootArgs *, struct PageTag *); \ 118 1.10.2.2 uwe } 119 1.10.2.2 uwe 120 1.10.2.2 uwe SH_(7709); 121 1.10.2.2 uwe SH_(7709A); 122 1.10.2.2 uwe SH_(7707); 123 1.10.2.2 uwe 124 1.10.2.2 uwe // 125 1.10.2.2 uwe // SH4 series. 126 1.10.2.2 uwe /// 127 1.10.2.2 uwe class SH7750 : public SHArchitecture { 128 1.10.2.2 uwe private: 129 1.10.2.2 uwe typedef SHArchitecture super; 130 1.10.2.2 uwe 131 1.10.2.2 uwe public: 132 1.10.2.2 uwe SH7750(Console *&cons, MemoryManager *&mem, boot_func_t bootfunc) 133 1.10.2.2 uwe : SHArchitecture(cons, mem, bootfunc) { 134 1.10.2.2 uwe DPRINTF((TEXT("CPU: SH7750\n"))); 135 1.10.2.2 uwe _dev = new SH4dev; 136 1.10.2.2 uwe } 137 1.10.2.2 uwe ~SH7750(void) { 138 1.10.2.2 uwe delete _dev; 139 1.10.2.2 uwe } 140 1.10.2.2 uwe 141 1.10.2.2 uwe virtual BOOL init(void) { 142 1.10.2.2 uwe 143 1.10.2.2 uwe if (!super::init()) 144 1.10.2.2 uwe return FALSE; 145 1.10.2.2 uwe _mem->loadBank(SH_AREA3_START, SH_AREA_SIZE); 146 1.10.2.2 uwe 147 1.10.2.2 uwe return TRUE; 148 1.10.2.2 uwe } 149 1.10.2.2 uwe 150 1.10.2.2 uwe virtual void cache_flush(void) { 151 1.10.2.2 uwe // 152 1.10.2.2 uwe // To invalidate I-cache, program must run on P2. I can't 153 1.10.2.2 uwe // do it myself, use WinCE API. (WCE2.10 or later) 154 1.10.2.2 uwe // 155 1.10.2.2 uwe CacheSync(CACHE_D_WBINV); 156 1.10.2.2 uwe CacheSync(CACHE_I_INV); 157 1.10.2.2 uwe } 158 1.10.2.2 uwe 159 1.10.2.2 uwe virtual BOOL setupLoader(void) { 160 1.10.2.2 uwe // 161 1.10.2.2 uwe // 2nd boot loader access cache address array. run on P2. 162 1.10.2.2 uwe // 163 1.10.2.2 uwe if (super::setupLoader()) { 164 1.10.2.2 uwe (uint32_t)_loader_addr |= 0x20000000; 165 1.10.2.2 uwe DPRINTF 166 1.10.2.2 uwe ((TEXT("loader address moved to P2-area 0x%08x\n"), 167 1.10.2.2 uwe (unsigned)_loader_addr)); 168 1.10.2.2 uwe return TRUE; 169 1.10.2.2 uwe } 170 1.10.2.2 uwe 171 1.10.2.2 uwe return FALSE; 172 1.10.2.2 uwe } 173 1.10.2.2 uwe 174 1.10.2.2 uwe static void boot_func(struct BootArgs *, struct PageTag *); 175 1.10.2.2 uwe }; 176 1.10.2.2 uwe 177 1.10.2.2 uwe // 178 1.10.2.2 uwe // 2nd-bootloader. make sure that PIC and its size is lower than page size. 179 1.10.2.2 uwe // and can't call subroutine. 180 1.10.2.2 uwe // 181 1.10.2.2 uwe #define SH_BOOT_FUNC_(x) \ 182 1.10.2.2 uwe void \ 183 1.10.2.2 uwe SH##x##::boot_func(struct BootArgs *bi, struct PageTag *p) \ 184 1.10.2.2 uwe { \ 185 1.10.2.2 uwe /* Disable interrupt. block exception.(TLB exception don't occur) */ \ 186 1.10.2.2 uwe int tmp; \ 187 1.10.2.2 uwe __asm("stc sr, r5\n" \ 188 1.10.2.2 uwe "or r4, r5\n" \ 189 1.10.2.2 uwe "ldc r5, sr\n", 0x500000f0, tmp); \ 190 1.10.2.2 uwe /* Now I run on P1(P2 for SH4), TLB flush. and disable. */ \ 191 1.10.2.2 uwe \ 192 1.10.2.2 uwe SH ## x ## _MMU_DISABLE(); \ 193 1.10.2.2 uwe do { \ 194 1.10.2.2 uwe uint32_t *dst =(uint32_t *)p->dst; \ 195 1.10.2.2 uwe uint32_t *src =(uint32_t *)p->src; \ 196 1.10.2.2 uwe uint32_t sz = p->sz / sizeof (int); \ 197 1.10.2.2 uwe if (p->src == ~0) \ 198 1.10.2.2 uwe while (sz--) \ 199 1.10.2.2 uwe *dst++ = 0; \ 200 1.10.2.2 uwe else \ 201 1.10.2.2 uwe while (sz--) \ 202 1.10.2.2 uwe *dst++ = *src++; \ 203 1.10.2.2 uwe } while ((p =(struct PageTag *)p->next) != ~0); \ 204 1.10.2.2 uwe \ 205 1.10.2.2 uwe SH ## x ## _CACHE_FLUSH(); \ 206 1.10.2.2 uwe \ 207 1.10.2.2 uwe /* jump to kernel entry. */ \ 208 1.10.2.2 uwe __asm("jmp @r7\n" \ 209 1.10.2.2 uwe "nop\n", bi->argc, bi->argv, \ 210 1.10.2.2 uwe bi->bootinfo, bi->kernel_entry); \ 211 1.10.2.2 uwe } 212 1.10.2.2 uwe 213 1.10.2.2 uwe // suspend/resume external Interrupt. 214 1.10.2.2 uwe // (don't block) use under privilege mode. 215 1.10.2.2 uwe // 216 1.10.2.2 uwe __BEGIN_DECLS 217 1.10.2.2 uwe uint32_t suspendIntr(void); 218 1.10.2.2 uwe void resumeIntr(uint32_t); 219 1.10.2.2 uwe __END_DECLS 220 1.10.2.2 uwe 221 1.10.2.2 uwe #endif // _HPCBOOT_SH_ARCH_H_ 222
Indexes created Tue Sep 30 20:09:53 GMT 2025