1 1.19 thorpej /* $NetBSD: ipaq_atmelgpio.c,v 1.19 2023/12/20 14:50:02 thorpej Exp $ */ 2 1.1 ichiro 3 1.1 ichiro /*- 4 1.1 ichiro * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 1.1 ichiro * 6 1.1 ichiro * This code is derived from software contributed to The NetBSD Foundation 7 1.1 ichiro * by Ichiro FUKUHARA (ichiro (at) ichiro.org). 8 1.1 ichiro * 9 1.1 ichiro * Redistribution and use in source and binary forms, with or without 10 1.1 ichiro * modification, are permitted provided that the following conditions 11 1.1 ichiro * are met: 12 1.1 ichiro * 1. Redistributions of source code must retain the above copyright 13 1.1 ichiro * notice, this list of conditions and the following disclaimer. 14 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 ichiro * notice, this list of conditions and the following disclaimer in the 16 1.1 ichiro * documentation and/or other materials provided with the distribution. 17 1.1 ichiro * 18 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.1 ichiro * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.1 ichiro * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.1 ichiro * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.1 ichiro * POSSIBILITY OF SUCH DAMAGE. 29 1.1 ichiro */ 30 1.1 ichiro /* 31 1.1 ichiro * iPAQ uses Atmel microcontroller to service a few of peripheral devices. 32 1.1 ichiro * This controller connect to UART1 of SA11x0. 33 1.1 ichiro */ 34 1.6 lukem 35 1.6 lukem #include <sys/cdefs.h> 36 1.19 thorpej __KERNEL_RCSID(0, "$NetBSD: ipaq_atmelgpio.c,v 1.19 2023/12/20 14:50:02 thorpej Exp $"); 37 1.1 ichiro 38 1.1 ichiro #include <sys/param.h> 39 1.1 ichiro #include <sys/systm.h> 40 1.1 ichiro #include <sys/types.h> 41 1.1 ichiro #include <sys/conf.h> 42 1.1 ichiro #include <sys/file.h> 43 1.1 ichiro #include <sys/device.h> 44 1.1 ichiro #include <sys/kernel.h> 45 1.1 ichiro #include <sys/kthread.h> 46 1.16 dyoung #include <sys/bus.h> 47 1.1 ichiro 48 1.1 ichiro #include <hpcarm/dev/ipaq_saipvar.h> 49 1.1 ichiro #include <hpcarm/dev/ipaq_gpioreg.h> 50 1.1 ichiro #include <hpcarm/dev/ipaq_atmel.h> 51 1.2 ichiro #include <hpcarm/dev/ipaq_atmelvar.h> 52 1.11 peter 53 1.11 peter #include <arm/sa11x0/sa11x0_gpioreg.h> 54 1.11 peter #include <arm/sa11x0/sa11x0_comreg.h> 55 1.11 peter #include <arm/sa11x0/sa11x0_reg.h> 56 1.1 ichiro 57 1.2 ichiro #ifdef ATMEL_DEBUG 58 1.15 rjs #define DPRINTF(x) aprint_normal x 59 1.2 ichiro #else 60 1.2 ichiro #define DPRINTF(x) 61 1.2 ichiro #endif 62 1.1 ichiro 63 1.15 rjs static int atmelgpio_match(device_t, cfdata_t, void *); 64 1.15 rjs static void atmelgpio_attach(device_t, device_t, void *); 65 1.1 ichiro static int atmelgpio_print(void *, const char *); 66 1.15 rjs static int atmelgpio_search(device_t, cfdata_t, const int *, void *); 67 1.1 ichiro static void atmelgpio_init(struct atmelgpio_softc *); 68 1.1 ichiro 69 1.2 ichiro static void rxtx_data(struct atmelgpio_softc *, int, int, 70 1.10 peter uint8_t *, struct atmel_rx *); 71 1.2 ichiro 72 1.15 rjs CFATTACH_DECL_NEW(atmelgpio, sizeof(struct atmelgpio_softc), 73 1.5 thorpej atmelgpio_match, atmelgpio_attach, NULL, NULL); 74 1.1 ichiro 75 1.1 ichiro static int 76 1.15 rjs atmelgpio_match(device_t parent, cfdata_t cf, void *aux) 77 1.1 ichiro { 78 1.1 ichiro return (1); 79 1.1 ichiro } 80 1.1 ichiro 81 1.1 ichiro static void 82 1.15 rjs atmelgpio_attach(device_t parent, device_t self, void *aux) 83 1.1 ichiro { 84 1.15 rjs struct atmelgpio_softc *sc = device_private(self); 85 1.15 rjs struct ipaq_softc *psc = device_private(parent); 86 1.1 ichiro 87 1.11 peter struct atmel_rx rxbuf; 88 1.2 ichiro 89 1.15 rjs aprint_normal("\n"); 90 1.15 rjs aprint_normal_dev(self, "Atmel microcontroller GPIO\n"); 91 1.1 ichiro 92 1.1 ichiro sc->sc_iot = psc->sc_iot; 93 1.1 ichiro sc->sc_ioh = psc->sc_ioh; 94 1.15 rjs sc->sc_parent = psc; 95 1.1 ichiro 96 1.1 ichiro if (bus_space_map(sc->sc_iot, SACOM1_BASE, SACOM_NPORTS, 0, 97 1.1 ichiro &sc->sc_ioh)) { 98 1.15 rjs aprint_normal_dev(self, "unable to map of UART1 registers\n"); 99 1.1 ichiro return; 100 1.1 ichiro } 101 1.1 ichiro 102 1.1 ichiro atmelgpio_init(sc); 103 1.1 ichiro 104 1.12 rjs rxbuf.idx = 0; 105 1.12 rjs rxbuf.len = 0; 106 1.12 rjs 107 1.2 ichiro #if 1 /* this is sample */ 108 1.11 peter rxtx_data(sc, STATUS_BATTERY, 0, NULL, &rxbuf); 109 1.2 ichiro 110 1.15 rjs aprint_normal("ac_status = %x\n", rxbuf.data[0]); 111 1.15 rjs aprint_normal("Battery kind = %x\n", rxbuf.data[1]); 112 1.15 rjs aprint_normal("Voltage = %d mV\n", 113 1.11 peter 1000 * (rxbuf.data[3] << 8 | rxbuf.data[2]) /228); 114 1.15 rjs aprint_normal("Battery Status = %x\n", rxbuf.data[4]); 115 1.15 rjs aprint_normal("Battery percentage = %d\n", 116 1.11 peter 425 * (rxbuf.data[3] << 8 | rxbuf.data[2]) /1000 - 298); 117 1.2 ichiro #endif 118 1.2 ichiro 119 1.13 rjs rxtx_data(sc, READ_IIC, 0, NULL, &rxbuf); 120 1.13 rjs 121 1.1 ichiro /* 122 1.1 ichiro * Attach each devices 123 1.1 ichiro */ 124 1.1 ichiro 125 1.17 thorpej config_search(self, NULL, 126 1.18 thorpej CFARGS(.search = atmelgpio_search)); 127 1.1 ichiro } 128 1.1 ichiro 129 1.1 ichiro static int 130 1.15 rjs atmelgpio_search(device_t parent, cfdata_t cf, const int *ldesc, 131 1.13 rjs void *aux) 132 1.1 ichiro { 133 1.17 thorpej if (config_probe(parent, cf, NULL)) 134 1.18 thorpej config_attach(parent, cf, NULL, atmelgpio_print, CFARGS_NONE); 135 1.1 ichiro return 0; 136 1.1 ichiro } 137 1.1 ichiro 138 1.1 ichiro 139 1.1 ichiro static int 140 1.13 rjs atmelgpio_print(void *aux, const char *name) 141 1.1 ichiro { 142 1.1 ichiro return (UNCONF); 143 1.1 ichiro } 144 1.1 ichiro 145 1.1 ichiro static void 146 1.13 rjs atmelgpio_init(struct atmelgpio_softc *sc) 147 1.1 ichiro { 148 1.1 ichiro /* 8 bits no parity 1 stop bit */ 149 1.1 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACOM_CR0, CR0_DSS); 150 1.1 ichiro 151 1.1 ichiro /* Set baud rate 115k */ 152 1.1 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACOM_CR1, 0); 153 1.1 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACOM_CR2, SACOMSPEED(115200)); 154 1.2 ichiro 155 1.2 ichiro /* RX/TX enable, RX/TX FIFO interrupt enable */ 156 1.2 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACOM_CR3, 157 1.2 ichiro (CR3_RXE | CR3_TXE | CR3_RIE | CR3_TIE)); 158 1.2 ichiro } 159 1.2 ichiro 160 1.2 ichiro static void 161 1.13 rjs rxtx_data(struct atmelgpio_softc *sc, int id, int size, uint8_t *buf, 162 1.13 rjs struct atmel_rx *rxbuf) 163 1.2 ichiro { 164 1.2 ichiro int i, checksum, length, rx_data; 165 1.10 peter uint8_t data[MAX_SENDSIZE]; 166 1.2 ichiro 167 1.2 ichiro length = size + FRAME_OVERHEAD_SIZE; 168 1.2 ichiro 169 1.2 ichiro while (! (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACOM_SR0) & SR0_TFS)) 170 1.2 ichiro ; 171 1.2 ichiro 172 1.10 peter data[0] = (uint8_t)FRAME_SOF; 173 1.10 peter data[1] = (uint8_t)((id << 4) | size); 174 1.2 ichiro checksum = data[1]; 175 1.2 ichiro i = 2; 176 1.2 ichiro while (size--) { 177 1.2 ichiro data[i++] = *buf; 178 1.10 peter checksum += (uint8_t)(*buf++); 179 1.2 ichiro } 180 1.2 ichiro data[length-1] = checksum; 181 1.2 ichiro 182 1.2 ichiro while (! (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACOM_SR1) & SR1_TNF)) 183 1.2 ichiro ; 184 1.2 ichiro i = 0; 185 1.2 ichiro while (i < length) 186 1.2 ichiro bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACOM_DR, data[i++]); 187 1.2 ichiro 188 1.2 ichiro delay(10000); 189 1.2 ichiro #if 0 190 1.2 ichiro while (! (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACOM_SR0) & 191 1.2 ichiro (SR0_RID | SR0_RFS))) 192 1.2 ichiro #endif 193 1.2 ichiro rxbuf->state = STATE_SOF; 194 1.2 ichiro while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACOM_SR1) & SR1_RNE) { 195 1.2 ichiro 196 1.2 ichiro rx_data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACOM_DR); 197 1.2 ichiro DPRINTF(("DATA = %x\n", rx_data)); 198 1.2 ichiro 199 1.2 ichiro switch (rxbuf->state) { 200 1.2 ichiro case STATE_SOF: 201 1.2 ichiro if (rx_data == FRAME_SOF) 202 1.2 ichiro rxbuf->state = STATE_ID; 203 1.2 ichiro break; 204 1.2 ichiro case STATE_ID: 205 1.2 ichiro rxbuf->id = (rx_data & 0xf0) >> 4; 206 1.2 ichiro rxbuf->len = rx_data & 0x0f; 207 1.2 ichiro rxbuf->idx = 0; 208 1.2 ichiro rxbuf->checksum = rx_data; 209 1.2 ichiro rxbuf->state = (rxbuf->len > 0 ) ? STATE_DATA : STATE_EOF; 210 1.2 ichiro break; 211 1.2 ichiro case STATE_DATA: 212 1.2 ichiro rxbuf->checksum += rx_data; 213 1.2 ichiro rxbuf->data[rxbuf->idx] = rx_data; 214 1.2 ichiro if (++rxbuf->idx == rxbuf->len) 215 1.2 ichiro rxbuf->state = STATE_EOF; 216 1.2 ichiro break; 217 1.2 ichiro case STATE_EOF: 218 1.2 ichiro rxbuf->state = STATE_SOF; 219 1.2 ichiro if (rx_data == FRAME_EOF || rx_data == rxbuf->checksum) 220 1.2 ichiro DPRINTF(("frame EOF\n")); 221 1.2 ichiro else 222 1.2 ichiro DPRINTF(("BadFrame\n")); 223 1.2 ichiro break; 224 1.2 ichiro default: 225 1.2 ichiro break; 226 1.2 ichiro } 227 1.2 ichiro } 228 1.1 ichiro } 229