sacc_hpcarm.c revision 1.2 1 1.2 drochner /* $NetBSD: sacc_hpcarm.c,v 1.2 2005/06/30 17:03:53 drochner Exp $ */
2 1.1 bsh
3 1.1 bsh /*-
4 1.1 bsh * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 bsh * All rights reserved.
6 1.1 bsh *
7 1.1 bsh * This code is derived from software contributed to The NetBSD Foundation
8 1.1 bsh * by IWAMOTO Toshihiro.
9 1.1 bsh *
10 1.1 bsh * Redistribution and use in source and binary forms, with or without
11 1.1 bsh * modification, are permitted provided that the following conditions
12 1.1 bsh * are met:
13 1.1 bsh * 1. Redistributions of source code must retain the above copyright
14 1.1 bsh * notice, this list of conditions and the following disclaimer.
15 1.1 bsh * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 bsh * notice, this list of conditions and the following disclaimer in the
17 1.1 bsh * documentation and/or other materials provided with the distribution.
18 1.1 bsh * 3. All advertising materials mentioning features or use of this software
19 1.1 bsh * must display the following acknowledgement:
20 1.1 bsh * This product includes software developed by the NetBSD
21 1.1 bsh * Foundation, Inc. and its contributors.
22 1.1 bsh * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 bsh * contributors may be used to endorse or promote products derived
24 1.1 bsh * from this software without specific prior written permission.
25 1.1 bsh *
26 1.1 bsh * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 bsh * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 bsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 bsh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 bsh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 bsh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 bsh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 bsh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 bsh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 bsh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 bsh * POSSIBILITY OF SUCH DAMAGE.
37 1.1 bsh */
38 1.1 bsh
39 1.1 bsh /*
40 1.1 bsh * Platform dependent part for SA11[01]1 companion chip on hpcarm.
41 1.1 bsh */
42 1.1 bsh
43 1.1 bsh #include <sys/cdefs.h>
44 1.2 drochner __KERNEL_RCSID(0, "$NetBSD: sacc_hpcarm.c,v 1.2 2005/06/30 17:03:53 drochner Exp $");
45 1.1 bsh
46 1.1 bsh #include <sys/param.h>
47 1.1 bsh #include <sys/systm.h>
48 1.1 bsh #include <sys/types.h>
49 1.1 bsh #include <sys/conf.h>
50 1.1 bsh #include <sys/device.h>
51 1.1 bsh #include <sys/kernel.h>
52 1.1 bsh #include <sys/malloc.h>
53 1.1 bsh #include <sys/uio.h>
54 1.1 bsh
55 1.1 bsh #include <machine/bus.h>
56 1.1 bsh #include <machine/platid.h>
57 1.1 bsh #include <machine/platid_mask.h>
58 1.1 bsh
59 1.1 bsh #include <arm/sa11x0/sa11x0_reg.h>
60 1.1 bsh #include <arm/sa11x0/sa11x0_var.h>
61 1.1 bsh #include <arm/sa11x0/sa11x0_gpioreg.h>
62 1.1 bsh #include <arm/sa11x0/sa1111_reg.h>
63 1.1 bsh #include <arm/sa11x0/sa1111_var.h>
64 1.1 bsh
65 1.1 bsh #include "locators.h"
66 1.1 bsh
67 1.1 bsh static void sacc_attach(struct device *, struct device *, void *);
68 1.1 bsh static int sacc_intr(void *);
69 1.1 bsh
70 1.1 bsh struct platid_data sacc_platid_table[] = {
71 1.1 bsh { &platid_mask_MACH_HP_JORNADA_720, (void *)1 },
72 1.1 bsh { &platid_mask_MACH_HP_JORNADA_720JP, (void *)1 },
73 1.1 bsh { NULL, NULL }
74 1.1 bsh };
75 1.1 bsh
76 1.1 bsh CFATTACH_DECL(sacc, sizeof(struct sacc_softc),
77 1.1 bsh sacc_probe, sacc_attach, NULL, NULL);
78 1.1 bsh
79 1.1 bsh #ifdef INTR_DEBUG
80 1.1 bsh #define DPRINTF(arg) printf arg
81 1.1 bsh #else
82 1.1 bsh #define DPRINTF(arg)
83 1.1 bsh #endif
84 1.1 bsh
85 1.1 bsh static void
86 1.1 bsh sacc_attach(parent, self, aux)
87 1.1 bsh struct device *parent;
88 1.1 bsh struct device *self;
89 1.1 bsh void *aux;
90 1.1 bsh {
91 1.1 bsh int i, gpiopin;
92 1.1 bsh u_int32_t skid;
93 1.1 bsh struct sacc_softc *sc = (struct sacc_softc *)self;
94 1.1 bsh struct sa11x0_softc *psc = (struct sa11x0_softc *)parent;
95 1.1 bsh struct sa11x0_attach_args *sa = aux;
96 1.1 bsh struct platid_data *p;
97 1.1 bsh
98 1.1 bsh printf("\n");
99 1.1 bsh
100 1.1 bsh sc->sc_iot = sa->sa_iot;
101 1.1 bsh sc->sc_piot = psc->sc_iot;
102 1.1 bsh sc->sc_gpioh = psc->sc_gpioh;
103 1.1 bsh if ((p = platid_search_data(&platid, sacc_platid_table)) == NULL)
104 1.1 bsh return;
105 1.1 bsh
106 1.1 bsh gpiopin = (int) p->data;
107 1.1 bsh sc->sc_gpiomask = 1 << gpiopin;
108 1.1 bsh
109 1.1 bsh if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0,
110 1.1 bsh &sc->sc_ioh)) {
111 1.1 bsh printf("%s: unable to map registers\n", sc->sc_dev.dv_xname);
112 1.1 bsh return;
113 1.1 bsh }
114 1.1 bsh
115 1.1 bsh skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID);
116 1.1 bsh
117 1.1 bsh printf("%s: SA1111 rev %d.%d\n", sc->sc_dev.dv_xname,
118 1.1 bsh (skid & 0xf0) >> 3, skid & 0xf);
119 1.1 bsh
120 1.1 bsh for(i = 0; i < SACCIC_LEN; i++)
121 1.1 bsh sc->sc_intrhand[i] = NULL;
122 1.1 bsh
123 1.1 bsh /* initialize SA1111 interrupt controller */
124 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0);
125 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0);
126 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0);
127 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh,
128 1.1 bsh SACCIC_INTSTATCLR0, 0xffffffff);
129 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh,
130 1.1 bsh SACCIC_INTSTATCLR1, 0xffffffff);
131 1.1 bsh
132 1.1 bsh /* connect to SA1110's GPIO intr */
133 1.1 bsh sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc);
134 1.1 bsh
135 1.1 bsh /*
136 1.1 bsh * Attach each devices
137 1.1 bsh */
138 1.2 drochner config_search_ia(sa1111_search, self, "sacc", NULL);
139 1.1 bsh }
140 1.1 bsh
141 1.1 bsh static int
142 1.1 bsh sacc_intr(arg)
143 1.1 bsh void *arg;
144 1.1 bsh {
145 1.1 bsh int i;
146 1.1 bsh u_int32_t mask;
147 1.1 bsh struct sacc_intrvec intstat;
148 1.1 bsh struct sacc_softc *sc = arg;
149 1.1 bsh struct sacc_intrhand *ih;
150 1.1 bsh
151 1.1 bsh intstat.lo =
152 1.1 bsh bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0);
153 1.1 bsh intstat.hi =
154 1.1 bsh bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1);
155 1.1 bsh DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi));
156 1.1 bsh
157 1.1 bsh /* clear SA1110's GPIO intr status */
158 1.1 bsh bus_space_write_4(sc->sc_piot, sc->sc_gpioh,
159 1.1 bsh SAGPIO_EDR, sc->sc_gpiomask);
160 1.1 bsh
161 1.1 bsh for(i = 0, mask = 1; i < 32; i++, mask <<= 1)
162 1.1 bsh if (intstat.lo & mask) {
163 1.1 bsh /*
164 1.1 bsh * Clear intr status before calling intr handlers.
165 1.1 bsh * This cause stray interrupts, but clearing
166 1.1 bsh * after calling intr handlers cause intr lossage.
167 1.1 bsh */
168 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh,
169 1.1 bsh SACCIC_INTSTATCLR0, 1 << i);
170 1.1 bsh
171 1.1 bsh for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
172 1.1 bsh softintr_schedule(ih->ih_soft);
173 1.1 bsh }
174 1.1 bsh for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1)
175 1.1 bsh if (intstat.hi & mask) {
176 1.1 bsh bus_space_write_4(sc->sc_iot, sc->sc_ioh,
177 1.1 bsh SACCIC_INTSTATCLR1, 1 << i);
178 1.1 bsh for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
179 1.1 bsh softintr_schedule(ih->ih_soft);
180 1.1 bsh }
181 1.1 bsh return 1;
182 1.1 bsh }
183